2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (key
->force_dual_color_blend
&&
134 var
->data
.location
== FRAG_RESULT_DATA1
) {
135 this->dual_src_output
= reg
;
136 this->do_dual_src
= true;
137 } else if (var
->data
.index
> 0) {
138 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
139 assert(var
->data
.index
== 1);
140 this->dual_src_output
= reg
;
141 this->do_dual_src
= true;
142 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
143 /* Writing gl_FragColor outputs to all color regions. */
144 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
145 this->outputs
[i
] = reg
;
146 this->output_components
[i
] = 4;
148 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
149 this->frag_depth
= reg
;
150 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
151 this->frag_stencil
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
153 this->sample_mask
= reg
;
155 int vector_elements
= var
->type
->without_array()->vector_elements
;
157 /* gl_FragData or a user-defined FS output */
158 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
159 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
161 /* General color output. */
162 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
163 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
164 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
165 this->output_components
[output
] = vector_elements
;
170 unreachable("unhandled shader stage");
176 fs_visitor::nir_setup_uniforms()
178 if (dispatch_width
!= 8)
181 uniforms
= nir
->num_uniforms
/ 4;
185 emit_system_values_block(nir_block
*block
, void *void_visitor
)
187 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
190 nir_foreach_instr(block
, instr
) {
191 if (instr
->type
!= nir_instr_type_intrinsic
)
194 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
195 switch (intrin
->intrinsic
) {
196 case nir_intrinsic_load_vertex_id
:
197 unreachable("should be lowered by lower_vertex_id().");
199 case nir_intrinsic_load_vertex_id_zero_base
:
200 assert(v
->stage
== MESA_SHADER_VERTEX
);
201 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
202 if (reg
->file
== BAD_FILE
)
203 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
206 case nir_intrinsic_load_base_vertex
:
207 assert(v
->stage
== MESA_SHADER_VERTEX
);
208 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
209 if (reg
->file
== BAD_FILE
)
210 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
213 case nir_intrinsic_load_instance_id
:
214 assert(v
->stage
== MESA_SHADER_VERTEX
);
215 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
216 if (reg
->file
== BAD_FILE
)
217 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
220 case nir_intrinsic_load_base_instance
:
221 assert(v
->stage
== MESA_SHADER_VERTEX
);
222 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
223 if (reg
->file
== BAD_FILE
)
224 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
227 case nir_intrinsic_load_draw_id
:
228 assert(v
->stage
== MESA_SHADER_VERTEX
);
229 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
230 if (reg
->file
== BAD_FILE
)
231 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
234 case nir_intrinsic_load_invocation_id
:
235 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
236 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
237 if (reg
->file
== BAD_FILE
) {
238 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
239 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
240 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
241 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
246 case nir_intrinsic_load_sample_pos
:
247 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
248 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
249 if (reg
->file
== BAD_FILE
)
250 *reg
= *v
->emit_samplepos_setup();
253 case nir_intrinsic_load_sample_id
:
254 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
255 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
256 if (reg
->file
== BAD_FILE
)
257 *reg
= *v
->emit_sampleid_setup();
260 case nir_intrinsic_load_sample_mask_in
:
261 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
262 assert(v
->devinfo
->gen
>= 7);
263 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
264 if (reg
->file
== BAD_FILE
)
265 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
266 BRW_REGISTER_TYPE_D
));
269 case nir_intrinsic_load_local_invocation_id
:
270 assert(v
->stage
== MESA_SHADER_COMPUTE
);
271 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
272 if (reg
->file
== BAD_FILE
)
273 *reg
= *v
->emit_cs_local_invocation_id_setup();
276 case nir_intrinsic_load_work_group_id
:
277 assert(v
->stage
== MESA_SHADER_COMPUTE
);
278 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
279 if (reg
->file
== BAD_FILE
)
280 *reg
= *v
->emit_cs_work_group_id_setup();
283 case nir_intrinsic_load_helper_invocation
:
284 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
285 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
286 if (reg
->file
== BAD_FILE
) {
287 const fs_builder abld
=
288 v
->bld
.annotate("gl_HelperInvocation", NULL
);
290 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
291 * pixel mask is in g1.7 of the thread payload.
293 * We move the per-channel pixel enable bit to the low bit of each
294 * channel by shifting the byte containing the pixel mask by the
295 * vector immediate 0x76543210UV.
297 * The region of <1,8,0> reads only 1 byte (the pixel masks for
298 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
299 * masks for 2 and 3) in SIMD16.
301 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
303 stride(byte_offset(retype(brw_vec1_grf(1, 0),
304 BRW_REGISTER_TYPE_UB
), 28),
306 brw_imm_uv(0x76543210));
308 /* A set bit in the pixel mask means the channel is enabled, but
309 * that is the opposite of gl_HelperInvocation so we need to invert
312 * The negate source-modifier bit of logical instructions on Gen8+
313 * performs 1's complement negation, so we can use that instead of
316 fs_reg inverted
= negate(shifted
);
317 if (v
->devinfo
->gen
< 8) {
318 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
319 abld
.NOT(inverted
, shifted
);
322 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
323 * with 1 and negating.
325 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
326 abld
.AND(anded
, inverted
, brw_imm_uw(1));
328 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
329 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
343 fs_visitor::nir_emit_system_values()
345 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
346 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
347 nir_system_values
[i
] = fs_reg();
350 nir_foreach_function(nir
, function
) {
351 assert(strcmp(function
->name
, "main") == 0);
352 assert(function
->impl
);
353 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
358 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
360 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
361 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
362 nir_locals
[i
] = fs_reg();
365 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
366 unsigned array_elems
=
367 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
368 unsigned size
= array_elems
* reg
->num_components
;
369 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
372 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
375 nir_emit_cf_list(&impl
->body
);
379 fs_visitor::nir_emit_cf_list(exec_list
*list
)
381 exec_list_validate(list
);
382 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
383 switch (node
->type
) {
385 nir_emit_if(nir_cf_node_as_if(node
));
388 case nir_cf_node_loop
:
389 nir_emit_loop(nir_cf_node_as_loop(node
));
392 case nir_cf_node_block
:
393 nir_emit_block(nir_cf_node_as_block(node
));
397 unreachable("Invalid CFG node block");
403 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
405 /* first, put the condition into f0 */
406 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
407 retype(get_nir_src(if_stmt
->condition
),
408 BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
);
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 /* note: if the else is empty, dead CF elimination will remove it */
416 bld
.emit(BRW_OPCODE_ELSE
);
418 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
434 fs_visitor::nir_emit_block(nir_block
*block
)
436 nir_foreach_instr(block
, instr
) {
437 nir_emit_instr(instr
);
442 fs_visitor::nir_emit_instr(nir_instr
*instr
)
444 const fs_builder abld
= bld
.annotate(NULL
, instr
);
446 switch (instr
->type
) {
447 case nir_instr_type_alu
:
448 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
451 case nir_instr_type_intrinsic
:
453 case MESA_SHADER_VERTEX
:
454 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_TESS_EVAL
:
457 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_GEOMETRY
:
460 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_FRAGMENT
:
463 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_COMPUTE
:
466 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 unreachable("unsupported shader stage");
473 case nir_instr_type_tex
:
474 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
477 case nir_instr_type_load_const
:
478 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
481 case nir_instr_type_ssa_undef
:
482 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
485 case nir_instr_type_jump
:
486 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
490 unreachable("unknown instruction type");
495 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
499 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
500 const fs_reg
&result
)
502 if (!instr
->src
[0].src
.is_ssa
||
503 !instr
->src
[0].src
.ssa
->parent_instr
)
506 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
509 nir_alu_instr
*src0
=
510 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
513 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
516 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
517 assert(element
!= NULL
);
519 enum opcode extract_op
;
520 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
521 assert(element
->u32
[0] <= 1);
522 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
524 assert(element
->u32
[0] <= 3);
525 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
528 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
529 op0
.type
= brw_type_for_nir_type(nir_op_infos
[src0
->op
].input_types
[0]);
530 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
532 set_saturate(instr
->dest
.saturate
,
533 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
538 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
539 const fs_reg
&result
)
541 if (!instr
->src
[0].src
.is_ssa
||
542 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
545 nir_intrinsic_instr
*src0
=
546 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
548 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
551 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
552 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
555 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
556 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
559 fs_reg tmp
= vgrf(glsl_type::int_type
);
561 if (devinfo
->gen
>= 6) {
562 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
563 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
565 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
567 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
568 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
570 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
572 * This negation looks like it's safe in practice, because bits 0:4 will
573 * surely be TRIANGLES
576 if (value1
->f32
[0] == -1.0f
) {
580 tmp
.type
= BRW_REGISTER_TYPE_W
;
581 tmp
.subreg_offset
= 2;
584 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
586 tmp
.type
= BRW_REGISTER_TYPE_D
;
587 tmp
.subreg_offset
= 0;
590 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
591 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
593 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
595 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
596 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
598 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
600 * This negation looks like it's safe in practice, because bits 0:4 will
601 * surely be TRIANGLES
604 if (value1
->f32
[0] == -1.0f
) {
608 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
610 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
616 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
618 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
621 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
622 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
625 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
626 op
[i
] = get_nir_src(instr
->src
[i
].src
);
627 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
628 op
[i
].abs
= instr
->src
[i
].abs
;
629 op
[i
].negate
= instr
->src
[i
].negate
;
632 /* We get a bunch of mov's out of the from_ssa pass and they may still
633 * be vectorized. We'll handle them as a special-case. We'll also
634 * handle vecN here because it's basically the same thing.
642 fs_reg temp
= result
;
643 bool need_extra_copy
= false;
644 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
645 if (!instr
->src
[i
].src
.is_ssa
&&
646 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
647 need_extra_copy
= true;
648 temp
= bld
.vgrf(result
.type
, 4);
653 for (unsigned i
= 0; i
< 4; i
++) {
654 if (!(instr
->dest
.write_mask
& (1 << i
)))
657 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
658 inst
= bld
.MOV(offset(temp
, bld
, i
),
659 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
661 inst
= bld
.MOV(offset(temp
, bld
, i
),
662 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
664 inst
->saturate
= instr
->dest
.saturate
;
667 /* In this case the source and destination registers were the same,
668 * so we need to insert an extra set of moves in order to deal with
671 if (need_extra_copy
) {
672 for (unsigned i
= 0; i
< 4; i
++) {
673 if (!(instr
->dest
.write_mask
& (1 << i
)))
676 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
685 /* At this point, we have dealt with any instruction that operates on
686 * more than a single channel. Therefore, we can just adjust the source
687 * and destination registers for that channel and emit the instruction.
689 unsigned channel
= 0;
690 if (nir_op_infos
[instr
->op
].output_size
== 0) {
691 /* Since NIR is doing the scalarizing for us, we should only ever see
692 * vectorized operations with a single channel.
694 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
695 channel
= ffs(instr
->dest
.write_mask
) - 1;
697 result
= offset(result
, bld
, channel
);
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
702 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
708 if (optimize_extract_to_float(instr
, result
))
711 inst
= bld
.MOV(result
, op
[0]);
712 inst
->saturate
= instr
->dest
.saturate
;
717 bld
.MOV(result
, op
[0]);
721 /* AND(val, 0x80000000) gives the sign bit.
723 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
726 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
728 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
729 op
[0].type
= BRW_REGISTER_TYPE_UD
;
730 result
.type
= BRW_REGISTER_TYPE_UD
;
731 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
733 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
734 inst
->predicate
= BRW_PREDICATE_NORMAL
;
735 if (instr
->dest
.saturate
) {
736 inst
= bld
.MOV(result
, result
);
737 inst
->saturate
= true;
743 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
744 * -> non-negative val generates 0x00000000.
745 * Predicated OR sets 1 if val is positive.
747 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
748 bld
.ASR(result
, op
[0], brw_imm_d(31));
749 inst
= bld
.OR(result
, result
, brw_imm_d(1));
750 inst
->predicate
= BRW_PREDICATE_NORMAL
;
754 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
755 inst
->saturate
= instr
->dest
.saturate
;
759 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
760 inst
->saturate
= instr
->dest
.saturate
;
764 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
765 inst
->saturate
= instr
->dest
.saturate
;
769 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
770 inst
->saturate
= instr
->dest
.saturate
;
774 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
775 inst
->saturate
= instr
->dest
.saturate
;
779 if (fs_key
->high_quality_derivatives
) {
780 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
782 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
784 inst
->saturate
= instr
->dest
.saturate
;
786 case nir_op_fddx_fine
:
787 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
788 inst
->saturate
= instr
->dest
.saturate
;
790 case nir_op_fddx_coarse
:
791 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
792 inst
->saturate
= instr
->dest
.saturate
;
795 if (fs_key
->high_quality_derivatives
) {
796 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
797 brw_imm_d(fs_key
->render_to_fbo
));
799 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
800 brw_imm_d(fs_key
->render_to_fbo
));
802 inst
->saturate
= instr
->dest
.saturate
;
804 case nir_op_fddy_fine
:
805 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
806 brw_imm_d(fs_key
->render_to_fbo
));
807 inst
->saturate
= instr
->dest
.saturate
;
809 case nir_op_fddy_coarse
:
810 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
811 brw_imm_d(fs_key
->render_to_fbo
));
812 inst
->saturate
= instr
->dest
.saturate
;
817 inst
= bld
.ADD(result
, op
[0], op
[1]);
818 inst
->saturate
= instr
->dest
.saturate
;
822 inst
= bld
.MUL(result
, op
[0], op
[1]);
823 inst
->saturate
= instr
->dest
.saturate
;
827 bld
.MUL(result
, op
[0], op
[1]);
830 case nir_op_imul_high
:
831 case nir_op_umul_high
:
832 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
837 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
840 case nir_op_uadd_carry
:
841 unreachable("Should have been lowered by carry_to_arith().");
843 case nir_op_usub_borrow
:
844 unreachable("Should have been lowered by borrow_to_arith().");
848 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
849 * appears that our hardware just does the right thing for signed
852 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
856 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
857 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
859 /* Math instructions don't support conditional mod */
860 inst
= bld
.MOV(bld
.null_reg_d(), result
);
861 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
863 /* Now, we need to determine if signs of the sources are different.
864 * When we XOR the sources, the top bit is 0 if they are the same and 1
865 * if they are different. We can then use a conditional modifier to
866 * turn that into a predicate. This leads us to an XOR.l instruction.
868 * Technically, according to the PRM, you're not allowed to use .l on a
869 * XOR instruction. However, emperical experiments and Curro's reading
870 * of the simulator source both indicate that it's safe.
872 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
873 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
874 inst
->predicate
= BRW_PREDICATE_NORMAL
;
875 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
877 /* If the result of the initial remainder operation is non-zero and the
878 * two sources have different signs, add in a copy of op[1] to get the
879 * final integer modulus value.
881 inst
= bld
.ADD(result
, result
, op
[1]);
882 inst
->predicate
= BRW_PREDICATE_NORMAL
;
889 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
895 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
900 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
905 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
909 if (devinfo
->gen
>= 8) {
910 op
[0] = resolve_source_modifiers(op
[0]);
912 bld
.NOT(result
, op
[0]);
915 if (devinfo
->gen
>= 8) {
916 op
[0] = resolve_source_modifiers(op
[0]);
917 op
[1] = resolve_source_modifiers(op
[1]);
919 bld
.XOR(result
, op
[0], op
[1]);
922 if (devinfo
->gen
>= 8) {
923 op
[0] = resolve_source_modifiers(op
[0]);
924 op
[1] = resolve_source_modifiers(op
[1]);
926 bld
.OR(result
, op
[0], op
[1]);
929 if (devinfo
->gen
>= 8) {
930 op
[0] = resolve_source_modifiers(op
[0]);
931 op
[1] = resolve_source_modifiers(op
[1]);
933 bld
.AND(result
, op
[0], op
[1]);
939 case nir_op_ball_fequal2
:
940 case nir_op_ball_iequal2
:
941 case nir_op_ball_fequal3
:
942 case nir_op_ball_iequal3
:
943 case nir_op_ball_fequal4
:
944 case nir_op_ball_iequal4
:
945 case nir_op_bany_fnequal2
:
946 case nir_op_bany_inequal2
:
947 case nir_op_bany_fnequal3
:
948 case nir_op_bany_inequal3
:
949 case nir_op_bany_fnequal4
:
950 case nir_op_bany_inequal4
:
951 unreachable("Lowered by nir_lower_alu_reductions");
953 case nir_op_fnoise1_1
:
954 case nir_op_fnoise1_2
:
955 case nir_op_fnoise1_3
:
956 case nir_op_fnoise1_4
:
957 case nir_op_fnoise2_1
:
958 case nir_op_fnoise2_2
:
959 case nir_op_fnoise2_3
:
960 case nir_op_fnoise2_4
:
961 case nir_op_fnoise3_1
:
962 case nir_op_fnoise3_2
:
963 case nir_op_fnoise3_3
:
964 case nir_op_fnoise3_4
:
965 case nir_op_fnoise4_1
:
966 case nir_op_fnoise4_2
:
967 case nir_op_fnoise4_3
:
968 case nir_op_fnoise4_4
:
969 unreachable("not reached: should be handled by lower_noise");
972 unreachable("not reached: should be handled by ldexp_to_arith()");
975 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
980 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
981 inst
->saturate
= instr
->dest
.saturate
;
986 bld
.MOV(result
, negate(op
[0]));
990 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
993 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
997 inst
= bld
.RNDZ(result
, op
[0]);
998 inst
->saturate
= instr
->dest
.saturate
;
1001 case nir_op_fceil
: {
1002 op
[0].negate
= !op
[0].negate
;
1003 fs_reg temp
= vgrf(glsl_type::float_type
);
1004 bld
.RNDD(temp
, op
[0]);
1006 inst
= bld
.MOV(result
, temp
);
1007 inst
->saturate
= instr
->dest
.saturate
;
1011 inst
= bld
.RNDD(result
, op
[0]);
1012 inst
->saturate
= instr
->dest
.saturate
;
1015 inst
= bld
.FRC(result
, op
[0]);
1016 inst
->saturate
= instr
->dest
.saturate
;
1018 case nir_op_fround_even
:
1019 inst
= bld
.RNDE(result
, op
[0]);
1020 inst
->saturate
= instr
->dest
.saturate
;
1023 case nir_op_fquantize2f16
: {
1024 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1025 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1026 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1028 /* The destination stride must be at least as big as the source stride. */
1029 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1032 /* Check for denormal */
1033 fs_reg abs_src0
= op
[0];
1034 abs_src0
.abs
= true;
1035 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1037 /* Get the appropriately signed zero */
1038 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1039 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1040 brw_imm_ud(0x80000000));
1041 /* Do the actual F32 -> F16 -> F32 conversion */
1042 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1043 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1044 /* Select that or zero based on normal status */
1045 inst
= bld
.SEL(result
, zero
, tmp32
);
1046 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1047 inst
->saturate
= instr
->dest
.saturate
;
1054 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1055 inst
->saturate
= instr
->dest
.saturate
;
1061 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1062 inst
->saturate
= instr
->dest
.saturate
;
1065 case nir_op_pack_snorm_2x16
:
1066 case nir_op_pack_snorm_4x8
:
1067 case nir_op_pack_unorm_2x16
:
1068 case nir_op_pack_unorm_4x8
:
1069 case nir_op_unpack_snorm_2x16
:
1070 case nir_op_unpack_snorm_4x8
:
1071 case nir_op_unpack_unorm_2x16
:
1072 case nir_op_unpack_unorm_4x8
:
1073 case nir_op_unpack_half_2x16
:
1074 case nir_op_pack_half_2x16
:
1075 unreachable("not reached: should be handled by lower_packing_builtins");
1077 case nir_op_unpack_half_2x16_split_x
:
1078 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1079 inst
->saturate
= instr
->dest
.saturate
;
1081 case nir_op_unpack_half_2x16_split_y
:
1082 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1083 inst
->saturate
= instr
->dest
.saturate
;
1087 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1088 inst
->saturate
= instr
->dest
.saturate
;
1091 case nir_op_bitfield_reverse
:
1092 bld
.BFREV(result
, op
[0]);
1095 case nir_op_bit_count
:
1096 bld
.CBIT(result
, op
[0]);
1099 case nir_op_ufind_msb
:
1100 case nir_op_ifind_msb
: {
1101 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1103 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1104 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1105 * subtract the result from 31 to convert the MSB count into an LSB count.
1107 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1109 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1110 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1111 inst
->src
[0].negate
= true;
1115 case nir_op_find_lsb
:
1116 bld
.FBL(result
, op
[0]);
1119 case nir_op_ubitfield_extract
:
1120 case nir_op_ibitfield_extract
:
1121 unreachable("should have been lowered");
1124 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1127 bld
.BFI1(result
, op
[0], op
[1]);
1130 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1133 case nir_op_bitfield_insert
:
1134 unreachable("not reached: should have been lowered");
1137 bld
.SHL(result
, op
[0], op
[1]);
1140 bld
.ASR(result
, op
[0], op
[1]);
1143 bld
.SHR(result
, op
[0], op
[1]);
1146 case nir_op_pack_half_2x16_split
:
1147 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1151 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1152 inst
->saturate
= instr
->dest
.saturate
;
1156 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1157 inst
->saturate
= instr
->dest
.saturate
;
1161 if (optimize_frontfacing_ternary(instr
, result
))
1164 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1165 inst
= bld
.SEL(result
, op
[1], op
[2]);
1166 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1169 case nir_op_extract_u8
:
1170 case nir_op_extract_i8
: {
1171 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1172 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1173 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1177 case nir_op_extract_u16
:
1178 case nir_op_extract_i16
: {
1179 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1180 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1181 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1186 unreachable("unhandled instruction");
1189 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1190 * to sign extend the low bit to 0/~0
1192 if (devinfo
->gen
<= 5 &&
1193 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1194 fs_reg masked
= vgrf(glsl_type::int_type
);
1195 bld
.AND(masked
, result
, brw_imm_d(1));
1196 masked
.negate
= true;
1197 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1202 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1203 nir_load_const_instr
*instr
)
1205 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1207 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1208 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1210 nir_ssa_values
[instr
->def
.index
] = reg
;
1214 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1216 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1217 instr
->def
.num_components
);
1221 fs_visitor::get_nir_src(nir_src src
)
1225 reg
= nir_ssa_values
[src
.ssa
->index
];
1227 /* We don't handle indirects on locals */
1228 assert(src
.reg
.indirect
== NULL
);
1229 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1230 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1233 /* to avoid floating-point denorm flushing problems, set the type by
1234 * default to D - instructions that need floating point semantics will set
1235 * this to F if they need to
1237 return retype(reg
, BRW_REGISTER_TYPE_D
);
1241 fs_visitor::get_nir_dest(nir_dest dest
)
1244 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1245 dest
.ssa
.num_components
);
1246 return nir_ssa_values
[dest
.ssa
.index
];
1248 /* We don't handle indirects on locals */
1249 assert(dest
.reg
.indirect
== NULL
);
1250 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1251 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1256 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1258 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1259 BRW_REGISTER_TYPE_UD
);
1261 unsigned indirect_max
= 0;
1263 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1264 tail
= tail
->child
) {
1265 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1266 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1267 const unsigned size
= glsl_get_length(tail
->type
);
1268 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1269 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1270 image
= offset(image
, bld
, base
* element_size
);
1272 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1273 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1275 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1276 /* IVB hangs when trying to access an invalid surface index with
1277 * the dataport. According to the spec "if the index used to
1278 * select an individual element is negative or greater than or
1279 * equal to the size of the array, the results of the operation
1280 * are undefined but may not lead to termination" -- which is one
1281 * of the possible outcomes of the hang. Clamp the index to
1282 * prevent access outside of the array bounds.
1284 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1285 BRW_REGISTER_TYPE_UD
),
1286 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1288 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1291 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1293 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1294 if (indirect
.file
== BAD_FILE
) {
1297 bld
.ADD(indirect
, indirect
, tmp
);
1302 if (indirect
.file
== BAD_FILE
) {
1305 /* Emit a pile of MOVs to load the uniform into a temporary. The
1306 * dead-code elimination pass will get rid of what we don't use.
1308 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1309 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1310 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1311 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1312 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1319 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1322 for (unsigned i
= 0; i
< 4; i
++) {
1323 if (!((wr_mask
>> i
) & 1))
1326 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1327 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1328 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1329 if (new_inst
->src
[j
].file
== VGRF
)
1330 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1337 * Get the matching channel register datatype for an image intrinsic of the
1338 * specified GLSL image type.
1341 get_image_base_type(const glsl_type
*type
)
1343 switch ((glsl_base_type
)type
->sampled_type
) {
1344 case GLSL_TYPE_UINT
:
1345 return BRW_REGISTER_TYPE_UD
;
1347 return BRW_REGISTER_TYPE_D
;
1348 case GLSL_TYPE_FLOAT
:
1349 return BRW_REGISTER_TYPE_F
;
1351 unreachable("Not reached.");
1356 * Get the appropriate atomic op for an image atomic intrinsic.
1359 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1362 case nir_intrinsic_image_atomic_add
:
1364 case nir_intrinsic_image_atomic_min
:
1365 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1366 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1367 case nir_intrinsic_image_atomic_max
:
1368 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1369 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1370 case nir_intrinsic_image_atomic_and
:
1372 case nir_intrinsic_image_atomic_or
:
1374 case nir_intrinsic_image_atomic_xor
:
1376 case nir_intrinsic_image_atomic_exchange
:
1378 case nir_intrinsic_image_atomic_comp_swap
:
1379 return BRW_AOP_CMPWR
;
1381 unreachable("Not reachable.");
1386 emit_pixel_interpolater_send(const fs_builder
&bld
,
1391 glsl_interp_qualifier interpolation
)
1397 if (src
.file
== BAD_FILE
) {
1399 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1403 mlen
= 2 * bld
.dispatch_width() / 8;
1406 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1408 /* 2 floats per slot returned */
1409 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1410 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1416 * Computes 1 << x, given a D/UD register containing some value x.
1419 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1421 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1423 fs_reg result
= bld
.vgrf(x
.type
, 1);
1424 fs_reg one
= bld
.vgrf(x
.type
, 1);
1426 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1427 bld
.SHL(result
, one
, x
);
1432 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1434 assert(stage
== MESA_SHADER_GEOMETRY
);
1436 struct brw_gs_prog_data
*gs_prog_data
=
1437 (struct brw_gs_prog_data
*) prog_data
;
1439 /* We can only do EndPrimitive() functionality when the control data
1440 * consists of cut bits. Fortunately, the only time it isn't is when the
1441 * output type is points, in which case EndPrimitive() is a no-op.
1443 if (gs_prog_data
->control_data_format
!=
1444 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1448 /* Cut bits use one bit per vertex. */
1449 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1451 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1452 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1454 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1455 * vertex n, 0 otherwise. So all we need to do here is mark bit
1456 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1457 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1458 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1460 * Note that if EndPrimitive() is called before emitting any vertices, this
1461 * will cause us to set bit 31 of the control_data_bits register to 1.
1462 * That's fine because:
1464 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1465 * output, so the hardware will ignore cut bit 31.
1467 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1468 * last vertex, so setting cut bit 31 has no effect (since the primitive
1469 * is automatically ended when the GS terminates).
1471 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1472 * control_data_bits register to 0 when the first vertex is emitted.
1475 const fs_builder abld
= bld
.annotate("end primitive");
1477 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1478 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1479 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1480 fs_reg mask
= intexp2(abld
, prev_count
);
1481 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1482 * attention to the lower 5 bits of its second source argument, so on this
1483 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1484 * ((vertex_count - 1) % 32).
1486 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1490 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1492 assert(stage
== MESA_SHADER_GEOMETRY
);
1493 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1495 struct brw_gs_prog_data
*gs_prog_data
=
1496 (struct brw_gs_prog_data
*) prog_data
;
1498 const fs_builder abld
= bld
.annotate("emit control data bits");
1499 const fs_builder fwa_bld
= bld
.exec_all();
1501 /* We use a single UD register to accumulate control data bits (32 bits
1502 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1505 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1506 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1507 * use the Channel Mask phase to enable/disable which DWord within that
1508 * group to write. (Remember, different SIMD8 channels may have emitted
1509 * different numbers of vertices, so we may need per-slot offsets.)
1511 * Channel masking presents an annoying problem: we may have to replicate
1512 * the data up to 4 times:
1514 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1516 * To avoid penalizing shaders that emit a small number of vertices, we
1517 * can avoid these sometimes: if the size of the control data header is
1518 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1519 * land in the same 128-bit group, so we can skip per-slot offsets.
1521 * Similarly, if the control data header is <= 32 bits, there is only one
1522 * DWord, so we can skip channel masks.
1524 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1526 fs_reg channel_mask
, per_slot_offset
;
1528 if (gs_compile
->control_data_header_size_bits
> 32) {
1529 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1530 channel_mask
= vgrf(glsl_type::uint_type
);
1533 if (gs_compile
->control_data_header_size_bits
> 128) {
1534 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1535 per_slot_offset
= vgrf(glsl_type::uint_type
);
1538 /* Figure out which DWord we're trying to write to using the formula:
1540 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1542 * Since bits_per_vertex is a power of two, and is known at compile
1543 * time, this can be optimized to:
1545 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1547 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1548 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1549 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1550 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1551 unsigned log2_bits_per_vertex
=
1552 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1553 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1555 if (per_slot_offset
.file
!= BAD_FILE
) {
1556 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1557 * the appropriate OWord within the control data header.
1559 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1562 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1563 * write to the appropriate DWORD within the OWORD.
1565 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1566 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1567 channel_mask
= intexp2(fwa_bld
, channel
);
1568 /* Then the channel masks need to be in bits 23:16. */
1569 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1572 /* Store the control data bits in the message payload and send it. */
1574 if (channel_mask
.file
!= BAD_FILE
)
1575 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1576 if (per_slot_offset
.file
!= BAD_FILE
)
1579 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1580 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1582 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1583 if (per_slot_offset
.file
!= BAD_FILE
)
1584 sources
[i
++] = per_slot_offset
;
1585 if (channel_mask
.file
!= BAD_FILE
)
1586 sources
[i
++] = channel_mask
;
1588 sources
[i
++] = this->control_data_bits
;
1591 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1592 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1594 /* We need to increment Global Offset by 256-bits to make room for
1595 * Broadwell's extra "Vertex Count" payload at the beginning of the
1596 * URB entry. Since this is an OWord message, Global Offset is counted
1597 * in 128-bit units, so we must set it to 2.
1599 if (gs_prog_data
->static_vertex_count
== -1)
1604 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1607 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1609 /* Note: we are calling this *before* increasing vertex_count, so
1610 * this->vertex_count == vertex_count - 1 in the formula above.
1613 /* Stream mode uses 2 bits per vertex */
1614 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1616 /* Must be a valid stream */
1617 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1619 /* Control data bits are initialized to 0 so we don't have to set any
1620 * bits when sending vertices to stream 0.
1625 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1627 /* reg::sid = stream_id */
1628 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1629 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1631 /* reg:shift_count = 2 * (vertex_count - 1) */
1632 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1633 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1635 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1636 * attention to the lower 5 bits of its second source argument, so on this
1637 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1638 * stream_id << ((2 * (vertex_count - 1)) % 32).
1640 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1641 abld
.SHL(mask
, sid
, shift_count
);
1642 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1646 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1649 assert(stage
== MESA_SHADER_GEOMETRY
);
1651 struct brw_gs_prog_data
*gs_prog_data
=
1652 (struct brw_gs_prog_data
*) prog_data
;
1654 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1655 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1657 /* Haswell and later hardware ignores the "Render Stream Select" bits
1658 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1659 * and instead sends all primitives down the pipeline for rasterization.
1660 * If the SOL stage is enabled, "Render Stream Select" is honored and
1661 * primitives bound to non-zero streams are discarded after stream output.
1663 * Since the only purpose of primives sent to non-zero streams is to
1664 * be recorded by transform feedback, we can simply discard all geometry
1665 * bound to these streams when transform feedback is disabled.
1667 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1670 /* If we're outputting 32 control data bits or less, then we can wait
1671 * until the shader is over to output them all. Otherwise we need to
1672 * output them as we go. Now is the time to do it, since we're about to
1673 * output the vertex_count'th vertex, so it's guaranteed that the
1674 * control data bits associated with the (vertex_count - 1)th vertex are
1677 if (gs_compile
->control_data_header_size_bits
> 32) {
1678 const fs_builder abld
=
1679 bld
.annotate("emit vertex: emit control data bits");
1681 /* Only emit control data bits if we've finished accumulating a batch
1682 * of 32 bits. This is the case when:
1684 * (vertex_count * bits_per_vertex) % 32 == 0
1686 * (in other words, when the last 5 bits of vertex_count *
1687 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1688 * integer n (which is always the case, since bits_per_vertex is
1689 * always 1 or 2), this is equivalent to requiring that the last 5-n
1690 * bits of vertex_count are 0:
1692 * vertex_count & (2^(5-n) - 1) == 0
1694 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1697 * vertex_count & (32 / bits_per_vertex - 1) == 0
1699 * TODO: If vertex_count is an immediate, we could do some of this math
1700 * at compile time...
1703 abld
.AND(bld
.null_reg_d(), vertex_count
,
1704 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1705 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1707 abld
.IF(BRW_PREDICATE_NORMAL
);
1708 /* If vertex_count is 0, then no control data bits have been
1709 * accumulated yet, so we can skip emitting them.
1711 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1712 BRW_CONDITIONAL_NEQ
);
1713 abld
.IF(BRW_PREDICATE_NORMAL
);
1714 emit_gs_control_data_bits(vertex_count
);
1715 abld
.emit(BRW_OPCODE_ENDIF
);
1717 /* Reset control_data_bits to 0 so we can start accumulating a new
1720 * Note: in the case where vertex_count == 0, this neutralizes the
1721 * effect of any call to EndPrimitive() that the shader may have
1722 * made before outputting its first vertex.
1724 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1725 inst
->force_writemask_all
= true;
1726 abld
.emit(BRW_OPCODE_ENDIF
);
1729 emit_urb_writes(vertex_count
);
1731 /* In stream mode we have to set control data bits for all vertices
1732 * unless we have disabled control data bits completely (which we do
1733 * do for GL_POINTS outputs that don't use streams).
1735 if (gs_compile
->control_data_header_size_bits
> 0 &&
1736 gs_prog_data
->control_data_format
==
1737 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1738 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1743 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1744 const nir_src
&vertex_src
,
1745 unsigned base_offset
,
1746 const nir_src
&offset_src
,
1747 unsigned num_components
)
1749 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1751 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1752 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1753 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1755 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1756 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1757 * gl_PointSize is available as a GS input, however, so it must be that.
1759 const bool is_point_size
= (base_offset
== 0);
1761 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1762 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1763 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1764 vertex_const
->u32
[0] * push_reg_count
;
1765 /* This input was pushed into registers. */
1766 if (is_point_size
) {
1767 /* gl_PointSize comes in .w */
1768 assert(imm_offset
== 0);
1769 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1771 for (unsigned i
= 0; i
< num_components
; i
++) {
1772 bld
.MOV(offset(dst
, bld
, i
),
1773 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1777 /* Resort to the pull model. Ensure the VUE handles are provided. */
1778 gs_prog_data
->base
.include_vue_handles
= true;
1780 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1784 /* The vertex index is constant; just select the proper URB handle. */
1786 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1787 BRW_REGISTER_TYPE_UD
);
1789 /* The vertex index is non-constant. We need to use indirect
1790 * addressing to fetch the proper URB handle.
1792 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1793 * indicating that channel <n> should read the handle from
1794 * DWord <n>. We convert that to bytes by multiplying by 4.
1796 * Next, we convert the vertex index to bytes by multiplying
1797 * by 32 (shifting by 5), and add the two together. This is
1798 * the final indirect byte offset.
1800 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1801 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1802 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1803 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1804 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1806 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1807 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1808 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1809 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1810 /* Convert vertex_index to bytes (multiply by 32) */
1811 bld
.SHL(vertex_offset_bytes
,
1812 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1814 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1816 /* Use first_icp_handle as the base offset. There is one register
1817 * of URB handles per vertex, so inform the register allocator that
1818 * we might read up to nir->info.gs.vertices_in registers.
1820 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1821 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1822 fs_reg(icp_offset_bytes
),
1823 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1828 /* Constant indexing - use global offset. */
1829 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1830 inst
->offset
= base_offset
+ offset_const
->u32
[0];
1831 inst
->base_mrf
= -1;
1833 inst
->regs_written
= num_components
;
1835 /* Indirect indexing - use per-slot offsets as well. */
1836 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1837 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1838 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1840 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1841 inst
->offset
= base_offset
;
1842 inst
->base_mrf
= -1;
1844 inst
->regs_written
= num_components
;
1847 if (is_point_size
) {
1848 /* Read the whole VUE header (because of alignment) and read .w. */
1849 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1851 inst
->regs_written
= 4;
1852 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1858 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1860 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1861 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1864 /* The only constant offset we should find is 0. brw_nir.c's
1865 * add_const_offset_to_base() will fold other constant offsets
1866 * into instr->const_index[0].
1868 assert(const_value
->u32
[0] == 0);
1872 return get_nir_src(*offset_src
);
1876 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1877 nir_intrinsic_instr
*instr
)
1879 assert(stage
== MESA_SHADER_VERTEX
);
1882 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1883 dest
= get_nir_dest(instr
->dest
);
1885 switch (instr
->intrinsic
) {
1886 case nir_intrinsic_load_vertex_id
:
1887 unreachable("should be lowered by lower_vertex_id()");
1889 case nir_intrinsic_load_vertex_id_zero_base
:
1890 case nir_intrinsic_load_base_vertex
:
1891 case nir_intrinsic_load_instance_id
:
1892 case nir_intrinsic_load_base_instance
:
1893 case nir_intrinsic_load_draw_id
: {
1894 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1895 fs_reg val
= nir_system_values
[sv
];
1896 assert(val
.file
!= BAD_FILE
);
1897 dest
.type
= val
.type
;
1903 nir_emit_intrinsic(bld
, instr
);
1909 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1910 nir_intrinsic_instr
*instr
)
1912 assert(stage
== MESA_SHADER_TESS_EVAL
);
1913 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1916 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1917 dest
= get_nir_dest(instr
->dest
);
1919 switch (instr
->intrinsic
) {
1920 case nir_intrinsic_load_primitive_id
:
1921 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1923 case nir_intrinsic_load_tess_coord
:
1924 /* gl_TessCoord is part of the payload in g1-3 */
1925 for (unsigned i
= 0; i
< 3; i
++) {
1926 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1930 case nir_intrinsic_load_tess_level_outer
:
1931 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1932 * appears as a push-model input. So, we can simply use the ATTR file
1933 * rather than issuing URB read messages. The data is stored in the
1934 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1937 switch (tes_prog_data
->domain
) {
1938 case BRW_TESS_DOMAIN_QUAD
:
1939 for (unsigned i
= 0; i
< 4; i
++)
1940 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1942 case BRW_TESS_DOMAIN_TRI
:
1943 for (unsigned i
= 0; i
< 3; i
++)
1944 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1946 case BRW_TESS_DOMAIN_ISOLINE
:
1947 for (unsigned i
= 0; i
< 2; i
++)
1948 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1953 case nir_intrinsic_load_tess_level_inner
:
1954 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1955 * appears as a push-model input. So, we can simply use the ATTR file
1956 * rather than issuing URB read messages.
1958 switch (tes_prog_data
->domain
) {
1959 case BRW_TESS_DOMAIN_QUAD
:
1960 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1961 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1963 case BRW_TESS_DOMAIN_TRI
:
1964 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1966 case BRW_TESS_DOMAIN_ISOLINE
:
1967 /* ignore - value is undefined */
1972 case nir_intrinsic_load_input
:
1973 case nir_intrinsic_load_per_vertex_input
: {
1974 fs_reg indirect_offset
= get_indirect_offset(instr
);
1975 unsigned imm_offset
= instr
->const_index
[0];
1978 if (indirect_offset
.file
== BAD_FILE
) {
1979 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1980 * which is 16 registers (since each holds 2 vec4 slots).
1982 const unsigned max_push_slots
= 32;
1983 if (imm_offset
< max_push_slots
) {
1984 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1985 for (int i
= 0; i
< instr
->num_components
; i
++) {
1986 bld
.MOV(offset(dest
, bld
, i
),
1987 component(src
, 4 * (imm_offset
% 2) + i
));
1989 tes_prog_data
->base
.urb_read_length
=
1990 MAX2(tes_prog_data
->base
.urb_read_length
,
1991 DIV_ROUND_UP(imm_offset
+ 1, 2));
1993 /* Replicate the patch handle to all enabled channels */
1994 const fs_reg srcs
[] = {
1995 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1997 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1998 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2000 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2002 inst
->offset
= imm_offset
;
2003 inst
->base_mrf
= -1;
2004 inst
->regs_written
= instr
->num_components
;
2007 /* Indirect indexing - use per-slot offsets as well. */
2008 const fs_reg srcs
[] = {
2009 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2012 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2013 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2015 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2017 inst
->offset
= imm_offset
;
2018 inst
->base_mrf
= -1;
2019 inst
->regs_written
= instr
->num_components
;
2024 nir_emit_intrinsic(bld
, instr
);
2030 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2031 nir_intrinsic_instr
*instr
)
2033 assert(stage
== MESA_SHADER_GEOMETRY
);
2034 fs_reg indirect_offset
;
2037 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2038 dest
= get_nir_dest(instr
->dest
);
2040 switch (instr
->intrinsic
) {
2041 case nir_intrinsic_load_primitive_id
:
2042 assert(stage
== MESA_SHADER_GEOMETRY
);
2043 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2044 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2045 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2048 case nir_intrinsic_load_input
:
2049 unreachable("load_input intrinsics are invalid for the GS stage");
2051 case nir_intrinsic_load_per_vertex_input
:
2052 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2053 instr
->src
[1], instr
->num_components
);
2056 case nir_intrinsic_emit_vertex_with_counter
:
2057 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2060 case nir_intrinsic_end_primitive_with_counter
:
2061 emit_gs_end_primitive(instr
->src
[0]);
2064 case nir_intrinsic_set_vertex_count
:
2065 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2068 case nir_intrinsic_load_invocation_id
: {
2069 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2070 assert(val
.file
!= BAD_FILE
);
2071 dest
.type
= val
.type
;
2077 nir_emit_intrinsic(bld
, instr
);
2083 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2084 nir_intrinsic_instr
*instr
)
2086 assert(stage
== MESA_SHADER_FRAGMENT
);
2087 struct brw_wm_prog_data
*wm_prog_data
=
2088 (struct brw_wm_prog_data
*) prog_data
;
2091 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2092 dest
= get_nir_dest(instr
->dest
);
2094 switch (instr
->intrinsic
) {
2095 case nir_intrinsic_load_front_face
:
2096 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2097 *emit_frontfacing_interpolation());
2100 case nir_intrinsic_load_sample_pos
: {
2101 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2102 assert(sample_pos
.file
!= BAD_FILE
);
2103 dest
.type
= sample_pos
.type
;
2104 bld
.MOV(dest
, sample_pos
);
2105 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2109 case nir_intrinsic_load_helper_invocation
:
2110 case nir_intrinsic_load_sample_mask_in
:
2111 case nir_intrinsic_load_sample_id
: {
2112 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2113 fs_reg val
= nir_system_values
[sv
];
2114 assert(val
.file
!= BAD_FILE
);
2115 dest
.type
= val
.type
;
2120 case nir_intrinsic_discard
:
2121 case nir_intrinsic_discard_if
: {
2122 /* We track our discarded pixels in f0.1. By predicating on it, we can
2123 * update just the flag bits that aren't yet discarded. If there's no
2124 * condition, we emit a CMP of g0 != g0, so all currently executing
2125 * channels will get turned off.
2128 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2129 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2130 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2132 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2133 BRW_REGISTER_TYPE_UW
));
2134 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2136 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2137 cmp
->flag_subreg
= 1;
2139 if (devinfo
->gen
>= 6) {
2140 emit_discard_jump();
2145 case nir_intrinsic_interp_var_at_centroid
:
2146 case nir_intrinsic_interp_var_at_sample
:
2147 case nir_intrinsic_interp_var_at_offset
: {
2148 /* Handle ARB_gpu_shader5 interpolation intrinsics
2150 * It's worth a quick word of explanation as to why we handle the full
2151 * variable-based interpolation intrinsic rather than a lowered version
2152 * with like we do for other inputs. We have to do that because the way
2153 * we set up inputs doesn't allow us to use the already setup inputs for
2154 * interpolation. At the beginning of the shader, we go through all of
2155 * the input variables and do the initial interpolation and put it in
2156 * the nir_inputs array based on its location as determined in
2157 * nir_lower_io. If the input isn't used, dead code cleans up and
2158 * everything works fine. However, when we get to the ARB_gpu_shader5
2159 * interpolation intrinsics, we need to reinterpolate the input
2160 * differently. If we used an intrinsic that just had an index it would
2161 * only give us the offset into the nir_inputs array. However, this is
2162 * useless because that value is post-interpolation and we need
2163 * pre-interpolation. In order to get the actual location of the bits
2164 * we get from the vertex fetching hardware, we need the variable.
2166 wm_prog_data
->pulls_bary
= true;
2168 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2169 const glsl_interp_qualifier interpolation
=
2170 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2172 switch (instr
->intrinsic
) {
2173 case nir_intrinsic_interp_var_at_centroid
:
2174 emit_pixel_interpolater_send(bld
,
2175 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2182 case nir_intrinsic_interp_var_at_sample
: {
2183 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2186 unsigned msg_data
= const_sample
->i32
[0] << 4;
2188 emit_pixel_interpolater_send(bld
,
2189 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2192 brw_imm_ud(msg_data
),
2195 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2196 BRW_REGISTER_TYPE_UD
);
2198 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2199 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2200 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2201 bld
.exec_all().group(1, 0)
2202 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2203 emit_pixel_interpolater_send(bld
,
2204 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2210 /* Make a loop that sends a message to the pixel interpolater
2211 * for the sample number in each live channel. If there are
2212 * multiple channels with the same sample number then these
2213 * will be handled simultaneously with a single interation of
2216 bld
.emit(BRW_OPCODE_DO
);
2218 /* Get the next live sample number into sample_id_reg */
2219 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2221 /* Set the flag register so that we can perform the send
2222 * message on all channels that have the same sample number
2224 bld
.CMP(bld
.null_reg_ud(),
2225 sample_src
, sample_id
,
2226 BRW_CONDITIONAL_EQ
);
2227 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2228 bld
.exec_all().group(1, 0)
2229 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2231 emit_pixel_interpolater_send(bld
,
2232 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2237 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2239 /* Continue the loop if there are any live channels left */
2240 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2242 bld
.emit(BRW_OPCODE_WHILE
));
2249 case nir_intrinsic_interp_var_at_offset
: {
2250 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2253 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2254 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2256 emit_pixel_interpolater_send(bld
,
2257 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2260 brw_imm_ud(off_x
| (off_y
<< 4)),
2263 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2264 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2265 BRW_REGISTER_TYPE_F
);
2266 for (int i
= 0; i
< 2; i
++) {
2267 fs_reg temp
= vgrf(glsl_type::float_type
);
2268 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2269 fs_reg itemp
= vgrf(glsl_type::int_type
);
2270 bld
.MOV(itemp
, temp
); /* float to int */
2272 /* Clamp the upper end of the range to +7/16.
2273 * ARB_gpu_shader5 requires that we support a maximum offset
2274 * of +0.5, which isn't representable in a S0.4 value -- if
2275 * we didn't clamp it, we'd end up with -8/16, which is the
2276 * opposite of what the shader author wanted.
2278 * This is legal due to ARB_gpu_shader5's quantization
2281 * "Not all values of <offset> may be supported; x and y
2282 * offsets may be rounded to fixed-point values with the
2283 * number of fraction bits given by the
2284 * implementation-dependent constant
2285 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2287 set_condmod(BRW_CONDITIONAL_L
,
2288 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2291 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2292 emit_pixel_interpolater_send(bld
,
2303 unreachable("Invalid intrinsic");
2306 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2307 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2308 src
.type
= dest
.type
;
2310 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2311 dest
= offset(dest
, bld
, 1);
2316 nir_emit_intrinsic(bld
, instr
);
2322 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2323 nir_intrinsic_instr
*instr
)
2325 assert(stage
== MESA_SHADER_COMPUTE
);
2326 struct brw_cs_prog_data
*cs_prog_data
=
2327 (struct brw_cs_prog_data
*) prog_data
;
2330 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2331 dest
= get_nir_dest(instr
->dest
);
2333 switch (instr
->intrinsic
) {
2334 case nir_intrinsic_barrier
:
2336 cs_prog_data
->uses_barrier
= true;
2339 case nir_intrinsic_load_local_invocation_id
:
2340 case nir_intrinsic_load_work_group_id
: {
2341 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2342 fs_reg val
= nir_system_values
[sv
];
2343 assert(val
.file
!= BAD_FILE
);
2344 dest
.type
= val
.type
;
2345 for (unsigned i
= 0; i
< 3; i
++)
2346 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2350 case nir_intrinsic_load_num_work_groups
: {
2351 const unsigned surface
=
2352 cs_prog_data
->binding_table
.work_groups_start
;
2354 cs_prog_data
->uses_num_work_groups
= true;
2356 fs_reg surf_index
= brw_imm_ud(surface
);
2357 brw_mark_surface_used(prog_data
, surface
);
2359 /* Read the 3 GLuint components of gl_NumWorkGroups */
2360 for (unsigned i
= 0; i
< 3; i
++) {
2361 fs_reg read_result
=
2362 emit_untyped_read(bld
, surf_index
,
2364 1 /* dims */, 1 /* size */,
2365 BRW_PREDICATE_NONE
);
2366 read_result
.type
= dest
.type
;
2367 bld
.MOV(dest
, read_result
);
2368 dest
= offset(dest
, bld
, 1);
2373 case nir_intrinsic_shared_atomic_add
:
2374 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2376 case nir_intrinsic_shared_atomic_imin
:
2377 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2379 case nir_intrinsic_shared_atomic_umin
:
2380 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2382 case nir_intrinsic_shared_atomic_imax
:
2383 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2385 case nir_intrinsic_shared_atomic_umax
:
2386 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2388 case nir_intrinsic_shared_atomic_and
:
2389 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2391 case nir_intrinsic_shared_atomic_or
:
2392 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2394 case nir_intrinsic_shared_atomic_xor
:
2395 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2397 case nir_intrinsic_shared_atomic_exchange
:
2398 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2400 case nir_intrinsic_shared_atomic_comp_swap
:
2401 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2404 case nir_intrinsic_load_shared
: {
2405 assert(devinfo
->gen
>= 7);
2407 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2409 /* Get the offset to read from */
2411 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2413 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
2415 offset_reg
= vgrf(glsl_type::uint_type
);
2417 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2418 brw_imm_ud(instr
->const_index
[0]));
2421 /* Read the vector */
2422 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2424 instr
->num_components
,
2425 BRW_PREDICATE_NONE
);
2426 read_result
.type
= dest
.type
;
2427 for (int i
= 0; i
< instr
->num_components
; i
++)
2428 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2433 case nir_intrinsic_store_shared
: {
2434 assert(devinfo
->gen
>= 7);
2437 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2440 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2443 unsigned writemask
= instr
->const_index
[1];
2445 /* Combine groups of consecutive enabled channels in one write
2446 * message. We use ffs to find the first enabled channel and then ffs on
2447 * the bit-inverse, down-shifted writemask to determine the length of
2448 * the block of enabled bits.
2451 unsigned first_component
= ffs(writemask
) - 1;
2452 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2455 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2457 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
2458 4 * first_component
);
2460 offset_reg
= vgrf(glsl_type::uint_type
);
2462 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2463 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2466 emit_untyped_write(bld
, surf_index
, offset_reg
,
2467 offset(val_reg
, bld
, first_component
),
2468 1 /* dims */, length
,
2469 BRW_PREDICATE_NONE
);
2471 /* Clear the bits in the writemask that we just wrote, then try
2472 * again to see if more channels are left.
2474 writemask
&= (15 << (first_component
+ length
));
2481 nir_emit_intrinsic(bld
, instr
);
2487 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2490 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2491 dest
= get_nir_dest(instr
->dest
);
2493 switch (instr
->intrinsic
) {
2494 case nir_intrinsic_atomic_counter_inc
:
2495 case nir_intrinsic_atomic_counter_dec
:
2496 case nir_intrinsic_atomic_counter_read
: {
2497 /* Get the arguments of the atomic intrinsic. */
2498 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2499 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2500 instr
->const_index
[0]);
2503 /* Emit a surface read or atomic op. */
2504 switch (instr
->intrinsic
) {
2505 case nir_intrinsic_atomic_counter_read
:
2506 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2509 case nir_intrinsic_atomic_counter_inc
:
2510 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2511 fs_reg(), 1, 1, BRW_AOP_INC
);
2514 case nir_intrinsic_atomic_counter_dec
:
2515 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2516 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2520 unreachable("Unreachable");
2523 /* Assign the result. */
2524 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2526 /* Mark the surface as used. */
2527 brw_mark_surface_used(stage_prog_data
, surface
);
2531 case nir_intrinsic_image_load
:
2532 case nir_intrinsic_image_store
:
2533 case nir_intrinsic_image_atomic_add
:
2534 case nir_intrinsic_image_atomic_min
:
2535 case nir_intrinsic_image_atomic_max
:
2536 case nir_intrinsic_image_atomic_and
:
2537 case nir_intrinsic_image_atomic_or
:
2538 case nir_intrinsic_image_atomic_xor
:
2539 case nir_intrinsic_image_atomic_exchange
:
2540 case nir_intrinsic_image_atomic_comp_swap
: {
2541 using namespace image_access
;
2543 /* Get the referenced image variable and type. */
2544 const nir_variable
*var
= instr
->variables
[0]->var
;
2545 const glsl_type
*type
= var
->type
->without_array();
2546 const brw_reg_type base_type
= get_image_base_type(type
);
2548 /* Get some metadata from the image intrinsic. */
2549 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2550 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2551 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2552 const mesa_format format
=
2553 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2554 _mesa_get_shader_image_format(var
->data
.image
.format
));
2556 /* Get the arguments of the image intrinsic. */
2557 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2558 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2559 BRW_REGISTER_TYPE_UD
);
2560 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2561 retype(get_nir_src(instr
->src
[2]), base_type
) :
2563 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2564 retype(get_nir_src(instr
->src
[3]), base_type
) :
2568 /* Emit an image load, store or atomic op. */
2569 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2570 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2572 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2573 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2576 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2577 surf_dims
, arr_dims
, info
->dest_components
,
2578 get_image_atomic_op(instr
->intrinsic
, type
));
2580 /* Assign the result. */
2581 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2582 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2583 offset(tmp
, bld
, c
));
2587 case nir_intrinsic_memory_barrier_atomic_counter
:
2588 case nir_intrinsic_memory_barrier_buffer
:
2589 case nir_intrinsic_memory_barrier_image
:
2590 case nir_intrinsic_memory_barrier
: {
2591 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2592 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2597 case nir_intrinsic_group_memory_barrier
:
2598 case nir_intrinsic_memory_barrier_shared
:
2599 /* We treat these workgroup-level barriers as no-ops. This should be
2600 * safe at present and as long as:
2602 * - Memory access instructions are not subsequently reordered by the
2603 * compiler back-end.
2605 * - All threads from a given compute shader workgroup fit within a
2606 * single subslice and therefore talk to the same HDC shared unit
2607 * what supposedly guarantees ordering and coherency between threads
2608 * from the same workgroup. This may change in the future when we
2609 * start splitting workgroups across multiple subslices.
2611 * - The context is not in fault-and-stream mode, which could cause
2612 * memory transactions (including to SLM) prior to the barrier to be
2613 * replayed after the barrier if a pagefault occurs. This shouldn't
2614 * be a problem up to and including SKL because fault-and-stream is
2615 * not usable due to hardware issues, but that's likely to change in
2620 case nir_intrinsic_shader_clock
: {
2621 /* We cannot do anything if there is an event, so ignore it for now */
2622 fs_reg shader_clock
= get_timestamp(bld
);
2623 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2625 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2629 case nir_intrinsic_image_size
: {
2630 /* Get the referenced image variable and type. */
2631 const nir_variable
*var
= instr
->variables
[0]->var
;
2632 const glsl_type
*type
= var
->type
->without_array();
2634 /* Get the size of the image. */
2635 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2636 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2638 /* For 1DArray image types, the array index is stored in the Z component.
2639 * Fix this by swizzling the Z component to the Y component.
2641 const bool is_1d_array_image
=
2642 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2643 type
->sampler_array
;
2645 /* For CubeArray images, we should count the number of cubes instead
2646 * of the number of faces. Fix it by dividing the (Z component) by 6.
2648 const bool is_cube_array_image
=
2649 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2650 type
->sampler_array
;
2652 /* Copy all the components. */
2653 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2654 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2655 if ((int)c
>= type
->coordinate_components()) {
2656 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2658 } else if (c
== 1 && is_1d_array_image
) {
2659 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2660 offset(size
, bld
, 2));
2661 } else if (c
== 2 && is_cube_array_image
) {
2662 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2663 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2664 offset(size
, bld
, c
), brw_imm_d(6));
2666 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2667 offset(size
, bld
, c
));
2674 case nir_intrinsic_image_samples
:
2675 /* The driver does not support multi-sampled images. */
2676 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2679 case nir_intrinsic_load_uniform
: {
2680 /* Offsets are in bytes but they should always be multiples of 4 */
2681 assert(instr
->const_index
[0] % 4 == 0);
2683 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2685 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2687 /* Offsets are in bytes but they should always be multiples of 4 */
2688 assert(const_offset
->u32
[0] % 4 == 0);
2689 src
.reg_offset
= const_offset
->u32
[0] / 4;
2691 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2692 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2695 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
2696 BRW_REGISTER_TYPE_UD
);
2698 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
2699 * go past the end of the uniform. In order to keep the n'th
2700 * component from running past, we subtract off the size of all but
2701 * one component of the vector.
2703 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
2704 unsigned read_size
= instr
->const_index
[1] -
2705 (instr
->num_components
- 1) * 4;
2707 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2708 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
2709 offset(dest
, bld
, j
), offset(src
, bld
, j
),
2710 indirect
, brw_imm_ud(read_size
));
2716 case nir_intrinsic_load_ubo
: {
2717 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2721 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2722 const_index
->u32
[0];
2723 surf_index
= brw_imm_ud(index
);
2724 brw_mark_surface_used(prog_data
, index
);
2726 /* The block index is not a constant. Evaluate the index expression
2727 * per-channel and add the base UBO index; we have to select a value
2728 * from any live channel.
2730 surf_index
= vgrf(glsl_type::uint_type
);
2731 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2732 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2733 surf_index
= bld
.emit_uniformize(surf_index
);
2735 /* Assume this may touch any UBO. It would be nice to provide
2736 * a tighter bound, but the array information is already lowered away.
2738 brw_mark_surface_used(prog_data
,
2739 stage_prog_data
->binding_table
.ubo_start
+
2740 nir
->info
.num_ubos
- 1);
2743 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2744 if (const_offset
== NULL
) {
2745 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2746 BRW_REGISTER_TYPE_D
);
2748 for (int i
= 0; i
< instr
->num_components
; i
++)
2749 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2750 base_offset
, i
* 4);
2752 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2753 packed_consts
.type
= dest
.type
;
2755 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
2756 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2757 surf_index
, const_offset_reg
);
2759 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2760 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
2762 /* The std140 packing rules don't allow vectors to cross 16-byte
2763 * boundaries, and a reg is 32 bytes.
2765 assert(packed_consts
.subreg_offset
< 32);
2767 bld
.MOV(dest
, packed_consts
);
2768 dest
= offset(dest
, bld
, 1);
2774 case nir_intrinsic_load_ssbo
: {
2775 assert(devinfo
->gen
>= 7);
2777 nir_const_value
*const_uniform_block
=
2778 nir_src_as_const_value(instr
->src
[0]);
2781 if (const_uniform_block
) {
2782 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2783 const_uniform_block
->u32
[0];
2784 surf_index
= brw_imm_ud(index
);
2785 brw_mark_surface_used(prog_data
, index
);
2787 surf_index
= vgrf(glsl_type::uint_type
);
2788 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2789 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2791 /* Assume this may touch any UBO. It would be nice to provide
2792 * a tighter bound, but the array information is already lowered away.
2794 brw_mark_surface_used(prog_data
,
2795 stage_prog_data
->binding_table
.ssbo_start
+
2796 nir
->info
.num_ssbos
- 1);
2800 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2802 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
2804 offset_reg
= get_nir_src(instr
->src
[1]);
2807 /* Read the vector */
2808 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2810 instr
->num_components
,
2811 BRW_PREDICATE_NONE
);
2812 read_result
.type
= dest
.type
;
2813 for (int i
= 0; i
< instr
->num_components
; i
++)
2814 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2819 case nir_intrinsic_load_input
: {
2821 if (stage
== MESA_SHADER_VERTEX
) {
2822 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2824 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2825 instr
->const_index
[0]);
2828 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2829 assert(const_offset
&& "Indirect input loads not allowed");
2830 src
= offset(src
, bld
, const_offset
->u32
[0]);
2832 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2833 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2838 case nir_intrinsic_store_ssbo
: {
2839 assert(devinfo
->gen
>= 7);
2843 nir_const_value
*const_uniform_block
=
2844 nir_src_as_const_value(instr
->src
[1]);
2845 if (const_uniform_block
) {
2846 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2847 const_uniform_block
->u32
[0];
2848 surf_index
= brw_imm_ud(index
);
2849 brw_mark_surface_used(prog_data
, index
);
2851 surf_index
= vgrf(glsl_type::uint_type
);
2852 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2853 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2855 brw_mark_surface_used(prog_data
,
2856 stage_prog_data
->binding_table
.ssbo_start
+
2857 nir
->info
.num_ssbos
- 1);
2861 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2864 unsigned writemask
= instr
->const_index
[0];
2866 /* Combine groups of consecutive enabled channels in one write
2867 * message. We use ffs to find the first enabled channel and then ffs on
2868 * the bit-inverse, down-shifted writemask to determine the length of
2869 * the block of enabled bits.
2872 unsigned first_component
= ffs(writemask
) - 1;
2873 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2876 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2878 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
2880 offset_reg
= vgrf(glsl_type::uint_type
);
2882 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2883 brw_imm_ud(4 * first_component
));
2886 emit_untyped_write(bld
, surf_index
, offset_reg
,
2887 offset(val_reg
, bld
, first_component
),
2888 1 /* dims */, length
,
2889 BRW_PREDICATE_NONE
);
2891 /* Clear the bits in the writemask that we just wrote, then try
2892 * again to see if more channels are left.
2894 writemask
&= (15 << (first_component
+ length
));
2899 case nir_intrinsic_store_output
: {
2900 fs_reg src
= get_nir_src(instr
->src
[0]);
2901 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2902 instr
->const_index
[0]);
2904 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2905 assert(const_offset
&& "Indirect output stores not allowed");
2906 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
2908 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2909 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2914 case nir_intrinsic_ssbo_atomic_add
:
2915 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2917 case nir_intrinsic_ssbo_atomic_imin
:
2918 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2920 case nir_intrinsic_ssbo_atomic_umin
:
2921 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2923 case nir_intrinsic_ssbo_atomic_imax
:
2924 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2926 case nir_intrinsic_ssbo_atomic_umax
:
2927 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2929 case nir_intrinsic_ssbo_atomic_and
:
2930 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2932 case nir_intrinsic_ssbo_atomic_or
:
2933 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2935 case nir_intrinsic_ssbo_atomic_xor
:
2936 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2938 case nir_intrinsic_ssbo_atomic_exchange
:
2939 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2941 case nir_intrinsic_ssbo_atomic_comp_swap
:
2942 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2945 case nir_intrinsic_get_buffer_size
: {
2946 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2947 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
2948 int reg_width
= dispatch_width
/ 8;
2951 fs_reg source
= brw_imm_d(0);
2953 int mlen
= 1 * reg_width
;
2955 /* A resinfo's sampler message is used to get the buffer size.
2956 * The SIMD8's writeback message consists of four registers and
2957 * SIMD16's writeback message consists of 8 destination registers
2958 * (two per each component), although we are only interested on the
2959 * first component, where resinfo returns the buffer size for
2962 int regs_written
= 4 * mlen
;
2963 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2964 BRW_REGISTER_TYPE_UD
);
2965 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2966 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2967 BRW_REGISTER_TYPE_UD
);
2968 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2969 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2970 src_payload
, brw_imm_ud(index
));
2971 inst
->header_size
= 0;
2973 inst
->regs_written
= regs_written
;
2975 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2977 brw_mark_surface_used(prog_data
, index
);
2982 unreachable("unknown intrinsic");
2987 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2988 int op
, nir_intrinsic_instr
*instr
)
2991 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2992 dest
= get_nir_dest(instr
->dest
);
2995 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2996 if (const_surface
) {
2997 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2998 const_surface
->u32
[0];
2999 surface
= brw_imm_ud(surf_index
);
3000 brw_mark_surface_used(prog_data
, surf_index
);
3002 surface
= vgrf(glsl_type::uint_type
);
3003 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3004 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3006 /* Assume this may touch any SSBO. This is the same we do for other
3007 * UBO/SSBO accesses with non-constant surface.
3009 brw_mark_surface_used(prog_data
,
3010 stage_prog_data
->binding_table
.ssbo_start
+
3011 nir
->info
.num_ssbos
- 1);
3014 fs_reg offset
= get_nir_src(instr
->src
[1]);
3015 fs_reg data1
= get_nir_src(instr
->src
[2]);
3017 if (op
== BRW_AOP_CMPWR
)
3018 data2
= get_nir_src(instr
->src
[3]);
3020 /* Emit the actual atomic operation operation */
3022 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3024 1 /* dims */, 1 /* rsize */,
3026 BRW_PREDICATE_NONE
);
3027 dest
.type
= atomic_result
.type
;
3028 bld
.MOV(dest
, atomic_result
);
3032 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3033 int op
, nir_intrinsic_instr
*instr
)
3036 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3037 dest
= get_nir_dest(instr
->dest
);
3039 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3040 fs_reg offset
= get_nir_src(instr
->src
[0]);
3041 fs_reg data1
= get_nir_src(instr
->src
[1]);
3043 if (op
== BRW_AOP_CMPWR
)
3044 data2
= get_nir_src(instr
->src
[2]);
3046 /* Emit the actual atomic operation operation */
3048 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3050 1 /* dims */, 1 /* rsize */,
3052 BRW_PREDICATE_NONE
);
3053 dest
.type
= atomic_result
.type
;
3054 bld
.MOV(dest
, atomic_result
);
3058 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3060 unsigned texture
= instr
->texture_index
;
3061 unsigned sampler
= instr
->sampler_index
;
3062 fs_reg
texture_reg(brw_imm_ud(texture
));
3063 fs_reg
sampler_reg(brw_imm_ud(sampler
));
3065 int gather_component
= instr
->component
;
3067 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3070 int lod_components
= 0;
3072 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
3074 /* The hardware requires a LOD for buffer textures */
3075 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3078 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3079 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3080 switch (instr
->src
[i
].src_type
) {
3081 case nir_tex_src_bias
:
3082 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3084 case nir_tex_src_comparitor
:
3085 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
3087 case nir_tex_src_coord
:
3088 switch (instr
->op
) {
3090 case nir_texop_txf_ms
:
3091 case nir_texop_samples_identical
:
3092 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
3095 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
3099 case nir_tex_src_ddx
:
3100 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3101 lod_components
= nir_tex_instr_src_size(instr
, i
);
3103 case nir_tex_src_ddy
:
3104 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
3106 case nir_tex_src_lod
:
3107 switch (instr
->op
) {
3109 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
3112 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
3115 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3119 case nir_tex_src_ms_index
:
3120 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
3123 case nir_tex_src_offset
: {
3124 nir_const_value
*const_offset
=
3125 nir_src_as_const_value(instr
->src
[i
].src
);
3127 tex_offset
= brw_imm_ud(brw_texture_offset(const_offset
->i32
, 3));
3129 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
3134 case nir_tex_src_projector
:
3135 unreachable("should be lowered");
3137 case nir_tex_src_texture_offset
: {
3138 /* Figure out the highest possible texture index and mark it as used */
3139 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3140 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3141 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3143 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3145 brw_mark_surface_used(prog_data
, max_used
);
3147 /* Emit code to evaluate the actual indexing expression */
3148 texture_reg
= vgrf(glsl_type::uint_type
);
3149 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3150 texture_reg
= bld
.emit_uniformize(texture_reg
);
3154 case nir_tex_src_sampler_offset
: {
3155 /* Emit code to evaluate the actual indexing expression */
3156 sampler_reg
= vgrf(glsl_type::uint_type
);
3157 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3158 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3163 unreachable("unknown texture source");
3167 if (instr
->op
== nir_texop_txf_ms
||
3168 instr
->op
== nir_texop_samples_identical
) {
3169 if (devinfo
->gen
>= 7 &&
3170 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3171 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3173 mcs
= brw_imm_ud(0u);
3177 enum glsl_base_type dest_base_type
=
3178 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3180 const glsl_type
*dest_type
=
3181 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3184 ir_texture_opcode op
;
3185 switch (instr
->op
) {
3186 case nir_texop_lod
: op
= ir_lod
; break;
3187 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3188 case nir_texop_tex
: op
= ir_tex
; break;
3189 case nir_texop_tg4
: op
= ir_tg4
; break;
3190 case nir_texop_txb
: op
= ir_txb
; break;
3191 case nir_texop_txd
: op
= ir_txd
; break;
3192 case nir_texop_txf
: op
= ir_txf
; break;
3193 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3194 case nir_texop_txl
: op
= ir_txl
; break;
3195 case nir_texop_txs
: op
= ir_txs
; break;
3196 case nir_texop_texture_samples
: {
3197 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3198 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3199 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3200 texture_reg
, texture_reg
);
3202 inst
->header_size
= 1;
3203 inst
->base_mrf
= -1;
3206 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3208 unreachable("unknown texture opcode");
3211 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3212 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3213 tex_offset
, mcs
, gather_component
, is_cube_array
,
3214 texture
, texture_reg
, sampler
, sampler_reg
);
3216 fs_reg dest
= get_nir_dest(instr
->dest
);
3217 dest
.type
= this->result
.type
;
3218 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3219 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3220 dest
, this->result
),
3221 (1 << num_components
) - 1);
3225 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3227 switch (instr
->type
) {
3228 case nir_jump_break
:
3229 bld
.emit(BRW_OPCODE_BREAK
);
3231 case nir_jump_continue
:
3232 bld
.emit(BRW_OPCODE_CONTINUE
);
3234 case nir_jump_return
:
3236 unreachable("unknown jump");