2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_optimization.h"
51 #include "../glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
62 this->frag_color
= ir
;
63 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
65 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
66 this->frag_depth
= ir
;
69 if (ir
->mode
== ir_var_in
) {
70 if (!strcmp(ir
->name
, "gl_FragCoord")) {
71 reg
= emit_fragcoord_interpolation(ir
);
72 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
73 reg
= emit_frontfacing_interpolation(ir
);
75 reg
= emit_general_interpolation(ir
);
78 hash_table_insert(this->variable_ht
, reg
, ir
);
82 if (ir
->mode
== ir_var_uniform
) {
83 int param_index
= c
->prog_data
.nr_params
;
85 if (c
->dispatch_width
== 16) {
86 if (!variable_storage(ir
)) {
87 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
92 if (!strncmp(ir
->name
, "gl_", 3)) {
93 setup_builtin_uniform_values(ir
);
95 setup_uniform_values(ir
->location
, ir
->type
);
98 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
99 reg
->type
= brw_type_for_base_type(ir
->type
);
103 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
105 hash_table_insert(this->variable_ht
, reg
, ir
);
109 fs_visitor::visit(ir_dereference_variable
*ir
)
111 fs_reg
*reg
= variable_storage(ir
->var
);
116 fs_visitor::visit(ir_dereference_record
*ir
)
118 const glsl_type
*struct_type
= ir
->record
->type
;
120 ir
->record
->accept(this);
122 unsigned int offset
= 0;
123 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
124 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
126 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
128 this->result
.reg_offset
+= offset
;
129 this->result
.type
= brw_type_for_base_type(ir
->type
);
133 fs_visitor::visit(ir_dereference_array
*ir
)
138 ir
->array
->accept(this);
139 index
= ir
->array_index
->as_constant();
141 element_size
= type_size(ir
->type
);
142 this->result
.type
= brw_type_for_base_type(ir
->type
);
145 assert(this->result
.file
== UNIFORM
||
146 (this->result
.file
== GRF
&&
147 this->result
.reg
!= 0));
148 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
150 assert(!"FINISHME: non-constant array element");
154 /* Instruction selection: Produce a MOV.sat instead of
155 * MIN(MAX(val, 0), 1) when possible.
158 fs_visitor::try_emit_saturate(ir_expression
*ir
)
160 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
165 this->result
= reg_undef
;
166 sat_val
->accept(this);
167 fs_reg src
= this->result
;
169 this->result
= fs_reg(this, ir
->type
);
170 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
171 inst
->saturate
= true;
177 fs_visitor::visit(ir_expression
*ir
)
179 unsigned int operand
;
183 assert(ir
->get_num_operands() <= 2);
185 if (try_emit_saturate(ir
))
188 /* This is where our caller would like us to put the result, if possible. */
189 fs_reg saved_result_storage
= this->result
;
191 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
192 this->result
= reg_undef
;
193 ir
->operands
[operand
]->accept(this);
194 if (this->result
.file
== BAD_FILE
) {
196 fail("Failed to get tree for expression operand:\n");
197 ir
->operands
[operand
]->accept(&v
);
199 op
[operand
] = this->result
;
201 /* Matrix expression operands should have been broken down to vector
202 * operations already.
204 assert(!ir
->operands
[operand
]->type
->is_matrix());
205 /* And then those vector operands should have been broken down to scalar.
207 assert(!ir
->operands
[operand
]->type
->is_vector());
210 /* Inherit storage from our parent if possible, and otherwise we
213 if (saved_result_storage
.file
== BAD_FILE
) {
214 this->result
= fs_reg(this, ir
->type
);
216 this->result
= saved_result_storage
;
219 switch (ir
->operation
) {
220 case ir_unop_logic_not
:
221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
222 * ones complement of the whole register, not just bit 0.
224 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
227 op
[0].negate
= !op
[0].negate
;
228 this->result
= op
[0];
232 op
[0].negate
= false;
233 this->result
= op
[0];
236 temp
= fs_reg(this, ir
->type
);
238 /* Unalias the destination. (imagine a = sign(a)) */
239 this->result
= fs_reg(this, ir
->type
);
241 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
243 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
244 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
245 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
246 inst
->predicated
= true;
248 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
249 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
250 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
251 inst
->predicated
= true;
255 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
259 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
262 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
266 assert(!"not reached: should be handled by ir_explog_to_explog2");
269 case ir_unop_sin_reduced
:
270 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
273 case ir_unop_cos_reduced
:
274 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
278 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
281 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
285 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
288 assert(!"not reached: should be handled by ir_sub_to_add_neg");
292 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
295 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
302 case ir_binop_greater
:
303 case ir_binop_lequal
:
304 case ir_binop_gequal
:
306 case ir_binop_all_equal
:
307 case ir_binop_nequal
:
308 case ir_binop_any_nequal
:
310 /* original gen4 does implicit conversion before comparison. */
312 temp
.type
= op
[0].type
;
314 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
315 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
316 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
319 case ir_binop_logic_xor
:
320 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
323 case ir_binop_logic_or
:
324 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
327 case ir_binop_logic_and
:
328 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
333 assert(!"not reached: should be handled by brw_fs_channel_expressions");
337 assert(!"not reached: should be handled by lower_noise");
340 case ir_quadop_vector
:
341 assert(!"not reached: should be handled by lower_quadop_vector");
345 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
349 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
356 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
361 /* original gen4 does implicit conversion before comparison. */
363 temp
.type
= op
[0].type
;
365 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
366 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
367 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
371 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
374 op
[0].negate
= !op
[0].negate
;
375 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
376 this->result
.negate
= true;
379 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
382 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
384 case ir_unop_round_even
:
385 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
389 if (intel
->gen
>= 6) {
390 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
391 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
393 /* Unalias the destination */
394 this->result
= fs_reg(this, ir
->type
);
396 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
397 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
399 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
400 inst
->predicated
= true;
404 if (intel
->gen
>= 6) {
405 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
406 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
408 /* Unalias the destination */
409 this->result
= fs_reg(this, ir
->type
);
411 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
412 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
414 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
415 inst
->predicated
= true;
420 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
423 case ir_unop_bit_not
:
424 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
426 case ir_binop_bit_and
:
427 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
429 case ir_binop_bit_xor
:
430 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
432 case ir_binop_bit_or
:
433 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
437 case ir_binop_lshift
:
438 case ir_binop_rshift
:
439 assert(!"GLSL 1.30 features unsupported");
445 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
446 const glsl_type
*type
, bool predicated
)
448 switch (type
->base_type
) {
449 case GLSL_TYPE_FLOAT
:
453 for (unsigned int i
= 0; i
< type
->components(); i
++) {
454 l
.type
= brw_type_for_base_type(type
);
455 r
.type
= brw_type_for_base_type(type
);
457 if (predicated
|| !l
.equals(&r
)) {
458 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
459 inst
->predicated
= predicated
;
466 case GLSL_TYPE_ARRAY
:
467 for (unsigned int i
= 0; i
< type
->length
; i
++) {
468 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
472 case GLSL_TYPE_STRUCT
:
473 for (unsigned int i
= 0; i
< type
->length
; i
++) {
474 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
479 case GLSL_TYPE_SAMPLER
:
483 assert(!"not reached");
489 fs_visitor::visit(ir_assignment
*ir
)
494 /* FINISHME: arrays on the lhs */
495 this->result
= reg_undef
;
496 ir
->lhs
->accept(this);
499 /* If we're doing a direct assignment, an RHS expression could
500 * drop its result right into our destination. Otherwise, tell it
504 !(ir
->lhs
->type
->is_scalar() ||
505 (ir
->lhs
->type
->is_vector() &&
506 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1))) {
507 this->result
= reg_undef
;
510 ir
->rhs
->accept(this);
513 assert(l
.file
!= BAD_FILE
);
514 assert(r
.file
!= BAD_FILE
);
517 emit_bool_to_cond_code(ir
->condition
);
520 if (ir
->lhs
->type
->is_scalar() ||
521 ir
->lhs
->type
->is_vector()) {
522 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
523 if (ir
->write_mask
& (1 << i
)) {
525 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
526 inst
->predicated
= true;
527 } else if (!l
.equals(&r
)) {
528 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
536 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
541 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
552 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
553 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
554 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
555 fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
556 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
557 inst
->saturate
= true;
559 coordinate
.reg_offset
++;
561 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
564 if (ir
->op
== ir_tex
) {
565 /* There's no plain shadow compare message, so we use shadow
566 * compare with a bias of 0.0.
568 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
570 } else if (ir
->op
== ir_txb
) {
571 this->result
= reg_undef
;
572 ir
->lod_info
.bias
->accept(this);
573 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
576 assert(ir
->op
== ir_txl
);
577 this->result
= reg_undef
;
578 ir
->lod_info
.lod
->accept(this);
579 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
583 this->result
= reg_undef
;
584 ir
->shadow_comparitor
->accept(this);
585 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
587 } else if (ir
->op
== ir_tex
) {
588 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
589 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
591 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
592 inst
->saturate
= true;
593 coordinate
.reg_offset
++;
595 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
597 } else if (ir
->op
== ir_txd
) {
598 ir
->lod_info
.grad
.dPdx
->accept(this);
599 fs_reg dPdx
= this->result
;
601 ir
->lod_info
.grad
.dPdy
->accept(this);
602 fs_reg dPdy
= this->result
;
604 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
605 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
606 coordinate
.reg_offset
++;
608 /* the slots for u and v are always present, but r is optional */
609 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
612 * dPdx = dudx, dvdx, drdx
613 * dPdy = dudy, dvdy, drdy
615 * 2-arg: dudx dvdx dudy dvdy
616 * dPdx.x dPdx.y dPdy.x dPdy.y
619 * 3-arg: dudx dvdx drdx dudy dvdy drdy
620 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
623 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
624 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
629 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
630 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
635 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
636 * instructions. We'll need to do SIMD16 here.
638 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
640 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
641 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
,
642 base_mrf
+ mlen
+ i
* 2),
644 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
645 inst
->saturate
= true;
646 coordinate
.reg_offset
++;
649 /* lod/bias appears after u/v/r. */
652 if (ir
->op
== ir_txb
) {
653 this->result
= reg_undef
;
654 ir
->lod_info
.bias
->accept(this);
655 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
658 this->result
= reg_undef
;
659 ir
->lod_info
.lod
->accept(this);
660 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
664 /* The unused upper half. */
667 /* Now, since we're doing simd16, the return is 2 interleaved
668 * vec4s where the odd-indexed ones are junk. We'll need to move
669 * this weirdness around to the expected layout.
673 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
675 dst
.type
= BRW_REGISTER_TYPE_F
;
678 fs_inst
*inst
= NULL
;
681 inst
= emit(FS_OPCODE_TEX
, dst
);
684 inst
= emit(FS_OPCODE_TXB
, dst
);
687 inst
= emit(FS_OPCODE_TXL
, dst
);
690 inst
= emit(FS_OPCODE_TXD
, dst
);
693 assert(!"GLSL 1.30 features unsupported");
696 inst
->base_mrf
= base_mrf
;
698 inst
->header_present
= true;
701 for (int i
= 0; i
< 4; i
++) {
702 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
703 orig_dst
.reg_offset
++;
711 /* gen5's sampler has slots for u, v, r, array index, then optional
712 * parameters like shadow comparitor or LOD bias. If optional
713 * parameters aren't present, those base slots are optional and don't
714 * need to be included in the message.
716 * We don't fill in the unnecessary slots regardless, which may look
717 * surprising in the disassembly.
720 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
725 int reg_width
= c
->dispatch_width
/ 8;
726 bool header_present
= false;
729 /* The offsets set up by the ir_texture visitor are in the
730 * m1 header, so we can't go headerless.
732 header_present
= true;
737 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
738 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
739 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
),
741 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
742 inst
->saturate
= true;
743 coordinate
.reg_offset
++;
745 mlen
+= ir
->coordinate
->type
->vector_elements
* reg_width
;
747 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
748 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
750 this->result
= reg_undef
;
751 ir
->shadow_comparitor
->accept(this);
752 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
756 fs_inst
*inst
= NULL
;
759 inst
= emit(FS_OPCODE_TEX
, dst
);
762 this->result
= reg_undef
;
763 ir
->lod_info
.bias
->accept(this);
764 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
765 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
768 inst
= emit(FS_OPCODE_TXB
, dst
);
772 this->result
= reg_undef
;
773 ir
->lod_info
.lod
->accept(this);
774 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
775 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
778 inst
= emit(FS_OPCODE_TXL
, dst
);
781 ir
->lod_info
.grad
.dPdx
->accept(this);
782 fs_reg dPdx
= this->result
;
784 ir
->lod_info
.grad
.dPdy
->accept(this);
785 fs_reg dPdy
= this->result
;
787 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
791 * dPdx = dudx, dvdx, drdx
792 * dPdy = dudy, dvdy, drdy
794 * Load up these values:
795 * - dudx dudy dvdx dvdy drdx drdy
796 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
798 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
799 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
803 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
808 inst
= emit(FS_OPCODE_TXD
, dst
);
812 assert(!"GLSL 1.30 features unsupported");
815 inst
->base_mrf
= base_mrf
;
817 inst
->header_present
= header_present
;
820 fail("Message length >11 disallowed by hardware\n");
827 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
832 int reg_width
= c
->dispatch_width
/ 8;
833 bool header_present
= false;
836 /* The offsets set up by the ir_texture visitor are in the
837 * m1 header, so we can't go headerless.
839 header_present
= true;
844 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
845 ir
->shadow_comparitor
->accept(this);
846 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
850 /* Set up the LOD info */
855 ir
->lod_info
.bias
->accept(this);
856 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
860 ir
->lod_info
.lod
->accept(this);
861 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
865 if (c
->dispatch_width
== 16)
866 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
868 ir
->lod_info
.grad
.dPdx
->accept(this);
869 fs_reg dPdx
= this->result
;
871 ir
->lod_info
.grad
.dPdy
->accept(this);
872 fs_reg dPdy
= this->result
;
874 /* Load dPdx and the coordinate together:
875 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
877 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
878 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
880 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
881 inst
->saturate
= true;
882 coordinate
.reg_offset
++;
885 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
889 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
896 assert(!"GLSL 1.30 features unsupported");
900 /* Set up the coordinate (except for TXD where it was done earlier) */
901 if (ir
->op
!= ir_txd
) {
902 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
903 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
905 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
906 inst
->saturate
= true;
907 coordinate
.reg_offset
++;
912 /* Generate the SEND */
913 fs_inst
*inst
= NULL
;
915 case ir_tex
: inst
= emit(FS_OPCODE_TEX
, dst
); break;
916 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
917 case ir_txl
: inst
= emit(FS_OPCODE_TXL
, dst
); break;
918 case ir_txd
: inst
= emit(FS_OPCODE_TXD
, dst
); break;
919 case ir_txf
: assert(!"TXF unsupported.");
921 inst
->base_mrf
= base_mrf
;
923 inst
->header_present
= header_present
;
926 fail("Message length >11 disallowed by hardware\n");
933 fs_visitor::visit(ir_texture
*ir
)
935 fs_inst
*inst
= NULL
;
937 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
938 sampler
= fp
->Base
.SamplerUnits
[sampler
];
940 /* Our hardware doesn't have a sample_d_c message, so shadow compares
941 * for textureGrad/TXD need to be emulated with instructions.
943 bool hw_compare_supported
= ir
->op
!= ir_txd
;
944 if (ir
->shadow_comparitor
&& !hw_compare_supported
) {
945 assert(c
->key
.compare_funcs
[sampler
] != GL_NONE
);
946 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */
947 if (c
->key
.compare_funcs
[sampler
] == GL_ALWAYS
)
948 return swizzle_result(ir
, fs_reg(1.0f
), sampler
);
949 else if (c
->key
.compare_funcs
[sampler
] == GL_NEVER
)
950 return swizzle_result(ir
, fs_reg(0.0f
), sampler
);
953 this->result
= reg_undef
;
954 ir
->coordinate
->accept(this);
955 fs_reg coordinate
= this->result
;
957 if (ir
->offset
!= NULL
) {
958 ir_constant
*offset
= ir
->offset
->as_constant();
959 assert(offset
!= NULL
);
961 signed char offsets
[3];
962 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
963 offsets
[i
] = (signed char) offset
->value
.i
[i
];
965 /* Combine all three offsets into a single unsigned dword:
967 * bits 11:8 - U Offset (X component)
968 * bits 7:4 - V Offset (Y component)
969 * bits 3:0 - R Offset (Z component)
971 unsigned offset_bits
= 0;
972 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
973 const unsigned shift
= 4 * (2 - i
);
974 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
977 /* Explicitly set up the message header by copying g0 to msg reg m1. */
978 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
979 fs_reg(GRF
, 0, BRW_REGISTER_TYPE_UD
));
981 /* Then set the offset bits in DWord 2 of the message header. */
983 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
984 BRW_REGISTER_TYPE_UD
)),
985 fs_reg(brw_imm_uw(offset_bits
)));
988 /* Should be lowered by do_lower_texture_projection */
989 assert(!ir
->projector
);
991 /* The 965 requires the EU to do the normalization of GL rectangle
992 * texture coordinates. We use the program parameter state
993 * tracking to get the scaling factor.
995 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
996 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
997 int tokens
[STATE_LENGTH
] = {
1005 if (c
->dispatch_width
== 16) {
1006 fail("rectangle scale uniform setup not supported on 16-wide\n");
1007 this->result
= fs_reg(this, ir
->type
);
1011 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1013 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1016 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1017 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1018 GLuint index
= _mesa_add_state_reference(params
,
1019 (gl_state_index
*)tokens
);
1021 this->param_index
[c
->prog_data
.nr_params
] = index
;
1022 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1023 c
->prog_data
.nr_params
++;
1024 this->param_index
[c
->prog_data
.nr_params
] = index
;
1025 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1026 c
->prog_data
.nr_params
++;
1028 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1029 fs_reg src
= coordinate
;
1032 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1035 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1038 /* Writemasking doesn't eliminate channels on SIMD8 texture
1039 * samples, so don't worry about them.
1041 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1043 if (intel
->gen
>= 7) {
1044 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
1045 } else if (intel
->gen
>= 5) {
1046 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
1048 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
1051 /* If there's an offset, we already set up m1. To avoid the implied move,
1052 * use the null register. Otherwise, we want an implied move from g0.
1054 if (ir
->offset
!= NULL
|| !inst
->header_present
)
1055 inst
->src
[0] = reg_undef
;
1057 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1059 inst
->sampler
= sampler
;
1061 if (ir
->shadow_comparitor
) {
1062 if (hw_compare_supported
) {
1063 inst
->shadow_compare
= true;
1065 ir
->shadow_comparitor
->accept(this);
1066 fs_reg ref
= this->result
;
1069 dst
= fs_reg(this, glsl_type::vec4_type
);
1071 /* FINISHME: This needs to be done pre-filtering. */
1073 uint32_t conditional
= 0;
1074 switch (c
->key
.compare_funcs
[sampler
]) {
1075 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */
1076 case GL_LESS
: conditional
= BRW_CONDITIONAL_L
; break;
1077 case GL_GREATER
: conditional
= BRW_CONDITIONAL_G
; break;
1078 case GL_LEQUAL
: conditional
= BRW_CONDITIONAL_LE
; break;
1079 case GL_GEQUAL
: conditional
= BRW_CONDITIONAL_GE
; break;
1080 case GL_EQUAL
: conditional
= BRW_CONDITIONAL_EQ
; break;
1081 case GL_NOTEQUAL
: conditional
= BRW_CONDITIONAL_NEQ
; break;
1082 default: assert(!"Should not get here: bad shadow compare function");
1085 /* Use conditional moves to load 0 or 1 as the result */
1086 this->current_annotation
= "manual shadow comparison";
1087 for (int i
= 0; i
< 4; i
++) {
1088 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(0.0f
));
1090 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, ref
, value
);
1091 inst
->conditional_mod
= conditional
;
1093 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(1.0f
));
1094 inst
->predicated
= true;
1103 swizzle_result(ir
, dst
, sampler
);
1107 * Swizzle the result of a texture result. This is necessary for
1108 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1111 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1113 this->result
= orig_val
;
1115 if (ir
->type
== glsl_type::float_type
) {
1116 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1117 assert(ir
->sampler
->type
->sampler_shadow
);
1118 } else if (c
->key
.tex_swizzles
[sampler
] != SWIZZLE_NOOP
) {
1119 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1121 for (int i
= 0; i
< 4; i
++) {
1122 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1123 fs_reg l
= swizzled_result
;
1126 if (swiz
== SWIZZLE_ZERO
) {
1127 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1128 } else if (swiz
== SWIZZLE_ONE
) {
1129 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1131 fs_reg r
= orig_val
;
1132 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1133 emit(BRW_OPCODE_MOV
, l
, r
);
1136 this->result
= swizzled_result
;
1141 fs_visitor::visit(ir_swizzle
*ir
)
1143 this->result
= reg_undef
;
1144 ir
->val
->accept(this);
1145 fs_reg val
= this->result
;
1147 if (ir
->type
->vector_elements
== 1) {
1148 this->result
.reg_offset
+= ir
->mask
.x
;
1152 fs_reg result
= fs_reg(this, ir
->type
);
1153 this->result
= result
;
1155 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1156 fs_reg channel
= val
;
1174 channel
.reg_offset
+= swiz
;
1175 emit(BRW_OPCODE_MOV
, result
, channel
);
1176 result
.reg_offset
++;
1181 fs_visitor::visit(ir_discard
*ir
)
1183 assert(ir
->condition
== NULL
); /* FINISHME */
1185 emit(FS_OPCODE_DISCARD
);
1186 kill_emitted
= true;
1190 fs_visitor::visit(ir_constant
*ir
)
1192 /* Set this->result to reg at the bottom of the function because some code
1193 * paths will cause this visitor to be applied to other fields. This will
1194 * cause the value stored in this->result to be modified.
1196 * Make reg constant so that it doesn't get accidentally modified along the
1197 * way. Yes, I actually had this problem. :(
1199 const fs_reg
reg(this, ir
->type
);
1200 fs_reg dst_reg
= reg
;
1202 if (ir
->type
->is_array()) {
1203 const unsigned size
= type_size(ir
->type
->fields
.array
);
1205 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1206 this->result
= reg_undef
;
1207 ir
->array_elements
[i
]->accept(this);
1208 fs_reg src_reg
= this->result
;
1210 dst_reg
.type
= src_reg
.type
;
1211 for (unsigned j
= 0; j
< size
; j
++) {
1212 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1213 src_reg
.reg_offset
++;
1214 dst_reg
.reg_offset
++;
1217 } else if (ir
->type
->is_record()) {
1218 foreach_list(node
, &ir
->components
) {
1219 ir_instruction
*const field
= (ir_instruction
*) node
;
1220 const unsigned size
= type_size(field
->type
);
1222 this->result
= reg_undef
;
1223 field
->accept(this);
1224 fs_reg src_reg
= this->result
;
1226 dst_reg
.type
= src_reg
.type
;
1227 for (unsigned j
= 0; j
< size
; j
++) {
1228 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1229 src_reg
.reg_offset
++;
1230 dst_reg
.reg_offset
++;
1234 const unsigned size
= type_size(ir
->type
);
1236 for (unsigned i
= 0; i
< size
; i
++) {
1237 switch (ir
->type
->base_type
) {
1238 case GLSL_TYPE_FLOAT
:
1239 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1241 case GLSL_TYPE_UINT
:
1242 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1245 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1247 case GLSL_TYPE_BOOL
:
1248 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1251 assert(!"Non-float/uint/int/bool constant");
1253 dst_reg
.reg_offset
++;
1261 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1263 ir_expression
*expr
= ir
->as_expression();
1269 assert(expr
->get_num_operands() <= 2);
1270 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1271 assert(expr
->operands
[i
]->type
->is_scalar());
1273 this->result
= reg_undef
;
1274 expr
->operands
[i
]->accept(this);
1275 op
[i
] = this->result
;
1278 switch (expr
->operation
) {
1279 case ir_unop_logic_not
:
1280 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1281 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1284 case ir_binop_logic_xor
:
1285 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1286 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1289 case ir_binop_logic_or
:
1290 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1291 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1294 case ir_binop_logic_and
:
1295 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1296 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1300 if (intel
->gen
>= 6) {
1301 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1303 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1305 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1309 if (intel
->gen
>= 6) {
1310 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1312 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1314 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1317 case ir_binop_greater
:
1318 case ir_binop_gequal
:
1320 case ir_binop_lequal
:
1321 case ir_binop_equal
:
1322 case ir_binop_all_equal
:
1323 case ir_binop_nequal
:
1324 case ir_binop_any_nequal
:
1325 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1326 inst
->conditional_mod
=
1327 brw_conditional_for_comparison(expr
->operation
);
1331 assert(!"not reached");
1332 fail("bad cond code\n");
1338 this->result
= reg_undef
;
1341 if (intel
->gen
>= 6) {
1342 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1343 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1345 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1346 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1351 * Emit a gen6 IF statement with the comparison folded into the IF
1355 fs_visitor::emit_if_gen6(ir_if
*ir
)
1357 ir_expression
*expr
= ir
->condition
->as_expression();
1364 assert(expr
->get_num_operands() <= 2);
1365 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1366 assert(expr
->operands
[i
]->type
->is_scalar());
1368 this->result
= reg_undef
;
1369 expr
->operands
[i
]->accept(this);
1370 op
[i
] = this->result
;
1373 switch (expr
->operation
) {
1374 case ir_unop_logic_not
:
1375 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1376 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1379 case ir_binop_logic_xor
:
1380 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1381 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1384 case ir_binop_logic_or
:
1385 temp
= fs_reg(this, glsl_type::bool_type
);
1386 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1387 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1388 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1391 case ir_binop_logic_and
:
1392 temp
= fs_reg(this, glsl_type::bool_type
);
1393 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1394 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1395 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1399 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1400 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1404 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1408 case ir_binop_greater
:
1409 case ir_binop_gequal
:
1411 case ir_binop_lequal
:
1412 case ir_binop_equal
:
1413 case ir_binop_all_equal
:
1414 case ir_binop_nequal
:
1415 case ir_binop_any_nequal
:
1416 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1417 inst
->conditional_mod
=
1418 brw_conditional_for_comparison(expr
->operation
);
1421 assert(!"not reached");
1422 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1423 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1424 fail("bad condition\n");
1430 this->result
= reg_undef
;
1431 ir
->condition
->accept(this);
1433 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1434 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1438 fs_visitor::visit(ir_if
*ir
)
1442 if (intel
->gen
!= 6 && c
->dispatch_width
== 16) {
1443 fail("Can't support (non-uniform) control flow on 16-wide\n");
1446 /* Don't point the annotation at the if statement, because then it plus
1447 * the then and else blocks get printed.
1449 this->base_ir
= ir
->condition
;
1451 if (intel
->gen
== 6) {
1454 emit_bool_to_cond_code(ir
->condition
);
1456 inst
= emit(BRW_OPCODE_IF
);
1457 inst
->predicated
= true;
1460 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1461 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1463 this->result
= reg_undef
;
1467 if (!ir
->else_instructions
.is_empty()) {
1468 emit(BRW_OPCODE_ELSE
);
1470 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1471 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1473 this->result
= reg_undef
;
1478 emit(BRW_OPCODE_ENDIF
);
1482 fs_visitor::visit(ir_loop
*ir
)
1484 fs_reg counter
= reg_undef
;
1486 if (c
->dispatch_width
== 16) {
1487 fail("Can't support (non-uniform) control flow on 16-wide\n");
1491 this->base_ir
= ir
->counter
;
1492 ir
->counter
->accept(this);
1493 counter
= *(variable_storage(ir
->counter
));
1496 this->result
= counter
;
1498 this->base_ir
= ir
->from
;
1499 this->result
= counter
;
1500 ir
->from
->accept(this);
1502 if (!this->result
.equals(&counter
))
1503 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1507 emit(BRW_OPCODE_DO
);
1510 this->base_ir
= ir
->to
;
1511 this->result
= reg_undef
;
1512 ir
->to
->accept(this);
1514 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1515 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1517 inst
= emit(BRW_OPCODE_BREAK
);
1518 inst
->predicated
= true;
1521 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1522 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1525 this->result
= reg_undef
;
1529 if (ir
->increment
) {
1530 this->base_ir
= ir
->increment
;
1531 this->result
= reg_undef
;
1532 ir
->increment
->accept(this);
1533 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1536 emit(BRW_OPCODE_WHILE
);
1540 fs_visitor::visit(ir_loop_jump
*ir
)
1543 case ir_loop_jump::jump_break
:
1544 emit(BRW_OPCODE_BREAK
);
1546 case ir_loop_jump::jump_continue
:
1547 emit(BRW_OPCODE_CONTINUE
);
1553 fs_visitor::visit(ir_call
*ir
)
1555 assert(!"FINISHME");
1559 fs_visitor::visit(ir_return
*ir
)
1561 assert(!"FINISHME");
1565 fs_visitor::visit(ir_function
*ir
)
1567 /* Ignore function bodies other than main() -- we shouldn't see calls to
1568 * them since they should all be inlined before we get to ir_to_mesa.
1570 if (strcmp(ir
->name
, "main") == 0) {
1571 const ir_function_signature
*sig
;
1574 sig
= ir
->matching_signature(&empty
);
1578 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1579 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1581 this->result
= reg_undef
;
1588 fs_visitor::visit(ir_function_signature
*ir
)
1590 assert(!"not reached");
1595 fs_visitor::emit(fs_inst inst
)
1597 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1600 if (force_uncompressed_stack
> 0)
1601 list_inst
->force_uncompressed
= true;
1602 else if (force_sechalf_stack
> 0)
1603 list_inst
->force_sechalf
= true;
1605 list_inst
->annotation
= this->current_annotation
;
1606 list_inst
->ir
= this->base_ir
;
1608 this->instructions
.push_tail(list_inst
);
1613 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1615 fs_visitor::emit_dummy_fs()
1617 /* Everyone's favorite color. */
1618 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1619 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1620 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1621 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1624 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1625 write
->base_mrf
= 2;
1628 /* The register location here is relative to the start of the URB
1629 * data. It will get adjusted to be a real location before
1630 * generate_code() time.
1633 fs_visitor::interp_reg(int location
, int channel
)
1635 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1636 int stride
= (channel
& 1) * 4;
1638 assert(urb_setup
[location
] != -1);
1640 return brw_vec1_grf(regnr
, stride
);
1643 /** Emits the interpolation for the varying inputs. */
1645 fs_visitor::emit_interpolation_setup_gen4()
1647 this->current_annotation
= "compute pixel centers";
1648 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1649 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1650 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1651 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1653 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1654 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1656 this->current_annotation
= "compute pixel deltas from v0";
1658 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1659 this->delta_y
= this->delta_x
;
1660 this->delta_y
.reg_offset
++;
1662 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1663 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1665 emit(BRW_OPCODE_ADD
, this->delta_x
,
1666 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1667 emit(BRW_OPCODE_ADD
, this->delta_y
,
1668 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1670 this->current_annotation
= "compute pos.w and 1/pos.w";
1671 /* Compute wpos.w. It's always in our setup, since it's needed to
1672 * interpolate the other attributes.
1674 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1675 emit(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1676 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1677 /* Compute the pixel 1/W value from wpos.w. */
1678 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1679 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1680 this->current_annotation
= NULL
;
1683 /** Emits the interpolation for the varying inputs. */
1685 fs_visitor::emit_interpolation_setup_gen6()
1687 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1689 /* If the pixel centers end up used, the setup is the same as for gen4. */
1690 this->current_annotation
= "compute pixel centers";
1691 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1692 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1693 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1694 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1695 emit(BRW_OPCODE_ADD
,
1697 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1698 fs_reg(brw_imm_v(0x10101010)));
1699 emit(BRW_OPCODE_ADD
,
1701 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1702 fs_reg(brw_imm_v(0x11001100)));
1704 /* As of gen6, we can no longer mix float and int sources. We have
1705 * to turn the integer pixel centers into floats for their actual
1708 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1709 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1710 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1711 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1713 this->current_annotation
= "compute pos.w";
1714 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1715 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1716 emit_math(FS_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1718 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1719 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1721 this->current_annotation
= NULL
;
1725 fs_visitor::emit_color_write(int index
, int first_color_mrf
, fs_reg color
)
1727 int reg_width
= c
->dispatch_width
/ 8;
1729 if (c
->dispatch_width
== 8 || intel
->gen
== 6) {
1730 /* SIMD8 write looks like:
1736 * gen6 SIMD16 DP write looks like:
1746 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
* reg_width
),
1749 /* pre-gen6 SIMD16 single source DP write looks like:
1759 if (brw
->has_compr4
) {
1760 /* By setting the high bit of the MRF register number, we
1761 * indicate that we want COMPR4 mode - instead of doing the
1762 * usual destination + 1 for the second half we get
1765 emit(BRW_OPCODE_MOV
,
1766 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
), color
);
1768 push_force_uncompressed();
1769 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
), color
);
1770 pop_force_uncompressed();
1772 push_force_sechalf();
1773 color
.sechalf
= true;
1774 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4), color
);
1775 pop_force_sechalf();
1776 color
.sechalf
= false;
1782 fs_visitor::emit_fb_writes()
1784 this->current_annotation
= "FB write header";
1785 GLboolean header_present
= GL_TRUE
;
1787 int reg_width
= c
->dispatch_width
/ 8;
1789 if (intel
->gen
>= 6 &&
1790 !this->kill_emitted
&&
1791 c
->key
.nr_color_regions
== 1) {
1792 header_present
= false;
1795 if (header_present
) {
1800 if (c
->aa_dest_stencil_reg
) {
1801 push_force_uncompressed();
1802 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1803 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
1804 pop_force_uncompressed();
1807 /* Reserve space for color. It'll be filled in per MRT below. */
1809 nr
+= 4 * reg_width
;
1811 if (c
->source_depth_to_render_target
) {
1812 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
1813 /* For outputting oDepth on gen6, SIMD8 writes have to be
1814 * used. This would require 8-wide moves of each half to
1815 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1816 * Just bail on doing so for now.
1818 fail("Missing support for simd16 depth writes on gen6\n");
1821 if (c
->computes_depth
) {
1822 /* Hand over gl_FragDepth. */
1823 assert(this->frag_depth
);
1824 fs_reg depth
= *(variable_storage(this->frag_depth
));
1826 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
1828 /* Pass through the payload depth. */
1829 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1830 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
1835 if (c
->dest_depth_reg
) {
1836 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1837 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
1841 fs_reg color
= reg_undef
;
1842 if (this->frag_color
)
1843 color
= *(variable_storage(this->frag_color
));
1844 else if (this->frag_data
) {
1845 color
= *(variable_storage(this->frag_data
));
1846 color
.type
= BRW_REGISTER_TYPE_F
;
1849 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1850 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
1851 "FB write target %d",
1853 if (this->frag_color
|| this->frag_data
) {
1854 for (int i
= 0; i
< 4; i
++) {
1855 emit_color_write(i
, color_mrf
, color
);
1860 if (this->frag_color
)
1861 color
.reg_offset
-= 4;
1863 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1864 inst
->target
= target
;
1867 if (target
== c
->key
.nr_color_regions
- 1)
1869 inst
->header_present
= header_present
;
1872 if (c
->key
.nr_color_regions
== 0) {
1873 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
1874 /* If the alpha test is enabled but there's no color buffer,
1875 * we still need to send alpha out the pipeline to our null
1878 color
.reg_offset
+= 3;
1879 emit_color_write(3, color_mrf
, color
);
1882 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1886 inst
->header_present
= header_present
;
1889 this->current_annotation
= NULL
;