2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "program/prog_parameter.h"
35 #include "program/prog_print.h"
36 #include "program/prog_optimize.h"
37 #include "util/register_allocate.h"
38 #include "program/hash_table.h"
39 #include "brw_context.h"
44 #include "brw_vec4_gs_visitor.h"
46 #include "main/uniforms.h"
47 #include "glsl/nir/glsl_types.h"
48 #include "glsl/ir_optimization.h"
49 #include "program/sampler.h"
54 fs_visitor::emit_vs_system_value(int location
)
56 fs_reg
*reg
= new(this->mem_ctx
)
57 fs_reg(ATTR
, 4 * _mesa_bitcount_64(nir
->info
.inputs_read
),
59 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
62 case SYSTEM_VALUE_BASE_VERTEX
:
64 vs_prog_data
->uses_vertexid
= true;
66 case SYSTEM_VALUE_VERTEX_ID
:
67 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
69 vs_prog_data
->uses_vertexid
= true;
71 case SYSTEM_VALUE_INSTANCE_ID
:
73 vs_prog_data
->uses_instanceid
= true;
76 unreachable("not reached");
82 /* Sample from the MCS surface attached to this multisample texture. */
84 fs_visitor::emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
85 const fs_reg
&texture
)
87 const fs_reg dest
= vgrf(glsl_type::uvec4_type
);
88 const fs_reg srcs
[] = {
89 coordinate
, fs_reg(), fs_reg(), fs_reg(), fs_reg(), fs_reg(),
90 texture
, texture
, fs_reg(), brw_imm_ud(components
), brw_imm_d(0)
92 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_TXF_MCS_LOGICAL
, dest
, srcs
,
95 /* We only care about one or two regs of response, but the sampler always
98 inst
->regs_written
= 4 * dispatch_width
/ 8;
104 fs_visitor::emit_texture(ir_texture_opcode op
,
105 const glsl_type
*dest_type
,
106 fs_reg coordinate
, int coord_components
,
108 fs_reg lod
, fs_reg lod2
, int grad_components
,
112 int gather_component
,
119 fs_inst
*inst
= NULL
;
121 if (op
== ir_query_levels
) {
122 /* textureQueryLevels() is implemented in terms of TXS so we need to
123 * pass a valid LOD argument.
125 assert(lod
.file
== BAD_FILE
);
126 lod
= brw_imm_ud(0u);
129 if (op
== ir_samples_identical
) {
130 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 1, 1));
132 /* If mcs is an immediate value, it means there is no MCS. In that case
135 if (mcs
.file
== BRW_IMMEDIATE_VALUE
) {
136 bld
.MOV(dst
, brw_imm_ud(0u));
137 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
138 fs_reg tmp
= vgrf(glsl_type::uint_type
);
139 bld
.OR(tmp
, mcs
, offset(mcs
, bld
, 1));
140 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
142 bld
.CMP(dst
, mcs
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
149 /* Writemasking doesn't eliminate channels on SIMD8 texture
150 * samples, so don't worry about them.
152 fs_reg dst
= vgrf(glsl_type::get_instance(dest_type
->base_type
, 4, 1));
153 const fs_reg srcs
[] = {
154 coordinate
, shadow_c
, lod
, lod2
,
155 sample_index
, mcs
, surface_reg
, sampler_reg
, offset_value
,
156 brw_imm_d(coord_components
), brw_imm_d(grad_components
)
162 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
165 opcode
= FS_OPCODE_TXB_LOGICAL
;
168 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
171 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
174 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
177 if ((key_tex
->msaa_16
& (1 << sampler
)))
178 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
180 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
183 case ir_query_levels
:
184 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
187 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
190 opcode
= (offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
?
191 SHADER_OPCODE_TG4_OFFSET_LOGICAL
: SHADER_OPCODE_TG4_LOGICAL
);
194 unreachable("Invalid texture opcode.");
197 inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
198 inst
->regs_written
= 4 * dispatch_width
/ 8;
200 if (shadow_c
.file
!= BAD_FILE
)
201 inst
->shadow_compare
= true;
203 if (offset_value
.file
== IMM
)
204 inst
->offset
= offset_value
.ud
;
207 if (gather_component
== 1 &&
208 key_tex
->gather_channel_quirk_mask
& (1 << surface
)) {
209 /* gather4 sampler is broken for green channel on RG32F --
210 * we must ask for blue instead.
212 inst
->offset
|= 2 << 16;
214 inst
->offset
|= gather_component
<< 16;
217 if (devinfo
->gen
== 6)
218 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[surface
], dst
);
221 /* fixup #layers for cube map arrays */
222 if (op
== ir_txs
&& is_cube_array
) {
223 fs_reg depth
= offset(dst
, bld
, 2);
224 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
225 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
227 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
228 int components
= inst
->regs_written
/ (inst
->exec_size
/ 8);
229 for (int i
= 0; i
< components
; i
++) {
231 fixed_payload
[i
] = fixed_depth
;
233 fixed_payload
[i
] = offset(dst
, bld
, i
);
236 bld
.LOAD_PAYLOAD(dst
, fixed_payload
, components
, 0);
239 if (op
== ir_query_levels
) {
240 /* # levels is in .w */
241 dst
= offset(dst
, bld
, 3);
248 * Apply workarounds for Gen6 gather with UINT/SINT
251 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
256 int width
= (wa
& WA_8BIT
) ? 8 : 16;
258 for (int i
= 0; i
< 4; i
++) {
259 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
260 /* Convert from UNORM to UINT */
261 bld
.MUL(dst_f
, dst_f
, brw_imm_f((1 << width
) - 1));
265 /* Reinterpret the UINT value as a signed INT value by
266 * shifting the sign bit into place, then shifting back
269 bld
.SHL(dst
, dst
, brw_imm_d(32 - width
));
270 bld
.ASR(dst
, dst
, brw_imm_d(32 - width
));
273 dst
= offset(dst
, bld
, 1);
277 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
279 fs_visitor::emit_dummy_fs()
281 int reg_width
= dispatch_width
/ 8;
283 /* Everyone's favorite color. */
284 const float color
[4] = { 1.0, 0.0, 1.0, 0.0 };
285 for (int i
= 0; i
< 4; i
++) {
286 bld
.MOV(fs_reg(MRF
, 2 + i
* reg_width
, BRW_REGISTER_TYPE_F
),
287 brw_imm_f(color
[i
]));
291 write
= bld
.emit(FS_OPCODE_FB_WRITE
);
293 if (devinfo
->gen
>= 6) {
295 write
->mlen
= 4 * reg_width
;
297 write
->header_size
= 2;
299 write
->mlen
= 2 + 4 * reg_width
;
302 /* Tell the SF we don't have any inputs. Gen4-5 require at least one
303 * varying to avoid GPU hangs, so set that.
305 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
306 wm_prog_data
->num_varying_inputs
= devinfo
->gen
< 6 ? 1 : 0;
307 memset(wm_prog_data
->urb_setup
, -1,
308 sizeof(wm_prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
310 /* We don't have any uniforms. */
311 stage_prog_data
->nr_params
= 0;
312 stage_prog_data
->nr_pull_params
= 0;
313 stage_prog_data
->curb_read_length
= 0;
314 stage_prog_data
->dispatch_grf_start_reg
= 2;
315 wm_prog_data
->dispatch_grf_start_reg_16
= 2;
316 grf_used
= 1; /* Gen4-5 don't allow zero GRF blocks */
321 /* The register location here is relative to the start of the URB
322 * data. It will get adjusted to be a real location before
323 * generate_code() time.
326 fs_visitor::interp_reg(int location
, int channel
)
328 assert(stage
== MESA_SHADER_FRAGMENT
);
329 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
330 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
331 int stride
= (channel
& 1) * 4;
333 assert(prog_data
->urb_setup
[location
] != -1);
335 return brw_vec1_grf(regnr
, stride
);
338 /** Emits the interpolation for the varying inputs. */
340 fs_visitor::emit_interpolation_setup_gen4()
342 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
344 fs_builder abld
= bld
.annotate("compute pixel centers");
345 this->pixel_x
= vgrf(glsl_type::uint_type
);
346 this->pixel_y
= vgrf(glsl_type::uint_type
);
347 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
348 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
349 abld
.ADD(this->pixel_x
,
350 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
351 fs_reg(brw_imm_v(0x10101010)));
352 abld
.ADD(this->pixel_y
,
353 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
354 fs_reg(brw_imm_v(0x11001100)));
356 abld
= bld
.annotate("compute pixel deltas from v0");
358 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
359 vgrf(glsl_type::vec2_type
);
360 const fs_reg
&delta_xy
= this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
361 const fs_reg
xstart(negate(brw_vec1_grf(1, 0)));
362 const fs_reg
ystart(negate(brw_vec1_grf(1, 1)));
364 if (devinfo
->has_pln
&& dispatch_width
== 16) {
365 for (unsigned i
= 0; i
< 2; i
++) {
366 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 0),
367 half(this->pixel_x
, i
), xstart
);
368 abld
.half(i
).ADD(half(offset(delta_xy
, abld
, i
), 1),
369 half(this->pixel_y
, i
), ystart
);
372 abld
.ADD(offset(delta_xy
, abld
, 0), this->pixel_x
, xstart
);
373 abld
.ADD(offset(delta_xy
, abld
, 1), this->pixel_y
, ystart
);
376 abld
= bld
.annotate("compute pos.w and 1/pos.w");
377 /* Compute wpos.w. It's always in our setup, since it's needed to
378 * interpolate the other attributes.
380 this->wpos_w
= vgrf(glsl_type::float_type
);
381 abld
.emit(FS_OPCODE_LINTERP
, wpos_w
, delta_xy
,
382 interp_reg(VARYING_SLOT_POS
, 3));
383 /* Compute the pixel 1/W value from wpos.w. */
384 this->pixel_w
= vgrf(glsl_type::float_type
);
385 abld
.emit(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
388 /** Emits the interpolation for the varying inputs. */
390 fs_visitor::emit_interpolation_setup_gen6()
392 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
394 fs_builder abld
= bld
.annotate("compute pixel centers");
395 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
396 /* The "Register Region Restrictions" page says for BDW (and newer,
399 * "When destination spans two registers, the source may be one or
400 * two registers. The destination elements must be evenly split
401 * between the two registers."
403 * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
404 * compute our pixel centers.
406 fs_reg
int_pixel_xy(VGRF
, alloc
.allocate(dispatch_width
/ 8),
407 BRW_REGISTER_TYPE_UW
);
409 const fs_builder dbld
= abld
.exec_all().group(dispatch_width
* 2, 0);
410 dbld
.ADD(int_pixel_xy
,
411 fs_reg(stride(suboffset(g1_uw
, 4), 1, 4, 0)),
412 fs_reg(brw_imm_v(0x11001010)));
414 this->pixel_x
= vgrf(glsl_type::float_type
);
415 this->pixel_y
= vgrf(glsl_type::float_type
);
416 abld
.emit(FS_OPCODE_PIXEL_X
, this->pixel_x
, int_pixel_xy
);
417 abld
.emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
, int_pixel_xy
);
419 /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
421 * "When destination spans two registers, the source MUST span two
424 * Since the GRF source of the ADD will only read a single register, we
425 * must do two separate ADDs in SIMD16.
427 fs_reg int_pixel_x
= vgrf(glsl_type::uint_type
);
428 fs_reg int_pixel_y
= vgrf(glsl_type::uint_type
);
429 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
430 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
431 abld
.ADD(int_pixel_x
,
432 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
433 fs_reg(brw_imm_v(0x10101010)));
434 abld
.ADD(int_pixel_y
,
435 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
436 fs_reg(brw_imm_v(0x11001100)));
438 /* As of gen6, we can no longer mix float and int sources. We have
439 * to turn the integer pixel centers into floats for their actual
442 this->pixel_x
= vgrf(glsl_type::float_type
);
443 this->pixel_y
= vgrf(glsl_type::float_type
);
444 abld
.MOV(this->pixel_x
, int_pixel_x
);
445 abld
.MOV(this->pixel_y
, int_pixel_y
);
448 abld
= bld
.annotate("compute pos.w");
449 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
450 this->wpos_w
= vgrf(glsl_type::float_type
);
451 abld
.emit(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
453 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
454 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
455 this->delta_xy
[i
] = fs_reg(brw_vec16_grf(reg
, 0));
459 static enum brw_conditional_mod
460 cond_for_alpha_func(GLenum func
)
464 return BRW_CONDITIONAL_G
;
466 return BRW_CONDITIONAL_GE
;
468 return BRW_CONDITIONAL_L
;
470 return BRW_CONDITIONAL_LE
;
472 return BRW_CONDITIONAL_EQ
;
474 return BRW_CONDITIONAL_NEQ
;
476 unreachable("Not reached");
481 * Alpha test support for when we compile it into the shader instead
482 * of using the normal fixed-function alpha test.
485 fs_visitor::emit_alpha_test()
487 assert(stage
== MESA_SHADER_FRAGMENT
);
488 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
489 const fs_builder abld
= bld
.annotate("Alpha test");
492 if (key
->alpha_test_func
== GL_ALWAYS
)
495 if (key
->alpha_test_func
== GL_NEVER
) {
497 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
498 BRW_REGISTER_TYPE_UW
));
499 cmp
= abld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
,
500 BRW_CONDITIONAL_NEQ
);
503 fs_reg color
= offset(outputs
[0], bld
, 3);
505 /* f0.1 &= func(color, ref) */
506 cmp
= abld
.CMP(bld
.null_reg_f(), color
, brw_imm_f(key
->alpha_test_ref
),
507 cond_for_alpha_func(key
->alpha_test_func
));
509 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
510 cmp
->flag_subreg
= 1;
514 fs_visitor::emit_single_fb_write(const fs_builder
&bld
,
515 fs_reg color0
, fs_reg color1
,
516 fs_reg src0_alpha
, unsigned components
)
518 assert(stage
== MESA_SHADER_FRAGMENT
);
519 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
521 /* Hand over gl_FragDepth or the payload depth. */
522 const fs_reg dst_depth
= (payload
.dest_depth_reg
?
523 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0)) :
525 fs_reg src_depth
, src_stencil
;
527 if (source_depth_to_render_target
) {
528 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
529 src_depth
= frag_depth
;
531 src_depth
= fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0));
534 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
))
535 src_stencil
= frag_stencil
;
537 const fs_reg sources
[] = {
538 color0
, color1
, src0_alpha
, src_depth
, dst_depth
, src_stencil
,
539 sample_mask
, brw_imm_ud(components
)
541 assert(ARRAY_SIZE(sources
) - 1 == FB_WRITE_LOGICAL_SRC_COMPONENTS
);
542 fs_inst
*write
= bld
.emit(FS_OPCODE_FB_WRITE_LOGICAL
, fs_reg(),
543 sources
, ARRAY_SIZE(sources
));
545 if (prog_data
->uses_kill
) {
546 write
->predicate
= BRW_PREDICATE_NORMAL
;
547 write
->flag_subreg
= 1;
554 fs_visitor::emit_fb_writes()
556 assert(stage
== MESA_SHADER_FRAGMENT
);
557 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
558 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
560 fs_inst
*inst
= NULL
;
562 if (source_depth_to_render_target
&& devinfo
->gen
== 6) {
563 /* For outputting oDepth on gen6, SIMD8 writes have to be used. This
564 * would require SIMD8 moves of each half to message regs, e.g. by using
565 * the SIMD lowering pass. Unfortunately this is more difficult than it
566 * sounds because the SIMD8 single-source message lacks channel selects
567 * for the second and third subspans.
569 no16("Missing support for simd16 depth writes on gen6\n");
572 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
)) {
573 /* From the 'Render Target Write message' section of the docs:
574 * "Output Stencil is not supported with SIMD16 Render Target Write
577 * FINISHME: split 16 into 2 8s
579 no16("FINISHME: support 2 simd8 writes for gl_FragStencilRefARB\n");
583 const fs_builder abld
= bld
.annotate("FB dual-source write");
585 inst
= emit_single_fb_write(abld
, this->outputs
[0],
586 this->dual_src_output
, reg_undef
, 4);
589 prog_data
->dual_src_blend
= true;
591 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
592 /* Skip over outputs that weren't written. */
593 if (this->outputs
[target
].file
== BAD_FILE
)
596 const fs_builder abld
= bld
.annotate(
597 ralloc_asprintf(this->mem_ctx
, "FB write target %d", target
));
600 if (devinfo
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
601 src0_alpha
= offset(outputs
[0], bld
, 3);
603 inst
= emit_single_fb_write(abld
, this->outputs
[target
], reg_undef
,
605 this->output_components
[target
]);
606 inst
->target
= target
;
611 /* Even if there's no color buffers enabled, we still need to send
612 * alpha out the pipeline to our null renderbuffer to support
613 * alpha-testing, alpha-to-coverage, and so on.
615 /* FINISHME: Factor out this frequently recurring pattern into a
618 const fs_reg srcs
[] = { reg_undef
, reg_undef
,
619 reg_undef
, offset(this->outputs
[0], bld
, 3) };
620 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
621 bld
.LOAD_PAYLOAD(tmp
, srcs
, 4, 0);
623 inst
= emit_single_fb_write(bld
, tmp
, reg_undef
, reg_undef
, 4);
631 fs_visitor::setup_uniform_clipplane_values(gl_clip_plane
*clip_planes
)
633 const struct brw_vs_prog_key
*key
=
634 (const struct brw_vs_prog_key
*) this->key
;
636 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
637 this->userplane
[i
] = fs_reg(UNIFORM
, uniforms
);
638 for (int j
= 0; j
< 4; ++j
) {
639 stage_prog_data
->param
[uniforms
+ j
] =
640 (gl_constant_value
*) &clip_planes
[i
][j
];
647 * Lower legacy fixed-function and gl_ClipVertex clipping to clip distances.
649 * This does nothing if the shader uses gl_ClipDistance or user clipping is
650 * disabled altogether.
652 void fs_visitor::compute_clip_distance(gl_clip_plane
*clip_planes
)
654 struct brw_vue_prog_data
*vue_prog_data
=
655 (struct brw_vue_prog_data
*) prog_data
;
656 const struct brw_vs_prog_key
*key
=
657 (const struct brw_vs_prog_key
*) this->key
;
659 /* Bail unless some sort of legacy clipping is enabled */
660 if (key
->nr_userclip_plane_consts
== 0)
663 /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
665 * "If a linked set of shaders forming the vertex stage contains no
666 * static write to gl_ClipVertex or gl_ClipDistance, but the
667 * application has requested clipping against user clip planes through
668 * the API, then the coordinate written to gl_Position is used for
669 * comparison against the user clip planes."
671 * This function is only called if the shader didn't write to
672 * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
673 * if the user wrote to it; otherwise we use gl_Position.
676 gl_varying_slot clip_vertex
= VARYING_SLOT_CLIP_VERTEX
;
677 if (!(vue_prog_data
->vue_map
.slots_valid
& VARYING_BIT_CLIP_VERTEX
))
678 clip_vertex
= VARYING_SLOT_POS
;
680 /* If the clip vertex isn't written, skip this. Typically this means
681 * the GS will set up clipping. */
682 if (outputs
[clip_vertex
].file
== BAD_FILE
)
685 setup_uniform_clipplane_values(clip_planes
);
687 const fs_builder abld
= bld
.annotate("user clip distances");
689 this->outputs
[VARYING_SLOT_CLIP_DIST0
] = vgrf(glsl_type::vec4_type
);
690 this->output_components
[VARYING_SLOT_CLIP_DIST0
] = 4;
691 this->outputs
[VARYING_SLOT_CLIP_DIST1
] = vgrf(glsl_type::vec4_type
);
692 this->output_components
[VARYING_SLOT_CLIP_DIST1
] = 4;
694 for (int i
= 0; i
< key
->nr_userclip_plane_consts
; i
++) {
695 fs_reg u
= userplane
[i
];
696 fs_reg output
= outputs
[VARYING_SLOT_CLIP_DIST0
+ i
/ 4];
697 output
.reg_offset
= i
& 3;
699 abld
.MUL(output
, outputs
[clip_vertex
], u
);
700 for (int j
= 1; j
< 4; j
++) {
701 u
.nr
= userplane
[i
].nr
+ j
;
702 abld
.MAD(output
, output
, offset(outputs
[clip_vertex
], bld
, j
), u
);
708 fs_visitor::emit_urb_writes(const fs_reg
&gs_vertex_count
)
710 int slot
, urb_offset
, length
;
711 int starting_urb_offset
= 0;
712 const struct brw_vue_prog_data
*vue_prog_data
=
713 (const struct brw_vue_prog_data
*) this->prog_data
;
714 const struct brw_vs_prog_key
*vs_key
=
715 (const struct brw_vs_prog_key
*) this->key
;
716 const GLbitfield64 psiz_mask
=
717 VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
| VARYING_BIT_PSIZ
;
718 const struct brw_vue_map
*vue_map
= &vue_prog_data
->vue_map
;
722 /* If we don't have any valid slots to write, just do a minimal urb write
723 * send to terminate the shader. This includes 1 slot of undefined data,
724 * because it's invalid to write 0 data:
726 * From the Broadwell PRM, Volume 7: 3D Media GPGPU, Shared Functions -
727 * Unified Return Buffer (URB) > URB_SIMD8_Write and URB_SIMD8_Read >
728 * Write Data Payload:
730 * "The write data payload can be between 1 and 8 message phases long."
732 if (vue_map
->slots_valid
== 0) {
733 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(2), BRW_REGISTER_TYPE_UD
);
734 bld
.exec_all().MOV(payload
, fs_reg(retype(brw_vec8_grf(1, 0),
735 BRW_REGISTER_TYPE_UD
)));
737 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
744 opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
746 fs_reg per_slot_offsets
;
748 if (stage
== MESA_SHADER_GEOMETRY
) {
749 const struct brw_gs_prog_data
*gs_prog_data
=
750 (const struct brw_gs_prog_data
*) this->prog_data
;
752 /* We need to increment the Global Offset to skip over the control data
753 * header and the extra "Vertex Count" field (1 HWord) at the beginning
754 * of the VUE. We're counting in OWords, so the units are doubled.
756 starting_urb_offset
= 2 * gs_prog_data
->control_data_header_size_hwords
;
757 if (gs_prog_data
->static_vertex_count
== -1)
758 starting_urb_offset
+= 2;
760 /* We also need to use per-slot offsets. The per-slot offset is the
761 * Vertex Count. SIMD8 mode processes 8 different primitives at a
762 * time; each may output a different number of vertices.
764 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
;
767 /* The URB offset is in 128-bit units, so we need to multiply by 2 */
768 const int output_vertex_size_owords
=
769 gs_prog_data
->output_vertex_size_hwords
* 2;
772 if (gs_vertex_count
.file
== IMM
) {
773 per_slot_offsets
= brw_imm_ud(output_vertex_size_owords
*
776 per_slot_offsets
= vgrf(glsl_type::int_type
);
777 bld
.MUL(per_slot_offsets
, gs_vertex_count
,
778 brw_imm_ud(output_vertex_size_owords
));
783 urb_offset
= starting_urb_offset
;
785 for (slot
= 0; slot
< vue_map
->num_slots
; slot
++) {
786 int varying
= vue_map
->slot_to_varying
[slot
];
788 case VARYING_SLOT_PSIZ
: {
789 /* The point size varying slot is the vue header and is always in the
790 * vue map. But often none of the special varyings that live there
791 * are written and in that case we can skip writing to the vue
792 * header, provided the corresponding state properly clamps the
793 * values further down the pipeline. */
794 if ((vue_map
->slots_valid
& psiz_mask
) == 0) {
800 fs_reg
zero(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
801 bld
.MOV(zero
, brw_imm_ud(0u));
803 sources
[length
++] = zero
;
804 if (vue_map
->slots_valid
& VARYING_BIT_LAYER
)
805 sources
[length
++] = this->outputs
[VARYING_SLOT_LAYER
];
807 sources
[length
++] = zero
;
809 if (vue_map
->slots_valid
& VARYING_BIT_VIEWPORT
)
810 sources
[length
++] = this->outputs
[VARYING_SLOT_VIEWPORT
];
812 sources
[length
++] = zero
;
814 if (vue_map
->slots_valid
& VARYING_BIT_PSIZ
)
815 sources
[length
++] = this->outputs
[VARYING_SLOT_PSIZ
];
817 sources
[length
++] = zero
;
820 case BRW_VARYING_SLOT_NDC
:
821 case VARYING_SLOT_EDGE
:
822 unreachable("unexpected scalar vs output");
826 /* gl_Position is always in the vue map, but isn't always written by
827 * the shader. Other varyings (clip distances) get added to the vue
828 * map but don't always get written. In those cases, the
829 * corresponding this->output[] slot will be invalid we and can skip
830 * the urb write for the varying. If we've already queued up a vue
831 * slot for writing we flush a mlen 5 urb write, otherwise we just
832 * advance the urb_offset.
834 if (varying
== BRW_VARYING_SLOT_PAD
||
835 this->outputs
[varying
].file
== BAD_FILE
) {
843 if (stage
== MESA_SHADER_VERTEX
&& vs_key
->clamp_vertex_color
&&
844 (varying
== VARYING_SLOT_COL0
||
845 varying
== VARYING_SLOT_COL1
||
846 varying
== VARYING_SLOT_BFC0
||
847 varying
== VARYING_SLOT_BFC1
)) {
848 /* We need to clamp these guys, so do a saturating MOV into a
849 * temp register and use that for the payload.
851 for (int i
= 0; i
< 4; i
++) {
852 fs_reg reg
= fs_reg(VGRF
, alloc
.allocate(1), outputs
[varying
].type
);
853 fs_reg src
= offset(this->outputs
[varying
], bld
, i
);
854 set_saturate(true, bld
.MOV(reg
, src
));
855 sources
[length
++] = reg
;
858 for (unsigned i
= 0; i
< output_components
[varying
]; i
++)
859 sources
[length
++] = offset(this->outputs
[varying
], bld
, i
);
860 for (unsigned i
= output_components
[varying
]; i
< 4; i
++)
861 sources
[length
++] = brw_imm_d(0);
866 const fs_builder abld
= bld
.annotate("URB write");
868 /* If we've queued up 8 registers of payload (2 VUE slots), if this is
869 * the last slot or if we need to flush (see BAD_FILE varying case
870 * above), emit a URB write send now to flush out the data.
872 int last
= slot
== vue_map
->num_slots
- 1;
873 if (length
== 8 || last
)
876 fs_reg
*payload_sources
=
877 ralloc_array(mem_ctx
, fs_reg
, length
+ header_size
);
878 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(length
+ header_size
),
879 BRW_REGISTER_TYPE_F
);
881 fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
883 if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
)
884 payload_sources
[1] = per_slot_offsets
;
886 memcpy(&payload_sources
[header_size
], sources
,
887 length
* sizeof sources
[0]);
889 abld
.LOAD_PAYLOAD(payload
, payload_sources
, length
+ header_size
,
892 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
893 inst
->eot
= last
&& stage
== MESA_SHADER_VERTEX
;
894 inst
->mlen
= length
+ header_size
;
895 inst
->offset
= urb_offset
;
896 urb_offset
= starting_urb_offset
+ slot
+ 1;
904 fs_visitor::emit_cs_terminate()
906 assert(devinfo
->gen
>= 7);
908 /* We are getting the thread ID from the compute shader header */
909 assert(stage
== MESA_SHADER_COMPUTE
);
911 /* We can't directly send from g0, since sends with EOT have to use
912 * g112-127. So, copy it to a virtual register, The register allocator will
913 * make sure it uses the appropriate register range.
915 struct brw_reg g0
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
);
916 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
917 bld
.group(8, 0).exec_all().MOV(payload
, g0
);
919 /* Send a message to the thread spawner to terminate the thread. */
920 fs_inst
*inst
= bld
.exec_all()
921 .emit(CS_OPCODE_CS_TERMINATE
, reg_undef
, payload
);
926 fs_visitor::emit_barrier()
928 assert(devinfo
->gen
>= 7);
930 /* We are getting the barrier ID from the compute shader header */
931 assert(stage
== MESA_SHADER_COMPUTE
);
933 fs_reg payload
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
935 const fs_builder pbld
= bld
.exec_all().group(8, 0);
937 /* Clear the message payload */
938 pbld
.MOV(payload
, brw_imm_ud(0u));
940 /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
941 fs_reg r0_2
= fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
));
942 pbld
.AND(component(payload
, 2), r0_2
, brw_imm_ud(0x0f000000u
));
944 /* Emit a gateway "barrier" message using the payload we set up, followed
945 * by a wait instruction.
947 bld
.exec_all().emit(SHADER_OPCODE_BARRIER
, reg_undef
, payload
);
950 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
953 struct brw_stage_prog_data
*prog_data
,
954 struct gl_program
*prog
,
955 const nir_shader
*shader
,
956 unsigned dispatch_width
,
957 int shader_time_index
)
958 : backend_shader(compiler
, log_data
, mem_ctx
, shader
, prog_data
),
959 key(key
), gs_compile(NULL
), prog_data(prog_data
), prog(prog
),
960 dispatch_width(dispatch_width
),
961 shader_time_index(shader_time_index
),
962 bld(fs_builder(this, dispatch_width
).at_end())
967 fs_visitor::fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
969 struct brw_gs_compile
*c
,
970 struct brw_gs_prog_data
*prog_data
,
971 const nir_shader
*shader
,
972 int shader_time_index
)
973 : backend_shader(compiler
, log_data
, mem_ctx
, shader
,
974 &prog_data
->base
.base
),
975 key(&c
->key
), gs_compile(c
),
976 prog_data(&prog_data
->base
.base
), prog(NULL
),
978 shader_time_index(shader_time_index
),
979 bld(fs_builder(this, dispatch_width
).at_end())
989 case MESA_SHADER_FRAGMENT
:
990 key_tex
= &((const brw_wm_prog_key
*) key
)->tex
;
992 case MESA_SHADER_VERTEX
:
993 key_tex
= &((const brw_vs_prog_key
*) key
)->tex
;
995 case MESA_SHADER_GEOMETRY
:
996 key_tex
= &((const brw_gs_prog_key
*) key
)->tex
;
998 case MESA_SHADER_COMPUTE
:
999 key_tex
= &((const brw_cs_prog_key
*) key
)->tex
;
1002 unreachable("unhandled shader stage");
1005 this->prog_data
= this->stage_prog_data
;
1007 this->failed
= false;
1008 this->simd16_unsupported
= false;
1009 this->no16_msg
= NULL
;
1011 this->nir_locals
= NULL
;
1012 this->nir_ssa_values
= NULL
;
1014 memset(&this->payload
, 0, sizeof(this->payload
));
1015 memset(this->output_components
, 0, sizeof(this->output_components
));
1016 this->source_depth_to_render_target
= false;
1017 this->runtime_check_aads_emit
= false;
1018 this->first_non_payload_grf
= 0;
1019 this->max_grf
= devinfo
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
1021 this->virtual_grf_start
= NULL
;
1022 this->virtual_grf_end
= NULL
;
1023 this->live_intervals
= NULL
;
1024 this->regs_live_at_ip
= NULL
;
1027 this->last_scratch
= 0;
1028 this->pull_constant_loc
= NULL
;
1029 this->push_constant_loc
= NULL
;
1031 this->promoted_constants
= 0,
1033 this->spilled_any_registers
= false;
1034 this->do_dual_src
= false;
1036 if (dispatch_width
== 8)
1037 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
1040 fs_visitor::~fs_visitor()