3 * Copyright © 2011-2015 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
34 class src_reg
: public backend_reg
37 DECLARE_RALLOC_CXX_OPERATORS(src_reg
)
41 src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
);
43 src_reg(struct ::brw_reg reg
);
45 bool equals(const src_reg
&r
) const;
47 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
48 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
, int size
);
50 explicit src_reg(const dst_reg
®
);
56 retype(src_reg reg
, enum brw_reg_type type
)
65 add_byte_offset(backend_reg
*reg
, unsigned bytes
)
74 assert(reg
->offset
% 16 == 0);
77 const unsigned suboffset
= reg
->offset
+ bytes
;
78 reg
->nr
+= suboffset
/ REG_SIZE
;
79 reg
->offset
= suboffset
% REG_SIZE
;
80 assert(reg
->offset
% 16 == 0);
85 const unsigned suboffset
= reg
->subnr
+ bytes
;
86 reg
->nr
+= suboffset
/ REG_SIZE
;
87 reg
->subnr
= suboffset
% REG_SIZE
;
88 assert(reg
->subnr
% 16 == 0);
96 } /* namepace detail */
99 byte_offset(src_reg reg
, unsigned bytes
)
101 detail::add_byte_offset(®
, bytes
);
105 static inline src_reg
106 offset(src_reg reg
, unsigned width
, unsigned delta
)
108 const unsigned stride
= (reg
.file
== UNIFORM
? 0 : 4);
109 const unsigned num_components
= MAX2(width
/ 4 * stride
, 4);
110 return byte_offset(reg
, num_components
* type_sz(reg
.type
) * delta
);
113 static inline src_reg
114 horiz_offset(src_reg reg
, unsigned delta
)
116 return byte_offset(reg
, delta
* type_sz(reg
.type
));
120 * Reswizzle a given source register.
123 static inline src_reg
124 swizzle(src_reg reg
, unsigned swizzle
)
127 reg
.ud
= brw_swizzle_immediate(reg
.type
, reg
.ud
, swizzle
);
129 reg
.swizzle
= brw_compose_swizzle(swizzle
, reg
.swizzle
);
134 static inline src_reg
137 assert(reg
.file
!= IMM
);
138 reg
.negate
= !reg
.negate
;
143 is_uniform(const src_reg
®
)
145 return (reg
.file
== IMM
|| reg
.file
== UNIFORM
|| reg
.is_null()) &&
146 (!reg
.reladdr
|| is_uniform(*reg
.reladdr
));
149 class dst_reg
: public backend_reg
152 DECLARE_RALLOC_CXX_OPERATORS(dst_reg
)
157 dst_reg(enum brw_reg_file file
, int nr
);
158 dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
160 dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
162 dst_reg(struct ::brw_reg reg
);
163 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
165 explicit dst_reg(const src_reg
®
);
167 bool equals(const dst_reg
&r
) const;
172 static inline dst_reg
173 retype(dst_reg reg
, enum brw_reg_type type
)
179 static inline dst_reg
180 byte_offset(dst_reg reg
, unsigned bytes
)
182 detail::add_byte_offset(®
, bytes
);
186 static inline dst_reg
187 offset(dst_reg reg
, unsigned width
, unsigned delta
)
189 const unsigned stride
= (reg
.file
== UNIFORM
? 0 : 4);
190 const unsigned num_components
= MAX2(width
/ 4 * stride
, 4);
191 return byte_offset(reg
, num_components
* type_sz(reg
.type
) * delta
);
194 static inline dst_reg
195 horiz_offset(dst_reg reg
, unsigned delta
)
197 return byte_offset(reg
, delta
* type_sz(reg
.type
));
200 static inline dst_reg
201 writemask(dst_reg reg
, unsigned mask
)
203 assert(reg
.file
!= IMM
);
204 assert((reg
.writemask
& mask
) != 0);
205 reg
.writemask
&= mask
;
210 * Return an integer identifying the discrete address space a register is
211 * contained in. A register is by definition fully contained in the single
212 * reg_space it belongs to, so two registers with different reg_space ids are
213 * guaranteed not to overlap. Most register files are a single reg_space of
214 * its own, only the VGRF file is composed of multiple discrete address
215 * spaces, one for each VGRF allocation.
217 static inline uint32_t
218 reg_space(const backend_reg
&r
)
220 return r
.file
<< 16 | (r
.file
== VGRF
? r
.nr
: 0);
224 * Return the base offset in bytes of a register relative to the start of its
227 static inline unsigned
228 reg_offset(const backend_reg
&r
)
230 return (r
.file
== VGRF
|| r
.file
== IMM
? 0 : r
.nr
) *
231 (r
.file
== UNIFORM
? 16 : REG_SIZE
) + r
.offset
+
232 (r
.file
== ARF
|| r
.file
== FIXED_GRF
? r
.subnr
: 0);
236 * Return whether the register region starting at \p r and spanning \p dr
237 * bytes could potentially overlap the register region starting at \p s and
238 * spanning \p ds bytes.
241 regions_overlap(const backend_reg
&r
, unsigned dr
,
242 const backend_reg
&s
, unsigned ds
)
244 if (r
.file
== MRF
&& (r
.nr
& BRW_MRF_COMPR4
)) {
245 /* COMPR4 regions are translated by the hardware during decompression
246 * into two separate half-regions 4 MRFs apart from each other.
249 t0
.nr
&= ~BRW_MRF_COMPR4
;
251 t1
.offset
+= 4 * REG_SIZE
;
252 return regions_overlap(t0
, dr
/ 2, s
, ds
) ||
253 regions_overlap(t1
, dr
/ 2, s
, ds
);
255 } else if (s
.file
== MRF
&& (s
.nr
& BRW_MRF_COMPR4
)) {
256 return regions_overlap(s
, ds
, r
, dr
);
259 return reg_space(r
) == reg_space(s
) &&
260 !(reg_offset(r
) + dr
<= reg_offset(s
) ||
261 reg_offset(s
) + ds
<= reg_offset(r
));
265 class vec4_instruction
: public backend_instruction
{
267 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction
)
269 vec4_instruction(enum opcode opcode
,
270 const dst_reg
&dst
= dst_reg(),
271 const src_reg
&src0
= src_reg(),
272 const src_reg
&src1
= src_reg(),
273 const src_reg
&src2
= src_reg());
278 enum brw_urb_write_flags urb_write_flags
;
280 unsigned sol_binding
; /**< gen6: SOL binding table index */
281 bool sol_final_write
; /**< gen6: send commit message */
282 unsigned sol_vertex
; /**< gen6: used for setting dst index in SVB header */
284 bool is_send_from_grf();
285 unsigned size_read(unsigned arg
) const;
286 bool can_reswizzle(const struct gen_device_info
*devinfo
, int dst_writemask
,
287 int swizzle
, int swizzle_mask
);
288 void reswizzle(int dst_writemask
, int swizzle
);
289 bool can_do_source_mods(const struct gen_device_info
*devinfo
);
290 bool can_do_writemask(const struct gen_device_info
*devinfo
);
291 bool can_change_types() const;
292 bool has_source_and_destination_hazard() const;
294 bool is_align1_partial_write()
296 return opcode
== VEC4_OPCODE_SET_LOW_32BIT
||
297 opcode
== VEC4_OPCODE_SET_HIGH_32BIT
;
302 return predicate
|| opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
;
305 bool reads_flag(unsigned c
)
307 if (opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
)
311 case BRW_PREDICATE_NONE
:
313 case BRW_PREDICATE_ALIGN16_REPLICATE_X
:
315 case BRW_PREDICATE_ALIGN16_REPLICATE_Y
:
317 case BRW_PREDICATE_ALIGN16_REPLICATE_Z
:
319 case BRW_PREDICATE_ALIGN16_REPLICATE_W
:
328 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
329 opcode
!= BRW_OPCODE_IF
&&
330 opcode
!= BRW_OPCODE_WHILE
));
335 * Make the execution of \p inst dependent on the evaluation of a possibly
336 * inverted predicate.
338 inline vec4_instruction
*
339 set_predicate_inv(enum brw_predicate pred
, bool inverse
,
340 vec4_instruction
*inst
)
342 inst
->predicate
= pred
;
343 inst
->predicate_inverse
= inverse
;
348 * Make the execution of \p inst dependent on the evaluation of a predicate.
350 inline vec4_instruction
*
351 set_predicate(enum brw_predicate pred
, vec4_instruction
*inst
)
353 return set_predicate_inv(pred
, false, inst
);
357 * Write the result of evaluating the condition given by \p mod to a flag
360 inline vec4_instruction
*
361 set_condmod(enum brw_conditional_mod mod
, vec4_instruction
*inst
)
363 inst
->conditional_mod
= mod
;
368 * Clamp the result of \p inst to the saturation range of its destination
371 inline vec4_instruction
*
372 set_saturate(bool saturate
, vec4_instruction
*inst
)
374 inst
->saturate
= saturate
;
379 * Return the number of dataflow registers written by the instruction (either
380 * fully or partially) counted from 'floor(reg_offset(inst->dst) /
381 * register_size)'. The somewhat arbitrary register size unit is 16B for the
382 * UNIFORM and IMM files and 32B for all other files.
385 regs_written(const vec4_instruction
*inst
)
387 assert(inst
->dst
.file
!= UNIFORM
&& inst
->dst
.file
!= IMM
);
388 return DIV_ROUND_UP(reg_offset(inst
->dst
) % REG_SIZE
+ inst
->size_written
,
393 * Return the number of dataflow registers read by the instruction (either
394 * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
395 * register_size)'. The somewhat arbitrary register size unit is 16B for the
396 * UNIFORM and IMM files and 32B for all other files.
399 regs_read(const vec4_instruction
*inst
, unsigned i
)
401 const unsigned reg_size
=
402 inst
->src
[i
].file
== UNIFORM
|| inst
->src
[i
].file
== IMM
? 16 : REG_SIZE
;
403 return DIV_ROUND_UP(reg_offset(inst
->src
[i
]) % reg_size
+ inst
->size_read(i
),
407 } /* namespace brw */