src/mesa/drivers/dri/i965/brw_link.cpp

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_nir.h"
  26 #include "brw_program.h"
  27 #include "compiler/glsl/ir.h"
  28 #include "compiler/glsl/ir_optimization.h"
  29 #include "compiler/glsl/program.h"
  30 #include "program/program.h"
  31 #include "main/shaderapi.h"
  32 #include "main/shaderobj.h"
  33 #include "main/uniforms.h"
  34
  35 /**
  36  * Performs a compile of the shader stages even when we don't know
  37  * what non-orthogonal state will be set, in the hope that it reflects
  38  * the eventual NOS used, and thus allows us to produce link failures.
  39  */
  40 static bool
  41 brw_shader_precompile(struct gl_context *ctx,
  42                       struct gl_shader_program *sh_prog)
  43 {
  44    struct gl_linked_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  45    struct gl_linked_shader *tcs = sh_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL];
  46    struct gl_linked_shader *tes = sh_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
  47    struct gl_linked_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  48    struct gl_linked_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  49    struct gl_linked_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
  50
  51    if (fs && !brw_fs_precompile(ctx, fs->Program))
  52       return false;
  53
  54    if (gs && !brw_gs_precompile(ctx, gs->Program))
  55       return false;
  56
  57    if (tes && !brw_tes_precompile(ctx, sh_prog, tes->Program))
  58       return false;
  59
  60    if (tcs && !brw_tcs_precompile(ctx, sh_prog, tcs->Program))
  61       return false;
  62
  63    if (vs && !brw_vs_precompile(ctx, vs->Program))
  64       return false;
  65
  66    if (cs && !brw_cs_precompile(ctx, cs->Program))
  67       return false;
  68
  69    return true;
  70 }
  71
  72 static void
  73 brw_lower_packing_builtins(struct brw_context *brw,
  74                            exec_list *ir)
  75 {
  76    /* Gens < 7 don't have instructions to convert to or from half-precision,
  77     * and Gens < 6 don't expose that functionality.
  78     */
  79    if (brw->gen != 6)
  80       return;
  81
  82    lower_packing_builtins(ir, LOWER_PACK_HALF_2x16 | LOWER_UNPACK_HALF_2x16);
  83 }
  84
  85 static void
  86 process_glsl_ir(struct brw_context *brw,
  87                 struct gl_shader_program *shader_prog,
  88                 struct gl_linked_shader *shader)
  89 {
  90    struct gl_context *ctx = &brw->ctx;
  91    const struct brw_compiler *compiler = brw->screen->compiler;
  92    const struct gl_shader_compiler_options *options =
  93       &ctx->Const.ShaderCompilerOptions[shader->Stage];
  94
  95    /* Temporary memory context for any new IR. */
  96    void *mem_ctx = ralloc_context(NULL);
  97
  98    ralloc_adopt(mem_ctx, shader->ir);
  99
 100    lower_blend_equation_advanced(shader);
 101
 102    /* lower_packing_builtins() inserts arithmetic instructions, so it
 103     * must precede lower_instructions().
 104     */
 105    brw_lower_packing_builtins(brw, shader->ir);
 106    do_mat_op_to_vec(shader->ir);
 107
 108    unsigned instructions_to_lower = (DIV_TO_MUL_RCP |
 109                                      SUB_TO_ADD_NEG |
 110                                      EXP_TO_EXP2 |
 111                                      LOG_TO_LOG2 |
 112                                      DFREXP_DLDEXP_TO_ARITH);
 113    if (brw->gen < 7) {
 114       instructions_to_lower |= BIT_COUNT_TO_MATH |
 115                                EXTRACT_TO_SHIFTS |
 116                                INSERT_TO_SHIFTS |
 117                                REVERSE_TO_SHIFTS;
 118    }
 119
 120    lower_instructions(shader->ir, instructions_to_lower);
 121    lower_64bit_integer_instructions(shader->ir,
 122                                     MUL64 |
 123                                     DIV64 |
 124                                     MOD64 |
 125                                     SIGN64);
 126
 127    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 128     * if-statements need to be flattened.
 129     */
 130    if (brw->gen < 6)
 131       lower_if_to_cond_assign(shader->Stage, shader->ir, 16);
 132
 133    do_lower_texture_projection(shader->ir);
 134    do_vec_index_to_cond_assign(shader->ir);
 135    lower_vector_insert(shader->ir, true);
 136    lower_offset_arrays(shader->ir);
 137    lower_noise(shader->ir);
 138    lower_quadop_vector(shader->ir, false);
 139
 140    bool progress;
 141    do {
 142       progress = false;
 143
 144       if (compiler->scalar_stage[shader->Stage]) {
 145          if (shader->Stage == MESA_SHADER_VERTEX ||
 146              shader->Stage == MESA_SHADER_FRAGMENT)
 147             brw_do_channel_expressions(shader->ir);
 148          brw_do_vector_splitting(shader->ir);
 149       }
 150
 151       progress = do_common_optimization(shader->ir, true, true,
 152                                         options, ctx->Const.NativeIntegers) || progress;
 153    } while (progress);
 154
 155    validate_ir_tree(shader->ir);
 156
 157    /* Now that we've finished altering the linked IR, reparent any live IR back
 158     * to the permanent memory context, and free the temporary one (discarding any
 159     * junk we optimized away).
 160     */
 161    reparent_ir(shader->ir, shader->ir);
 162    ralloc_free(mem_ctx);
 163
 164    if (ctx->_Shader->Flags & GLSL_DUMP) {
 165       fprintf(stderr, "\n");
 166       if (shader->ir) {
 167          fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 168                  _mesa_shader_stage_to_string(shader->Stage),
 169                  shader_prog->Name);
 170          _mesa_print_ir(stderr, shader->ir, NULL);
 171       } else {
 172          fprintf(stderr, "No GLSL IR for linked %s program %d (shader may be "
 173                  "from cache)\n", _mesa_shader_stage_to_string(shader->Stage),
 174                  shader_prog->Name);
 175       }
 176       fprintf(stderr, "\n");
 177    }
 178 }
 179
 180 static void
 181 unify_interfaces(struct shader_info **infos)
 182 {
 183    struct shader_info *prev_info = NULL;
 184
 185    for (unsigned i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
 186       if (!infos[i])
 187          continue;
 188
 189       if (prev_info) {
 190          prev_info->outputs_written |= infos[i]->inputs_read &
 191             ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
 192          infos[i]->inputs_read |= prev_info->outputs_written &
 193             ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
 194
 195          prev_info->patch_outputs_written |= infos[i]->patch_inputs_read;
 196          infos[i]->patch_inputs_read |= prev_info->patch_outputs_written;
 197       }
 198       prev_info = infos[i];
 199    }
 200 }
 201
 202 extern "C" GLboolean
 203 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 204 {
 205    struct brw_context *brw = brw_context(ctx);
 206    const struct brw_compiler *compiler = brw->screen->compiler;
 207    unsigned int stage;
 208    struct shader_info *infos[MESA_SHADER_STAGES] = { 0, };
 209
 210    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 211       struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
 212       if (!shader)
 213          continue;
 214
 215       struct gl_program *prog = shader->Program;
 216       prog->Parameters = _mesa_new_parameter_list();
 217
 218       process_glsl_ir(brw, shProg, shader);
 219
 220       _mesa_copy_linked_program_data(shProg, shader);
 221
 222       prog->ShadowSamplers = shader->shadow_samplers;
 223       _mesa_update_shader_textures_used(shProg, prog);
 224
 225       bool debug_enabled =
 226          (INTEL_DEBUG & intel_debug_flag_for_shader_stage(shader->Stage));
 227
 228       if (debug_enabled && shader->ir) {
 229          fprintf(stderr, "GLSL IR for native %s shader %d:\n",
 230                  _mesa_shader_stage_to_string(shader->Stage), shProg->Name);
 231          _mesa_print_ir(stderr, shader->ir, NULL);
 232          fprintf(stderr, "\n\n");
 233       }
 234
 235       prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 236                                  compiler->scalar_stage[stage]);
 237       infos[stage] = prog->nir->info;
 238
 239       /* Make a pass over the IR to add state references for any built-in
 240        * uniforms that are used.  This has to be done now (during linking).
 241        * Code generation doesn't happen until the first time this shader is
 242        * used for rendering.  Waiting until then to generate the parameters is
 243        * too late.  At that point, the values for the built-in uniforms won't
 244        * get sent to the shader.
 245        */
 246       nir_foreach_variable(var, &prog->nir->uniforms) {
 247          if (strncmp(var->name, "gl_", 3) == 0) {
 248             const nir_state_slot *const slots = var->state_slots;
 249             assert(var->state_slots != NULL);
 250
 251             for (unsigned int i = 0; i < var->num_state_slots; i++) {
 252                _mesa_add_state_reference(prog->Parameters,
 253                                          (gl_state_index *)slots[i].tokens);
 254             }
 255          }
 256       }
 257    }
 258
 259    /* The linker tries to dead code eliminate unused varying components,
 260     * and make sure interfaces match.  But it isn't able to do so in all
 261     * cases.  So, explicitly make the interfaces match by OR'ing together
 262     * the inputs_read/outputs_written bitfields of adjacent stages.
 263     */
 264    if (!shProg->SeparateShader)
 265       unify_interfaces(infos);
 266
 267    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 268       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 269          const struct gl_shader *sh = shProg->Shaders[i];
 270          if (!sh)
 271             continue;
 272
 273          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 274                  _mesa_shader_stage_to_string(sh->Stage),
 275                  i, shProg->Name);
 276          fprintf(stderr, "%s", sh->Source);
 277          fprintf(stderr, "\n");
 278       }
 279    }
 280
 281    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 282       return false;
 283
 284    build_program_resource_list(ctx, shProg);
 285
 286    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 287       struct gl_linked_shader *shader = shProg->_LinkedShaders[stage];
 288       if (!shader)
 289          continue;
 290
 291       /* The GLSL IR won't be needed anymore. */
 292       ralloc_free(shader->ir);
 293       shader->ir = NULL;
 294    }
 295
 296    return true;
 297 }