src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_regions.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40
  41
  42
  43
  44
  45 /***********************************************************************
  46  * Blend color
  47  */
  48
  49 static void upload_blend_constant_color(struct brw_context *brw)
  50 {
  51    GLcontext *ctx = &brw->intel.ctx;
  52    struct brw_blend_constant_color bcc;
  53
  54    memset(&bcc, 0, sizeof(bcc));
  55    bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
  56    bcc.header.length = sizeof(bcc)/4-2;
  57    bcc.blend_constant_color[0] = ctx->Color.BlendColor[0];
  58    bcc.blend_constant_color[1] = ctx->Color.BlendColor[1];
  59    bcc.blend_constant_color[2] = ctx->Color.BlendColor[2];
  60    bcc.blend_constant_color[3] = ctx->Color.BlendColor[3];
  61
  62    BRW_CACHED_BATCH_STRUCT(brw, &bcc);
  63 }
  64
  65
  66 const struct brw_tracked_state brw_blend_constant_color = {
  67    .dirty = {
  68       .mesa = _NEW_COLOR,
  69       .brw = BRW_NEW_CONTEXT,
  70       .cache = 0
  71    },
  72    .emit = upload_blend_constant_color
  73 };
  74
  75 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  76 static void upload_drawing_rect(struct brw_context *brw)
  77 {
  78    struct intel_context *intel = &brw->intel;
  79    GLcontext *ctx = &intel->ctx;
  80
  81    BEGIN_BATCH(4);
  82    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  83    OUT_BATCH(0); /* xmin, ymin */
  84    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  85             ((ctx->DrawBuffer->Height - 1) << 16));
  86    OUT_BATCH(0);
  87    ADVANCE_BATCH();
  88 }
  89
  90 const struct brw_tracked_state brw_drawing_rect = {
  91    .dirty = {
  92       .mesa = _NEW_BUFFERS,
  93       .brw = BRW_NEW_CONTEXT,
  94       .cache = 0
  95    },
  96    .emit = upload_drawing_rect
  97 };
  98
  99 static void prepare_binding_table_pointers(struct brw_context *brw)
 100 {
 101    brw_add_validated_bo(brw, brw->vs.bind_bo);
 102    brw_add_validated_bo(brw, brw->wm.bind_bo);
 103 }
 104
 105 /**
 106  * Upload the binding table pointers, which point each stage's array of surface
 107  * state pointers.
 108  *
 109  * The binding table pointers are relative to the surface state base address,
 110  * which is 0.
 111  */
 112 static void upload_binding_table_pointers(struct brw_context *brw)
 113 {
 114    struct intel_context *intel = &brw->intel;
 115
 116    BEGIN_BATCH(6);
 117    OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
 118    if (brw->vs.bind_bo != NULL)
 119       OUT_RELOC(brw->vs.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* vs */
 120    else
 121       OUT_BATCH(0);
 122    OUT_BATCH(0); /* gs */
 123    OUT_BATCH(0); /* clip */
 124    OUT_BATCH(0); /* sf */
 125    OUT_RELOC(brw->wm.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* wm/ps */
 126    ADVANCE_BATCH();
 127 }
 128
 129 const struct brw_tracked_state brw_binding_table_pointers = {
 130    .dirty = {
 131       .mesa = 0,
 132       .brw = BRW_NEW_BATCH,
 133       .cache = CACHE_NEW_SURF_BIND,
 134    },
 135    .prepare = prepare_binding_table_pointers,
 136    .emit = upload_binding_table_pointers,
 137 };
 138
 139
 140 /**
 141  * Upload pointers to the per-stage state.
 142  *
 143  * The state pointers in this packet are all relative to the general state
 144  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 145  */
 146 static void upload_pipelined_state_pointers(struct brw_context *brw )
 147 {
 148    struct intel_context *intel = &brw->intel;
 149
 150    BEGIN_BATCH(7);
 151    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
 152    OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 153    if (brw->gs.prog_active)
 154       OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
 155    else
 156       OUT_BATCH(0);
 157    OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
 158    OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 159    OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 160    OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 161    ADVANCE_BATCH();
 162
 163    brw->state.dirty.brw |= BRW_NEW_PSP;
 164 }
 165
 166
 167 static void prepare_psp_urb_cbs(struct brw_context *brw)
 168 {
 169    brw_add_validated_bo(brw, brw->vs.state_bo);
 170    brw_add_validated_bo(brw, brw->gs.state_bo);
 171    brw_add_validated_bo(brw, brw->clip.state_bo);
 172    brw_add_validated_bo(brw, brw->sf.state_bo);
 173    brw_add_validated_bo(brw, brw->wm.state_bo);
 174    brw_add_validated_bo(brw, brw->cc.state_bo);
 175 }
 176
 177 static void upload_psp_urb_cbs(struct brw_context *brw )
 178 {
 179    upload_pipelined_state_pointers(brw);
 180    brw_upload_urb_fence(brw);
 181    brw_upload_cs_urb_state(brw);
 182 }
 183
 184 const struct brw_tracked_state brw_psp_urb_cbs = {
 185    .dirty = {
 186       .mesa = 0,
 187       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 188       .cache = (CACHE_NEW_VS_UNIT |
 189                 CACHE_NEW_GS_UNIT |
 190                 CACHE_NEW_GS_PROG |
 191                 CACHE_NEW_CLIP_UNIT |
 192                 CACHE_NEW_SF_UNIT |
 193                 CACHE_NEW_WM_UNIT |
 194                 CACHE_NEW_CC_UNIT)
 195    },
 196    .prepare = prepare_psp_urb_cbs,
 197    .emit = upload_psp_urb_cbs,
 198 };
 199
 200 static void prepare_depthbuffer(struct brw_context *brw)
 201 {
 202    struct intel_region *region = brw->state.depth_region;
 203
 204    if (region != NULL)
 205       brw_add_validated_bo(brw, region->buffer);
 206 }
 207
 208 static void emit_depthbuffer(struct brw_context *brw)
 209 {
 210    struct intel_context *intel = &brw->intel;
 211    struct intel_region *region = brw->state.depth_region;
 212    unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5;
 213
 214    if (region == NULL) {
 215       BEGIN_BATCH(len);
 216       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 217       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 218                 (BRW_SURFACE_NULL << 29));
 219       OUT_BATCH(0);
 220       OUT_BATCH(0);
 221       OUT_BATCH(0);
 222
 223       if (intel->is_g4x || intel->is_ironlake)
 224          OUT_BATCH(0);
 225
 226       ADVANCE_BATCH();
 227    } else {
 228       unsigned int format;
 229
 230       switch (region->cpp) {
 231       case 2:
 232          format = BRW_DEPTHFORMAT_D16_UNORM;
 233          break;
 234       case 4:
 235          if (intel->depth_buffer_is_float)
 236             format = BRW_DEPTHFORMAT_D32_FLOAT;
 237          else
 238             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 239          break;
 240       default:
 241          assert(0);
 242          return;
 243       }
 244
 245       assert(region->tiling != I915_TILING_X);
 246
 247       BEGIN_BATCH(len);
 248       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 249       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 250                 (format << 18) |
 251                 (BRW_TILEWALK_YMAJOR << 26) |
 252                 ((region->tiling != I915_TILING_NONE) << 27) |
 253                 (BRW_SURFACE_2D << 29));
 254       OUT_RELOC(region->buffer,
 255                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 256                 0);
 257       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 258                 ((region->pitch - 1) << 6) |
 259                 ((region->height - 1) << 19));
 260       OUT_BATCH(0);
 261
 262       if (intel->is_g4x || intel->is_ironlake)
 263          OUT_BATCH(0);
 264
 265       ADVANCE_BATCH();
 266    }
 267 }
 268
 269 const struct brw_tracked_state brw_depthbuffer = {
 270    .dirty = {
 271       .mesa = 0,
 272       .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
 273       .cache = 0,
 274    },
 275    .prepare = prepare_depthbuffer,
 276    .emit = emit_depthbuffer,
 277 };
 278
 279
 280
 281 /***********************************************************************
 282  * Polygon stipple packet
 283  */
 284
 285 static void upload_polygon_stipple(struct brw_context *brw)
 286 {
 287    GLcontext *ctx = &brw->intel.ctx;
 288    struct brw_polygon_stipple bps;
 289    GLuint i;
 290
 291    memset(&bps, 0, sizeof(bps));
 292    bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
 293    bps.header.length = sizeof(bps)/4-2;
 294
 295    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 296     * row first.  If we're rendering to a window (i.e. the
 297     * default frame buffer object, 0), then we need to invert
 298     * it to match our pixel layout.  But if we're rendering
 299     * to a FBO (i.e. any named frame buffer object), we *don't*
 300     * need to invert - we already match the layout.
 301     */
 302    if (ctx->DrawBuffer->Name == 0) {
 303       for (i = 0; i < 32; i++)
 304          bps.stipple[i] = ctx->PolygonStipple[31 - i]; /* invert */
 305    }
 306    else {
 307       for (i = 0; i < 32; i++)
 308          bps.stipple[i] = ctx->PolygonStipple[i]; /* don't invert */
 309    }
 310
 311    BRW_CACHED_BATCH_STRUCT(brw, &bps);
 312 }
 313
 314 const struct brw_tracked_state brw_polygon_stipple = {
 315    .dirty = {
 316       .mesa = _NEW_POLYGONSTIPPLE,
 317       .brw = BRW_NEW_CONTEXT,
 318       .cache = 0
 319    },
 320    .emit = upload_polygon_stipple
 321 };
 322
 323
 324 /***********************************************************************
 325  * Polygon stipple offset packet
 326  */
 327
 328 static void upload_polygon_stipple_offset(struct brw_context *brw)
 329 {
 330    __DRIdrawable *dPriv = brw->intel.driDrawable;
 331    struct brw_polygon_stipple_offset bpso;
 332
 333    memset(&bpso, 0, sizeof(bpso));
 334    bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
 335    bpso.header.length = sizeof(bpso)/4-2;
 336
 337    /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 338     * we have to invert the Y axis in order to match the OpenGL
 339     * pixel coordinate system, and our offset must be matched
 340     * to the window position.  If we're drawing to a FBO
 341     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 342     * system works just fine, and there's no window system to
 343     * worry about.
 344     */
 345    if (brw->intel.ctx.DrawBuffer->Name == 0) {
 346       bpso.bits0.x_offset = (32 - (dPriv->x & 31)) & 31;
 347       bpso.bits0.y_offset = (32 - ((dPriv->y + dPriv->h) & 31)) & 31;
 348    }
 349    else {
 350       bpso.bits0.y_offset = 0;
 351       bpso.bits0.x_offset = 0;
 352    }
 353
 354    BRW_CACHED_BATCH_STRUCT(brw, &bpso);
 355 }
 356
 357 #define _NEW_WINDOW_POS 0x40000000
 358
 359 const struct brw_tracked_state brw_polygon_stipple_offset = {
 360    .dirty = {
 361       .mesa = _NEW_WINDOW_POS,
 362       .brw = BRW_NEW_CONTEXT,
 363       .cache = 0
 364    },
 365    .emit = upload_polygon_stipple_offset
 366 };
 367
 368 /**********************************************************************
 369  * AA Line parameters
 370  */
 371 static void upload_aa_line_parameters(struct brw_context *brw)
 372 {
 373    struct brw_aa_line_parameters balp;
 374
 375    if (!brw->has_aa_line_parameters)
 376       return;
 377
 378    /* use legacy aa line coverage computation */
 379    memset(&balp, 0, sizeof(balp));
 380    balp.header.opcode = CMD_AA_LINE_PARAMETERS;
 381    balp.header.length = sizeof(balp) / 4 - 2;
 382
 383    BRW_CACHED_BATCH_STRUCT(brw, &balp);
 384 }
 385
 386 const struct brw_tracked_state brw_aa_line_parameters = {
 387    .dirty = {
 388       .mesa = 0,
 389       .brw = BRW_NEW_CONTEXT,
 390       .cache = 0
 391    },
 392    .emit = upload_aa_line_parameters
 393 };
 394
 395 /***********************************************************************
 396  * Line stipple packet
 397  */
 398
 399 static void upload_line_stipple(struct brw_context *brw)
 400 {
 401    GLcontext *ctx = &brw->intel.ctx;
 402    struct brw_line_stipple bls;
 403    GLfloat tmp;
 404    GLint tmpi;
 405
 406    memset(&bls, 0, sizeof(bls));
 407    bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
 408    bls.header.length = sizeof(bls)/4 - 2;
 409
 410    bls.bits0.pattern = ctx->Line.StipplePattern;
 411    bls.bits1.repeat_count = ctx->Line.StippleFactor;
 412
 413    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 414    tmpi = tmp * (1<<13);
 415
 416
 417    bls.bits1.inverse_repeat_count = tmpi;
 418
 419    BRW_CACHED_BATCH_STRUCT(brw, &bls);
 420 }
 421
 422 const struct brw_tracked_state brw_line_stipple = {
 423    .dirty = {
 424       .mesa = _NEW_LINE,
 425       .brw = BRW_NEW_CONTEXT,
 426       .cache = 0
 427    },
 428    .emit = upload_line_stipple
 429 };
 430
 431
 432 /***********************************************************************
 433  * Misc invarient state packets
 434  */
 435
 436 static void upload_invarient_state( struct brw_context *brw )
 437 {
 438    {
 439       /* 0x61040000  Pipeline Select */
 440       /*     PipelineSelect            : 0 */
 441       struct brw_pipeline_select ps;
 442
 443       memset(&ps, 0, sizeof(ps));
 444       ps.header.opcode = brw->CMD_PIPELINE_SELECT;
 445       ps.header.pipeline_select = 0;
 446       BRW_BATCH_STRUCT(brw, &ps);
 447    }
 448
 449    {
 450       struct brw_global_depth_offset_clamp gdo;
 451       memset(&gdo, 0, sizeof(gdo));
 452
 453       /* Disable depth offset clamping.
 454        */
 455       gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP;
 456       gdo.header.length = sizeof(gdo)/4 - 2;
 457       gdo.depth_offset_clamp = 0.0;
 458
 459       BRW_BATCH_STRUCT(brw, &gdo);
 460    }
 461
 462
 463    /* 0x61020000  State Instruction Pointer */
 464    {
 465       struct brw_system_instruction_pointer sip;
 466       memset(&sip, 0, sizeof(sip));
 467
 468       sip.header.opcode = CMD_STATE_INSN_POINTER;
 469       sip.header.length = 0;
 470       sip.bits0.pad = 0;
 471       sip.bits0.system_instruction_pointer = 0;
 472       BRW_BATCH_STRUCT(brw, &sip);
 473    }
 474
 475
 476    {
 477       struct brw_vf_statistics vfs;
 478       memset(&vfs, 0, sizeof(vfs));
 479
 480       vfs.opcode = brw->CMD_VF_STATISTICS;
 481       if (INTEL_DEBUG & DEBUG_STATS)
 482          vfs.statistics_enable = 1;
 483
 484       BRW_BATCH_STRUCT(brw, &vfs);
 485    }
 486 }
 487
 488 const struct brw_tracked_state brw_invarient_state = {
 489    .dirty = {
 490       .mesa = 0,
 491       .brw = BRW_NEW_CONTEXT,
 492       .cache = 0
 493    },
 494    .emit = upload_invarient_state
 495 };
 496
 497 /**
 498  * Define the base addresses which some state is referenced from.
 499  *
 500  * This allows us to avoid having to emit relocations in many places for
 501  * cached state, and instead emit pointers inside of large, mostly-static
 502  * state pools.  This comes at the expense of memory, and more expensive cache
 503  * misses.
 504  */
 505 static void upload_state_base_address( struct brw_context *brw )
 506 {
 507    struct intel_context *intel = &brw->intel;
 508
 509    /* Output the structure (brw_state_base_address) directly to the
 510     * batchbuffer, so we can emit relocations inline.
 511     */
 512    if (intel->is_ironlake) {
 513        BEGIN_BATCH(8);
 514        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
 515        OUT_BATCH(1); /* General state base address */
 516        OUT_BATCH(1); /* Surface state base address */
 517        OUT_BATCH(1); /* Indirect object base address */
 518        OUT_BATCH(1); /* Instruction base address */
 519        OUT_BATCH(1); /* General state upper bound */
 520        OUT_BATCH(1); /* Indirect object upper bound */
 521        OUT_BATCH(1); /* Instruction access upper bound */
 522        ADVANCE_BATCH();
 523    } else {
 524        BEGIN_BATCH(6);
 525        OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 526        OUT_BATCH(1); /* General state base address */
 527        OUT_BATCH(1); /* Surface state base address */
 528        OUT_BATCH(1); /* Indirect object base address */
 529        OUT_BATCH(1); /* General state upper bound */
 530        OUT_BATCH(1); /* Indirect object upper bound */
 531        ADVANCE_BATCH();
 532    }
 533 }
 534
 535 const struct brw_tracked_state brw_state_base_address = {
 536    .dirty = {
 537       .mesa = 0,
 538       .brw = BRW_NEW_CONTEXT,
 539       .cache = 0,
 540    },
 541    .emit = upload_state_base_address
 542 };