2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
41 #include "compiler/brw_eu_defines.h"
43 #include "main/framebuffer.h"
44 #include "main/fbobject.h"
45 #include "main/glformats.h"
47 /* Constant single cliprect for framebuffer object or DRI2 drawing */
49 upload_drawing_rect(struct brw_context
*brw
)
51 struct gl_context
*ctx
= &brw
->ctx
;
52 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
53 const unsigned int fb_width
= _mesa_geometric_width(fb
);
54 const unsigned int fb_height
= _mesa_geometric_height(fb
);
57 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
58 OUT_BATCH(0); /* xmin, ymin */
59 OUT_BATCH(((fb_width
- 1) & 0xffff) | ((fb_height
- 1) << 16));
64 const struct brw_tracked_state brw_drawing_rect
= {
67 .brw
= BRW_NEW_BLORP
|
70 .emit
= upload_drawing_rect
74 * Upload pointers to the per-stage state.
76 * The state pointers in this packet are all relative to the general state
77 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
80 upload_pipelined_state_pointers(struct brw_context
*brw
)
83 /* Need to flush before changing clip max threads for errata. */
90 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
91 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
92 brw
->vs
.base
.state_offset
);
93 if (brw
->ff_gs
.prog_active
)
94 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
95 brw
->ff_gs
.state_offset
| 1);
98 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
99 brw
->clip
.state_offset
| 1);
100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
101 brw
->sf
.state_offset
);
102 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
103 brw
->wm
.base
.state_offset
);
104 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
105 brw
->cc
.state_offset
);
108 brw
->ctx
.NewDriverState
|= BRW_NEW_PSP
;
112 upload_psp_urb_cbs(struct brw_context
*brw
)
114 upload_pipelined_state_pointers(brw
);
115 brw_upload_urb_fence(brw
);
116 brw_upload_cs_urb_state(brw
);
119 const struct brw_tracked_state brw_psp_urb_cbs
= {
122 .brw
= BRW_NEW_BATCH
|
124 BRW_NEW_FF_GS_PROG_DATA
|
125 BRW_NEW_GEN4_UNIT_STATE
|
126 BRW_NEW_STATE_BASE_ADDRESS
|
129 .emit
= upload_psp_urb_cbs
,
133 brw_depthbuffer_format(struct brw_context
*brw
)
135 struct gl_context
*ctx
= &brw
->ctx
;
136 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
137 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
138 struct intel_renderbuffer
*srb
;
141 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
142 !srb
->mt
->stencil_mt
&&
143 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
144 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
149 return BRW_DEPTHFORMAT_D32_FLOAT
;
151 return brw_depth_format(brw
, drb
->mt
->format
);
155 * Returns the mask of how many bits of x and y must be handled through the
156 * depthbuffer's draw offset x and y fields.
158 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
159 * between the depth, hiz, and stencil buffers. Because it can be hard to get
160 * all 3 to agree on this value, we want to do as much drawing offset
161 * adjustment as possible by moving the base offset of the 3 buffers, which is
162 * restricted to tile boundaries.
164 * For each buffer, the remainder must be applied through the x/y draw offset.
165 * This returns the worst-case mask of the low bits that have to go into the
166 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
167 * mask, then we're in trouble.
170 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
171 uint32_t depth_level
,
172 uint32_t depth_layer
,
173 struct intel_mipmap_tree
*stencil_mt
,
174 uint32_t *out_tile_mask_x
,
175 uint32_t *out_tile_mask_y
)
177 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
180 intel_get_tile_masks(depth_mt
->tiling
, depth_mt
->tr_mode
,
182 &tile_mask_x
, &tile_mask_y
);
183 assert(!intel_miptree_level_has_hiz(depth_mt
, depth_level
));
187 if (stencil_mt
->stencil_mt
)
188 stencil_mt
= stencil_mt
->stencil_mt
;
190 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
191 /* Separate stencil buffer uses 64x64 tiles. */
195 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
196 intel_get_tile_masks(stencil_mt
->tiling
,
199 &stencil_tile_mask_x
,
200 &stencil_tile_mask_y
);
202 tile_mask_x
|= stencil_tile_mask_x
;
203 tile_mask_y
|= stencil_tile_mask_y
;
207 *out_tile_mask_x
= tile_mask_x
;
208 *out_tile_mask_y
= tile_mask_y
;
211 static struct intel_mipmap_tree
*
212 get_stencil_miptree(struct intel_renderbuffer
*irb
)
216 if (irb
->mt
->stencil_mt
)
217 return irb
->mt
->stencil_mt
;
222 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
223 GLbitfield clear_mask
)
225 struct gl_context
*ctx
= &brw
->ctx
;
226 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
227 bool rebase_depth
= false;
228 bool rebase_stencil
= false;
229 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
230 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
231 struct intel_mipmap_tree
*depth_mt
= NULL
;
232 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
233 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
234 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
235 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
236 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
239 depth_mt
= depth_irb
->mt
;
241 /* Initialize brw->depthstencil to 'nop' workaround state.
243 brw
->depthstencil
.tile_x
= 0;
244 brw
->depthstencil
.tile_y
= 0;
245 brw
->depthstencil
.depth_offset
= 0;
246 brw
->depthstencil
.stencil_offset
= 0;
247 brw
->depthstencil
.hiz_offset
= 0;
248 brw
->depthstencil
.depth_mt
= NULL
;
249 brw
->depthstencil
.stencil_mt
= NULL
;
251 brw
->depthstencil
.depth_mt
= depth_mt
;
253 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
255 /* Gen6+ doesn't require the workarounds, since we always program the
256 * surface state at the start of the whole surface.
261 /* Check if depth buffer is in depth/stencil format. If so, then it's only
262 * safe to invalidate it if we're also clearing stencil, and both depth_irb
263 * and stencil_irb point to the same miptree.
265 * Note: it's not sufficient to check for the case where
266 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
267 * because this fails to catch depth/stencil buffers on hardware that uses
268 * separate stencil. To catch that case, we check whether
269 * depth_mt->stencil_mt is non-NULL.
271 if (depth_irb
&& invalidate_depth
&&
272 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
273 depth_mt
->stencil_mt
)) {
274 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
275 && depth_irb
->mt
== stencil_irb
->mt
;
278 uint32_t tile_mask_x
, tile_mask_y
;
279 brw_get_depthstencil_tile_masks(depth_mt
,
280 depth_mt
? depth_irb
->mt_level
: 0,
281 depth_mt
? depth_irb
->mt_layer
: 0,
283 &tile_mask_x
, &tile_mask_y
);
286 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
287 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
289 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
290 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
291 * Coordinate Offset X/Y":
293 * "The 3 LSBs of both offsets must be zero to ensure correct
296 if (tile_x
& 7 || tile_y
& 7)
299 /* We didn't even have intra-tile offsets before g45. */
300 if (!brw
->has_surface_tile_offset
) {
301 if (tile_x
|| tile_y
)
306 perf_debug("HW workaround: blitting depth level %d to a temporary "
307 "to fix alignment (depth tile offset %d,%d)\n",
308 depth_irb
->mt_level
, tile_x
, tile_y
);
309 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
310 /* In the case of stencil_irb being the same packed depth/stencil
311 * texture but not the same rb, make it point at our rebased mt, too.
314 stencil_irb
!= depth_irb
&&
315 stencil_irb
->mt
== depth_mt
) {
316 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
317 intel_renderbuffer_set_draw_offset(stencil_irb
);
320 stencil_mt
= get_stencil_miptree(stencil_irb
);
322 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
323 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
327 stencil_mt
= get_stencil_miptree(stencil_irb
);
328 intel_miptree_get_image_offset(stencil_mt
,
329 stencil_irb
->mt_level
,
330 stencil_irb
->mt_layer
,
331 &stencil_draw_x
, &stencil_draw_y
);
332 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
333 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
335 /* If stencil doesn't match depth, then we'll need to rebase stencil
336 * as well. (if we hadn't decided to rebase stencil before, the
337 * post-stencil depth test will also rebase depth to try to match it
340 if (tile_x
!= stencil_tile_x
||
341 tile_y
!= stencil_tile_y
) {
342 rebase_stencil
= true;
347 /* If we have (just) stencil, check it for ignored low bits as well */
349 intel_miptree_get_image_offset(stencil_mt
,
350 stencil_irb
->mt_level
,
351 stencil_irb
->mt_layer
,
352 &stencil_draw_x
, &stencil_draw_y
);
353 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
354 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
356 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
357 rebase_stencil
= true;
359 if (!brw
->has_surface_tile_offset
) {
360 if (stencil_tile_x
|| stencil_tile_y
)
361 rebase_stencil
= true;
365 if (rebase_stencil
) {
366 perf_debug("HW workaround: blitting stencil level %d to a temporary "
367 "to fix alignment (stencil tile offset %d,%d)\n",
368 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
370 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
371 stencil_mt
= get_stencil_miptree(stencil_irb
);
373 intel_miptree_get_image_offset(stencil_mt
,
374 stencil_irb
->mt_level
,
375 stencil_irb
->mt_layer
,
376 &stencil_draw_x
, &stencil_draw_y
);
377 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
378 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
380 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
381 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
382 intel_renderbuffer_set_draw_offset(depth_irb
);
383 } else if (depth_irb
&& !rebase_depth
) {
384 if (tile_x
!= stencil_tile_x
||
385 tile_y
!= stencil_tile_y
) {
386 perf_debug("HW workaround: blitting depth level %d to a temporary "
387 "to match stencil level %d alignment (depth tile offset "
388 "%d,%d, stencil offset %d,%d)\n",
390 stencil_irb
->mt_level
,
392 stencil_tile_x
, stencil_tile_y
);
394 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
396 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
397 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
399 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
400 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
401 intel_renderbuffer_set_draw_offset(stencil_irb
);
404 WARN_ONCE(stencil_tile_x
!= tile_x
||
405 stencil_tile_y
!= tile_y
,
406 "Rebased stencil tile offset (%d,%d) doesn't match depth "
407 "tile offset (%d,%d).\n",
408 stencil_tile_x
, stencil_tile_y
,
415 tile_x
= stencil_tile_x
;
416 tile_y
= stencil_tile_y
;
419 /* While we just tried to get everything aligned, we may have failed to do
420 * so in the case of rendering to array or 3D textures, where nonzero faces
421 * will still have an offset post-rebase. At least give an informative
424 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
425 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
426 "Truncating offset, bad rendering may occur.\n");
430 /* Now, after rebasing, save off the new dephtstencil state so the hardware
431 * packets can just dereference that without re-calculating tile offsets.
433 brw
->depthstencil
.tile_x
= tile_x
;
434 brw
->depthstencil
.tile_y
= tile_y
;
436 depth_mt
= depth_irb
->mt
;
437 brw
->depthstencil
.depth_mt
= depth_mt
;
438 brw
->depthstencil
.depth_offset
=
439 intel_miptree_get_aligned_offset(depth_mt
,
440 depth_irb
->draw_x
& ~tile_mask_x
,
441 depth_irb
->draw_y
& ~tile_mask_y
);
442 if (intel_renderbuffer_has_hiz(depth_irb
)) {
443 brw
->depthstencil
.hiz_offset
=
444 intel_miptree_get_aligned_offset(depth_mt
,
445 depth_irb
->draw_x
& ~tile_mask_x
,
446 (depth_irb
->draw_y
& ~tile_mask_y
) / 2);
450 stencil_mt
= get_stencil_miptree(stencil_irb
);
452 brw
->depthstencil
.stencil_mt
= stencil_mt
;
453 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
454 /* Note: we can't compute the stencil offset using
455 * intel_region_get_aligned_offset(), because stencil_region claims
456 * that the region is untiled even though it's W tiled.
458 brw
->depthstencil
.stencil_offset
=
459 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
460 (stencil_draw_x
& ~tile_mask_x
) * 64;
466 brw_emit_depthbuffer(struct brw_context
*brw
)
468 struct gl_context
*ctx
= &brw
->ctx
;
469 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
471 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
472 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
473 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
474 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
475 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
476 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
477 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
478 bool separate_stencil
= false;
479 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
480 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
481 uint32_t depth_offset
= 0;
482 uint32_t width
= 1, height
= 1;
485 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
487 /* Gen7 supports only separate stencil */
488 assert(separate_stencil
|| brw
->gen
< 7);
491 /* If there's a packed depth/stencil bound to stencil only, we need to
492 * emit the packed depth/stencil buffer packet.
494 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
495 depth_irb
= stencil_irb
;
496 depth_mt
= stencil_mt
;
499 if (depth_irb
&& depth_mt
) {
500 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
501 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
502 * depthstencil format.
504 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
505 * set to the same value. Gens after 7 implicitly always set
506 * Separate_Stencil_Enable; software cannot disable it.
508 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
509 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
512 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
513 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
515 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
516 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
518 depthbuffer_format
= brw_depthbuffer_format(brw
);
519 depth_surface_type
= BRW_SURFACE_2D
;
520 depth_offset
= brw
->depthstencil
.depth_offset
;
521 width
= depth_irb
->Base
.Base
.Width
;
522 height
= depth_irb
->Base
.Base
.Height
;
523 } else if (separate_stencil
) {
525 * There exists a separate stencil buffer but no depth buffer.
527 * The stencil buffer inherits most of its fields from
528 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
531 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
532 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
533 * [DevGT+]: This field must be set to TRUE.
535 assert(brw
->has_separate_stencil
);
537 depth_surface_type
= BRW_SURFACE_2D
;
538 width
= stencil_irb
->Base
.Base
.Width
;
539 height
= stencil_irb
->Base
.Base
.Height
;
543 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
545 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
547 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
548 depthbuffer_format
, depth_surface_type
,
549 stencil_mt
, hiz
, separate_stencil
,
550 width
, height
, tile_x
, tile_y
);
554 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
555 struct intel_mipmap_tree
*depth_mt
,
556 uint32_t depth_offset
, uint32_t depthbuffer_format
,
557 uint32_t depth_surface_type
,
558 struct intel_mipmap_tree
*stencil_mt
,
559 bool hiz
, bool separate_stencil
,
560 uint32_t width
, uint32_t height
,
561 uint32_t tile_x
, uint32_t tile_y
)
563 /* Enable the hiz bit if we're doing separate stencil, because it and the
564 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
565 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
566 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
567 * Enable must also be enabled.
569 * [DevGT]: This field must be set to the same value (enabled or
570 * disabled) as Hierarchical Depth Buffer Enable
572 bool enable_hiz_ss
= hiz
|| separate_stencil
;
575 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
576 * non-pipelined state that will need the PIPE_CONTROL workaround.
579 brw_emit_depth_stall_flushes(brw
);
585 else if (brw
->is_g4x
|| brw
->gen
== 5)
591 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
592 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
593 (depthbuffer_format
<< 18) |
594 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
595 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
596 (BRW_TILEWALK_YMAJOR
<< 26) |
597 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
599 (depth_surface_type
<< 29));
602 OUT_RELOC(depth_mt
->bo
,
603 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
609 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
610 ((height
+ tile_y
- 1) << 19));
613 if (brw
->is_g4x
|| brw
->gen
>= 5)
614 OUT_BATCH(tile_x
| (tile_y
<< 16));
616 assert(tile_x
== 0 && tile_y
== 0);
623 if (hiz
|| separate_stencil
) {
625 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
626 * stencil enable' and 'hiz enable' bits were set. Therefore we must
627 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
628 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
629 * failure to do so causes hangs on gen5 and a stall on gen6.
632 /* Emit hiz buffer. */
636 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
637 OUT_BATCH(depth_mt
->hiz_buf
->aux_base
.pitch
- 1);
638 OUT_RELOC(depth_mt
->hiz_buf
->aux_base
.bo
,
639 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
640 brw
->depthstencil
.hiz_offset
);
644 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
650 /* Emit stencil buffer. */
651 if (separate_stencil
) {
653 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
654 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
655 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
656 * The pitch must be set to 2x the value computed based on width, as
657 * the stencil buffer is stored with two rows interleaved.
659 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
660 OUT_RELOC(stencil_mt
->bo
,
661 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
662 brw
->depthstencil
.stencil_offset
);
666 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
674 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
675 * params must be emitted.
677 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
678 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
679 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
681 if (brw
->gen
>= 6 || hiz
) {
683 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
684 GEN5_DEPTH_CLEAR_VALID
|
686 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
691 const struct brw_tracked_state brw_depthbuffer
= {
693 .mesa
= _NEW_BUFFERS
,
694 .brw
= BRW_NEW_BATCH
|
697 .emit
= brw_emit_depthbuffer
,
701 * Polygon stipple packet
704 upload_polygon_stipple(struct brw_context
*brw
)
706 struct gl_context
*ctx
= &brw
->ctx
;
710 if (!ctx
->Polygon
.StippleFlag
)
714 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
716 /* Polygon stipple is provided in OpenGL order, i.e. bottom
717 * row first. If we're rendering to a window (i.e. the
718 * default frame buffer object, 0), then we need to invert
719 * it to match our pixel layout. But if we're rendering
720 * to a FBO (i.e. any named frame buffer object), we *don't*
721 * need to invert - we already match the layout.
723 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
724 for (i
= 0; i
< 32; i
++)
725 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
727 for (i
= 0; i
< 32; i
++)
728 OUT_BATCH(ctx
->PolygonStipple
[i
]);
733 const struct brw_tracked_state brw_polygon_stipple
= {
735 .mesa
= _NEW_POLYGON
|
737 .brw
= BRW_NEW_CONTEXT
,
739 .emit
= upload_polygon_stipple
743 * Polygon stipple offset packet
746 upload_polygon_stipple_offset(struct brw_context
*brw
)
748 struct gl_context
*ctx
= &brw
->ctx
;
751 if (!ctx
->Polygon
.StippleFlag
)
755 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
759 * If we're drawing to a system window we have to invert the Y axis
760 * in order to match the OpenGL pixel coordinate system, and our
761 * offset must be matched to the window position. If we're drawing
762 * to a user-created FBO then our native pixel coordinate system
763 * works just fine, and there's no window system to worry about.
765 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
766 OUT_BATCH((32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31);
772 const struct brw_tracked_state brw_polygon_stipple_offset
= {
774 .mesa
= _NEW_BUFFERS
|
776 .brw
= BRW_NEW_CONTEXT
,
778 .emit
= upload_polygon_stipple_offset
782 * Line stipple packet
785 upload_line_stipple(struct brw_context
*brw
)
787 struct gl_context
*ctx
= &brw
->ctx
;
791 if (!ctx
->Line
.StippleFlag
)
795 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
796 OUT_BATCH(ctx
->Line
.StipplePattern
);
800 tmp
= 1.0f
/ ctx
->Line
.StippleFactor
;
801 tmpi
= tmp
* (1<<16);
802 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
805 tmp
= 1.0f
/ ctx
->Line
.StippleFactor
;
806 tmpi
= tmp
* (1<<13);
807 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
813 const struct brw_tracked_state brw_line_stipple
= {
816 .brw
= BRW_NEW_CONTEXT
,
818 .emit
= upload_line_stipple
822 brw_emit_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
824 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
825 const uint32_t _3DSTATE_PIPELINE_SELECT
=
826 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
828 if (brw
->gen
>= 8 && brw
->gen
< 10) {
829 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
831 * Software must clear the COLOR_CALC_STATE Valid field in
832 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
833 * with Pipeline Select set to GPGPU.
835 * The internal hardware docs recommend the same workaround for Gen9
838 if (pipeline
== BRW_COMPUTE_PIPELINE
) {
840 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
844 brw
->ctx
.NewDriverState
|= BRW_NEW_CC_STATE
;
847 } else if (brw
->gen
>= 6) {
848 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
849 * PIPELINE_SELECT [DevBWR+]":
853 * Software must ensure all the write caches are flushed through a
854 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
855 * command to invalidate read only caches prior to programming
856 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
858 const unsigned dc_flush
=
859 brw
->gen
>= 7 ? PIPE_CONTROL_DATA_CACHE_FLUSH
: 0;
861 brw_emit_pipe_control_flush(brw
,
862 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
863 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
865 PIPE_CONTROL_NO_WRITE
|
866 PIPE_CONTROL_CS_STALL
);
868 brw_emit_pipe_control_flush(brw
,
869 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
870 PIPE_CONTROL_CONST_CACHE_INVALIDATE
|
871 PIPE_CONTROL_STATE_CACHE_INVALIDATE
|
872 PIPE_CONTROL_INSTRUCTION_INVALIDATE
|
873 PIPE_CONTROL_NO_WRITE
);
876 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
877 * PIPELINE_SELECT [DevBWR+]":
879 * Project: PRE-DEVSNB
881 * Software must ensure the current pipeline is flushed via an
882 * MI_FLUSH or PIPE_CONTROL prior to the execution of PIPELINE_SELECT.
889 /* Select the pipeline */
891 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 |
892 (brw
->gen
>= 9 ? (3 << 8) : 0) |
893 (pipeline
== BRW_COMPUTE_PIPELINE
? 2 : 0));
896 if (brw
->gen
== 7 && !brw
->is_haswell
&&
897 pipeline
== BRW_RENDER_PIPELINE
) {
898 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
899 * PIPELINE_SELECT [DevBWR+]":
901 * Project: DEVIVB, DEVHSW:GT3:A0
903 * Software must send a pipe_control with a CS stall and a post sync
904 * operation and then a dummy DRAW after every MI_SET_CONTEXT and
905 * after any PIPELINE_SELECT that is enabling 3D mode.
907 gen7_emit_cs_stall_flush(brw
);
910 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2));
911 OUT_BATCH(_3DPRIM_POINTLIST
);
922 * Misc invariant state packets
925 brw_upload_invariant_state(struct brw_context
*brw
)
927 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
929 brw_emit_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
930 brw
->last_pipeline
= BRW_RENDER_PIPELINE
;
934 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
940 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
945 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
948 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
949 /* use legacy aa line coverage computation */
955 const uint32_t _3DSTATE_VF_STATISTICS
=
956 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
958 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
962 const struct brw_tracked_state brw_invariant_state
= {
965 .brw
= BRW_NEW_BLORP
|
968 .emit
= brw_upload_invariant_state
972 * Define the base addresses which some state is referenced from.
974 * This allows us to avoid having to emit relocations for the objects,
975 * and is actually required for binding table pointers on gen6.
977 * Surface state base address covers binding table pointers and
978 * surface state objects, but not the surfaces that the surface state
982 brw_upload_state_base_address(struct brw_context
*brw
)
984 if (brw
->batch
.state_base_address_emitted
)
987 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
988 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
989 * programmed prior to STATE_BASE_ADDRESS.
991 * However, given that the instruction SBA (general state base
992 * address) on this chipset is always set to 0 across X and GL,
993 * maybe this isn't required for us in particular.
997 uint32_t mocs_wb
= brw
->gen
>= 9 ? SKL_MOCS_WB
: BDW_MOCS_WB
;
998 int pkt_len
= brw
->gen
>= 9 ? 19 : 16;
1000 BEGIN_BATCH(pkt_len
);
1001 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (pkt_len
- 2));
1002 /* General state base address: stateless DP read/write requests */
1003 OUT_BATCH(mocs_wb
<< 4 | 1);
1005 OUT_BATCH(mocs_wb
<< 16);
1006 /* Surface state base address: */
1007 OUT_RELOC64(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1009 /* Dynamic state base address: */
1010 OUT_RELOC64(brw
->batch
.bo
,
1011 I915_GEM_DOMAIN_RENDER
| I915_GEM_DOMAIN_INSTRUCTION
, 0,
1013 /* Indirect object base address: MEDIA_OBJECT data */
1014 OUT_BATCH(mocs_wb
<< 4 | 1);
1016 /* Instruction base address: shader kernels (incl. SIP) */
1017 OUT_RELOC64(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1020 /* General state buffer size */
1021 OUT_BATCH(0xfffff001);
1022 /* Dynamic state buffer size */
1023 OUT_BATCH(ALIGN(brw
->batch
.bo
->size
, 4096) | 1);
1024 /* Indirect object upper bound */
1025 OUT_BATCH(0xfffff001);
1026 /* Instruction access upper bound */
1027 OUT_BATCH(ALIGN(brw
->cache
.bo
->size
, 4096) | 1);
1028 if (brw
->gen
>= 9) {
1034 } else if (brw
->gen
>= 6) {
1035 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
1038 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
1039 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
1040 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
1041 1); /* General State Base Address Modify Enable */
1042 /* Surface state base address:
1043 * BINDING_TABLE_STATE
1046 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
1047 /* Dynamic state base address:
1049 * SAMPLER_BORDER_COLOR_STATE
1050 * CLIP, SF, WM/CC viewport state
1052 * DEPTH_STENCIL_STATE
1054 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
1055 * Disable is clear, which we rely on)
1057 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
1058 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
1060 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
1061 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1062 1); /* Instruction base address: shader kernels (incl. SIP) */
1064 OUT_BATCH(1); /* General state upper bound */
1065 /* Dynamic state upper bound. Although the documentation says that
1066 * programming it to zero will cause it to be ignored, that is a lie.
1067 * If this isn't programmed to a real bound, the sampler border color
1068 * pointer is rejected, causing border color to mysteriously fail.
1070 OUT_BATCH(0xfffff001);
1071 OUT_BATCH(1); /* Indirect object upper bound */
1072 OUT_BATCH(1); /* Instruction access upper bound */
1074 } else if (brw
->gen
== 5) {
1076 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
1077 OUT_BATCH(1); /* General state base address */
1078 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1079 1); /* Surface state base address */
1080 OUT_BATCH(1); /* Indirect object base address */
1081 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
1082 1); /* Instruction base address */
1083 OUT_BATCH(0xfffff001); /* General state upper bound */
1084 OUT_BATCH(1); /* Indirect object upper bound */
1085 OUT_BATCH(1); /* Instruction access upper bound */
1089 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
1090 OUT_BATCH(1); /* General state base address */
1091 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1092 1); /* Surface state base address */
1093 OUT_BATCH(1); /* Indirect object base address */
1094 OUT_BATCH(1); /* General state upper bound */
1095 OUT_BATCH(1); /* Indirect object upper bound */
1099 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1100 * STATE_BASE_ADDRESS updates require a reissue of:
1102 * 3DSTATE_PIPELINE_POINTERS
1103 * 3DSTATE_BINDING_TABLE_POINTERS
1104 * MEDIA_STATE_POINTERS
1106 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1107 * 1 part 1 says that the folowing packets must be reissued:
1109 * 3DSTATE_CC_POINTERS
1110 * 3DSTATE_BINDING_TABLE_POINTERS
1111 * 3DSTATE_SAMPLER_STATE_POINTERS
1112 * 3DSTATE_VIEWPORT_STATE_POINTERS
1113 * MEDIA_STATE_POINTERS
1115 * Those are always reissued following SBA updates anyway (new
1116 * batch time), except in the case of the program cache BO
1117 * changing. Having a separate state flag makes the sequence more
1121 brw
->ctx
.NewDriverState
|= BRW_NEW_STATE_BASE_ADDRESS
;
1122 brw
->batch
.state_base_address_emitted
= true;