src/mesa/drivers/dri/i965/brw_nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_nir.h"
  25 #include "brw_shader.h"
  26 #include "glsl/glsl_parser_extras.h"
  27 #include "glsl/nir/glsl_to_nir.h"
  28 #include "program/prog_to_nir.h"
  29
  30 static bool
  31 remap_vs_attrs(nir_block *block, void *closure)
  32 {
  33    GLbitfield64 inputs_read = *((GLbitfield64 *) closure);
  34
  35    nir_foreach_instr(block, instr) {
  36       if (instr->type != nir_instr_type_intrinsic)
  37          continue;
  38
  39       nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
  40
  41       /* We set EmitNoIndirect for VS inputs, so there are no indirects. */
  42       assert(intrin->intrinsic != nir_intrinsic_load_input_indirect);
  43
  44       if (intrin->intrinsic == nir_intrinsic_load_input) {
  45          /* Attributes come in a contiguous block, ordered by their
  46           * gl_vert_attrib value.  That means we can compute the slot
  47           * number for an attribute by masking out the enabled attributes
  48           * before it and counting the bits.
  49           */
  50          int attr = intrin->const_index[0];
  51          int slot = _mesa_bitcount_64(inputs_read & BITFIELD64_MASK(attr));
  52          intrin->const_index[0] = 4 * slot;
  53       }
  54    }
  55    return true;
  56 }
  57
  58 static void
  59 brw_nir_lower_inputs(nir_shader *nir, bool is_scalar)
  60 {
  61    switch (nir->stage) {
  62    case MESA_SHADER_VERTEX:
  63       /* For now, leave the vec4 backend doing the old method. */
  64       if (!is_scalar) {
  65          nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
  66                                   type_size_vec4);
  67          break;
  68       }
  69
  70       /* Start with the location of the variable's base. */
  71       foreach_list_typed(nir_variable, var, node, &nir->inputs) {
  72          var->data.driver_location = var->data.location;
  73       }
  74
  75       /* Now use nir_lower_io to walk dereference chains.  Attribute arrays
  76        * are loaded as one vec4 per element (or matrix column), so we use
  77        * type_size_vec4 here.
  78        */
  79       nir_lower_io(nir, nir_var_shader_in, type_size_vec4);
  80
  81       /* Finally, translate VERT_ATTRIB_* values into the actual registers.
  82        *
  83        * Note that we can use nir->info.inputs_read instead of key->inputs_read
  84        * since the two are identical aside from Gen4-5 edge flag differences.
  85        */
  86       GLbitfield64 inputs_read = nir->info.inputs_read;
  87       nir_foreach_overload(nir, overload) {
  88          if (overload->impl) {
  89             nir_foreach_block(overload->impl, remap_vs_attrs, &inputs_read);
  90          }
  91       }
  92       break;
  93    case MESA_SHADER_GEOMETRY:
  94       foreach_list_typed(nir_variable, var, node, &nir->inputs) {
  95          var->data.driver_location = var->data.location;
  96       }
  97       break;
  98    case MESA_SHADER_FRAGMENT:
  99       assert(is_scalar);
 100       nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
 101                                type_size_scalar);
 102       break;
 103    case MESA_SHADER_COMPUTE:
 104       /* Compute shaders have no inputs. */
 105       assert(exec_list_is_empty(&nir->inputs));
 106       break;
 107    default:
 108       unreachable("unsupported shader stage");
 109    }
 110 }
 111
 112 static void
 113 brw_nir_lower_outputs(nir_shader *nir, bool is_scalar)
 114 {
 115    switch (nir->stage) {
 116    case MESA_SHADER_VERTEX:
 117    case MESA_SHADER_GEOMETRY:
 118       if (is_scalar) {
 119          nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 120                                   type_size_scalar);
 121       } else {
 122          nir_foreach_variable(var, &nir->outputs)
 123             var->data.driver_location = var->data.location;
 124       }
 125       break;
 126    case MESA_SHADER_FRAGMENT:
 127       nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
 128                                type_size_scalar);
 129       break;
 130    case MESA_SHADER_COMPUTE:
 131       /* Compute shaders have no outputs. */
 132       assert(exec_list_is_empty(&nir->outputs));
 133       break;
 134    default:
 135       unreachable("unsupported shader stage");
 136    }
 137 }
 138
 139 static void
 140 nir_optimize(nir_shader *nir, bool is_scalar)
 141 {
 142    bool progress;
 143    do {
 144       progress = false;
 145       nir_lower_vars_to_ssa(nir);
 146       nir_validate_shader(nir);
 147
 148       if (is_scalar) {
 149          nir_lower_alu_to_scalar(nir);
 150          nir_validate_shader(nir);
 151       }
 152
 153       progress |= nir_copy_prop(nir);
 154       nir_validate_shader(nir);
 155
 156       if (is_scalar) {
 157          nir_lower_phis_to_scalar(nir);
 158          nir_validate_shader(nir);
 159       }
 160
 161       progress |= nir_copy_prop(nir);
 162       nir_validate_shader(nir);
 163       progress |= nir_opt_dce(nir);
 164       nir_validate_shader(nir);
 165       progress |= nir_opt_cse(nir);
 166       nir_validate_shader(nir);
 167       progress |= nir_opt_peephole_select(nir);
 168       nir_validate_shader(nir);
 169       progress |= nir_opt_algebraic(nir);
 170       nir_validate_shader(nir);
 171       progress |= nir_opt_constant_folding(nir);
 172       nir_validate_shader(nir);
 173       progress |= nir_opt_dead_cf(nir);
 174       nir_validate_shader(nir);
 175       progress |= nir_opt_remove_phis(nir);
 176       nir_validate_shader(nir);
 177       progress |= nir_opt_undef(nir);
 178       nir_validate_shader(nir);
 179    } while (progress);
 180 }
 181
 182 nir_shader *
 183 brw_create_nir(struct brw_context *brw,
 184                const struct gl_shader_program *shader_prog,
 185                const struct gl_program *prog,
 186                gl_shader_stage stage,
 187                bool is_scalar)
 188 {
 189    struct gl_context *ctx = &brw->ctx;
 190    const nir_shader_compiler_options *options =
 191       ctx->Const.ShaderCompilerOptions[stage].NirOptions;
 192    nir_shader *nir;
 193
 194    /* First, lower the GLSL IR or Mesa IR to NIR */
 195    if (shader_prog) {
 196       nir = glsl_to_nir(shader_prog, stage, options);
 197    } else {
 198       nir = prog_to_nir(prog, options);
 199       nir_convert_to_ssa(nir); /* turn registers into SSA */
 200    }
 201    nir_validate_shader(nir);
 202
 203    brw_process_nir(nir, brw->intelScreen->devinfo, shader_prog, stage, is_scalar);
 204
 205    static GLuint msg_id = 0;
 206    _mesa_gl_debug(&brw->ctx, &msg_id,
 207                   MESA_DEBUG_SOURCE_SHADER_COMPILER,
 208                   MESA_DEBUG_TYPE_OTHER,
 209                   MESA_DEBUG_SEVERITY_NOTIFICATION,
 210                   "%s NIR shader:\n",
 211                   _mesa_shader_stage_to_abbrev(stage));
 212
 213    return nir;
 214 }
 215
 216 void
 217 brw_process_nir(nir_shader *nir,
 218                 const struct brw_device_info *devinfo,
 219                 const struct gl_shader_program *shader_prog,
 220                 gl_shader_stage stage, bool is_scalar)
 221 {
 222    bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 223    static const nir_lower_tex_options tex_options = {
 224       .lower_txp = ~0,
 225    };
 226
 227    if (stage == MESA_SHADER_GEOMETRY) {
 228       nir_lower_gs_intrinsics(nir);
 229       nir_validate_shader(nir);
 230    }
 231
 232    nir_lower_global_vars_to_local(nir);
 233    nir_validate_shader(nir);
 234
 235    nir_lower_tex(nir, &tex_options);
 236    nir_validate_shader(nir);
 237
 238    nir_normalize_cubemap_coords(nir);
 239    nir_validate_shader(nir);
 240
 241    nir_split_var_copies(nir);
 242    nir_validate_shader(nir);
 243
 244    nir_optimize(nir, is_scalar);
 245
 246    /* Lower a bunch of stuff */
 247    nir_lower_var_copies(nir);
 248    nir_validate_shader(nir);
 249
 250    /* Get rid of split copies */
 251    nir_optimize(nir, is_scalar);
 252
 253    brw_nir_lower_inputs(nir, is_scalar);
 254    brw_nir_lower_outputs(nir, is_scalar);
 255    nir_assign_var_locations(&nir->uniforms,
 256                             &nir->num_uniforms,
 257                             is_scalar ? type_size_scalar : type_size_vec4);
 258    nir_lower_io(nir, -1, is_scalar ? type_size_scalar : type_size_vec4);
 259    nir_validate_shader(nir);
 260
 261    nir_remove_dead_variables(nir);
 262    nir_validate_shader(nir);
 263
 264    if (shader_prog) {
 265       nir_lower_samplers(nir, shader_prog);
 266       nir_validate_shader(nir);
 267    }
 268
 269    nir_lower_system_values(nir);
 270    nir_validate_shader(nir);
 271
 272    nir_lower_atomics(nir);
 273    nir_validate_shader(nir);
 274
 275    nir_optimize(nir, is_scalar);
 276
 277    if (devinfo->gen >= 6) {
 278       /* Try and fuse multiply-adds */
 279       nir_opt_peephole_ffma(nir);
 280       nir_validate_shader(nir);
 281    }
 282
 283    nir_opt_algebraic_late(nir);
 284    nir_validate_shader(nir);
 285
 286    nir_lower_locals_to_regs(nir);
 287    nir_validate_shader(nir);
 288
 289    nir_lower_to_source_mods(nir);
 290    nir_validate_shader(nir);
 291    nir_copy_prop(nir);
 292    nir_validate_shader(nir);
 293    nir_opt_dce(nir);
 294    nir_validate_shader(nir);
 295
 296    if (unlikely(debug_enabled)) {
 297       /* Re-index SSA defs so we print more sensible numbers. */
 298       nir_foreach_overload(nir, overload) {
 299          if (overload->impl)
 300             nir_index_ssa_defs(overload->impl);
 301       }
 302
 303       fprintf(stderr, "NIR (SSA form) for %s shader:\n",
 304               _mesa_shader_stage_to_string(stage));
 305       nir_print_shader(nir, stderr);
 306    }
 307
 308    nir_convert_from_ssa(nir, true);
 309    nir_validate_shader(nir);
 310
 311    if (!is_scalar) {
 312       nir_move_vec_src_uses_to_dest(nir);
 313       nir_validate_shader(nir);
 314
 315       nir_lower_vec_to_movs(nir);
 316       nir_validate_shader(nir);
 317    }
 318
 319    /* This is the last pass we run before we start emitting stuff.  It
 320     * determines when we need to insert boolean resolves on Gen <= 5.  We
 321     * run it last because it stashes data in instr->pass_flags and we don't
 322     * want that to be squashed by other NIR passes.
 323     */
 324    if (devinfo->gen <= 5)
 325       brw_nir_analyze_boolean_resolves(nir);
 326
 327    nir_sweep(nir);
 328
 329    if (unlikely(debug_enabled)) {
 330       fprintf(stderr, "NIR (final form) for %s shader:\n",
 331               _mesa_shader_stage_to_string(stage));
 332       nir_print_shader(nir, stderr);
 333    }
 334 }
 335
 336 enum brw_reg_type
 337 brw_type_for_nir_type(nir_alu_type type)
 338 {
 339    switch (type) {
 340    case nir_type_unsigned:
 341       return BRW_REGISTER_TYPE_UD;
 342    case nir_type_bool:
 343    case nir_type_int:
 344       return BRW_REGISTER_TYPE_D;
 345    case nir_type_float:
 346       return BRW_REGISTER_TYPE_F;
 347    default:
 348       unreachable("unknown type");
 349    }
 350
 351    return BRW_REGISTER_TYPE_F;
 352 }
 353
 354 /* Returns the glsl_base_type corresponding to a nir_alu_type.
 355  * This is used by both brw_vec4_nir and brw_fs_nir.
 356  */
 357 enum glsl_base_type
 358 brw_glsl_base_type_for_nir_type(nir_alu_type type)
 359 {
 360    switch (type) {
 361    case nir_type_float:
 362       return GLSL_TYPE_FLOAT;
 363
 364    case nir_type_int:
 365       return GLSL_TYPE_INT;
 366
 367    case nir_type_unsigned:
 368       return GLSL_TYPE_UINT;
 369
 370    default:
 371       unreachable("bad type");
 372    }
 373 }