src/mesa/drivers/dri/i965/brw_optimize.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "main/macros.h"
  29 #include "shader/program.h"
  30 #include "shader/prog_parameter.h"
  31 #include "shader/prog_print.h"
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "brw_eu.h"
  35
  36 static GLboolean
  37 is_single_channel_dp4(struct brw_instruction *insn)
  38 {
  39    if (insn->header.opcode != BRW_OPCODE_DP4 ||
  40        insn->header.execution_size != BRW_EXECUTE_8 ||
  41        insn->header.access_mode != BRW_ALIGN_16 ||
  42        insn->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
  43       return GL_FALSE;
  44
  45    if (!is_power_of_two(insn->bits1.da16.dest_writemask))
  46       return GL_FALSE;
  47
  48    return GL_TRUE;
  49 }
  50
  51 /**
  52  * Sets the dependency control fields on DP4 instructions.
  53  *
  54  * The hardware only tracks dependencies on a register basis, so when
  55  * you do:
  56  *
  57  * DP4 dst.x src1 src2
  58  * DP4 dst.y src1 src3
  59  * DP4 dst.z src1 src4
  60  * DP4 dst.w src1 src5
  61  *
  62  * It will wait to do the DP4 dst.y until the dst.x is resolved, etc.
  63  * We can examine our instruction stream and set the dependency
  64  * control fields to tell the hardware when to do it.
  65  *
  66  * We may want to extend this to other instructions that are used to
  67  * fill in a channel at a time of the destination register.
  68  */
  69 static void
  70 brw_set_dp4_dependency_control(struct brw_compile *p)
  71 {
  72    int i;
  73
  74    for (i = 1; i < p->nr_insn; i++) {
  75       struct brw_instruction *insn = &p->store[i];
  76       struct brw_instruction *prev = &p->store[i - 1];
  77
  78       if (!is_single_channel_dp4(prev))
  79          continue;
  80
  81       if (!is_single_channel_dp4(insn)) {
  82          i++;
  83          continue;
  84       }
  85
  86       /* Only avoid hw dep control if the write masks are different
  87        * channels of one reg.
  88        */
  89       if (insn->bits1.da16.dest_writemask == prev->bits1.da16.dest_writemask)
  90          continue;
  91       if (insn->bits1.da16.dest_reg_nr != prev->bits1.da16.dest_reg_nr)
  92          continue;
  93
  94       /* Check if the second instruction depends on the previous one
  95        * for a src.
  96        */
  97       if (insn->bits1.da1.src0_reg_file == BRW_GENERAL_REGISTER_FILE &&
  98           (insn->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT ||
  99            insn->bits2.da1.src0_reg_nr == insn->bits1.da16.dest_reg_nr))
 100           continue;
 101       if (insn->bits1.da1.src1_reg_file == BRW_GENERAL_REGISTER_FILE &&
 102           (insn->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT ||
 103            insn->bits3.da1.src1_reg_nr == insn->bits1.da16.dest_reg_nr))
 104           continue;
 105
 106       prev->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
 107       insn->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
 108    }
 109 }
 110
 111 void
 112 brw_optimize(struct brw_compile *p)
 113 {
 114    brw_set_dp4_dependency_control(p);
 115 }