Merge commit 'origin/7.8'
[mesa.git] / src / mesa / drivers / dri / i965 / brw_optimize.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "main/macros.h"
29 #include "shader/program.h"
30 #include "shader/prog_print.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_eu.h"
34
35 static GLboolean
36 is_single_channel_dp4(struct brw_instruction *insn)
37 {
38 if (insn->header.opcode != BRW_OPCODE_DP4 ||
39 insn->header.execution_size != BRW_EXECUTE_8 ||
40 insn->header.access_mode != BRW_ALIGN_16 ||
41 insn->bits1.da1.dest_reg_file != BRW_GENERAL_REGISTER_FILE)
42 return GL_FALSE;
43
44 if (!is_power_of_two(insn->bits1.da16.dest_writemask))
45 return GL_FALSE;
46
47 return GL_TRUE;
48 }
49
50 /**
51 * Sets the dependency control fields on DP4 instructions.
52 *
53 * The hardware only tracks dependencies on a register basis, so when
54 * you do:
55 *
56 * DP4 dst.x src1 src2
57 * DP4 dst.y src1 src3
58 * DP4 dst.z src1 src4
59 * DP4 dst.w src1 src5
60 *
61 * It will wait to do the DP4 dst.y until the dst.x is resolved, etc.
62 * We can examine our instruction stream and set the dependency
63 * control fields to tell the hardware when to do it.
64 *
65 * We may want to extend this to other instructions that are used to
66 * fill in a channel at a time of the destination register.
67 */
68 static void
69 brw_set_dp4_dependency_control(struct brw_compile *p)
70 {
71 int i;
72
73 for (i = 1; i < p->nr_insn; i++) {
74 struct brw_instruction *insn = &p->store[i];
75 struct brw_instruction *prev = &p->store[i - 1];
76
77 if (!is_single_channel_dp4(prev))
78 continue;
79
80 if (!is_single_channel_dp4(insn)) {
81 i++;
82 continue;
83 }
84
85 /* Only avoid hw dep control if the write masks are different
86 * channels of one reg.
87 */
88 if (insn->bits1.da16.dest_writemask == prev->bits1.da16.dest_writemask)
89 continue;
90 if (insn->bits1.da16.dest_reg_nr != prev->bits1.da16.dest_reg_nr)
91 continue;
92
93 /* Check if the second instruction depends on the previous one
94 * for a src.
95 */
96 if (insn->bits1.da1.src0_reg_file == BRW_GENERAL_REGISTER_FILE &&
97 (insn->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT ||
98 insn->bits2.da1.src0_reg_nr == insn->bits1.da16.dest_reg_nr))
99 continue;
100 if (insn->bits1.da1.src1_reg_file == BRW_GENERAL_REGISTER_FILE &&
101 (insn->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT ||
102 insn->bits3.da1.src1_reg_nr == insn->bits1.da16.dest_reg_nr))
103 continue;
104
105 prev->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
106 insn->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
107 }
108 }
109
110 void
111 brw_optimize(struct brw_compile *p)
112 {
113 brw_set_dp4_dependency_control(p);
114 }