2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "main/glspirv.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_to_nir.h"
38 #include "program/program.h"
39 #include "program/programopt.h"
41 #include "util/ralloc.h"
42 #include "compiler/glsl/ir.h"
43 #include "compiler/glsl/glsl_to_nir.h"
44 #include "compiler/glsl/float64_glsl.h"
46 #include "brw_program.h"
47 #include "brw_context.h"
48 #include "compiler/brw_nir.h"
49 #include "brw_defines.h"
50 #include "intel_batchbuffer.h"
57 #include "main/shaderapi.h"
58 #include "main/shaderobj.h"
61 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
64 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
65 type_size_scalar_bytes
);
66 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
68 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
69 type_size_vec4_bytes
);
70 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
74 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
75 GLuint id
, bool is_arb_asm
);
78 compile_fp64_funcs(struct gl_context
*ctx
,
79 const nir_shader_compiler_options
*options
,
81 gl_shader_stage stage
)
83 const GLuint name
= ~0;
86 sh
= _mesa_new_shader(name
, stage
);
88 sh
->Source
= float64_source
;
89 sh
->CompileStatus
= COMPILE_FAILURE
;
90 _mesa_compile_shader(ctx
, sh
);
92 if (!sh
->CompileStatus
) {
95 "fp64 software impl compile failed:\n%s\nsource:\n%s\n",
96 sh
->InfoLog
, float64_source
);
100 struct gl_shader_program
*sh_prog
;
101 sh_prog
= _mesa_new_shader_program(name
);
102 sh_prog
->Label
= NULL
;
103 sh_prog
->NumShaders
= 1;
104 sh_prog
->Shaders
= malloc(sizeof(struct gl_shader
*));
105 sh_prog
->Shaders
[0] = sh
;
107 struct gl_linked_shader
*linked
= rzalloc(NULL
, struct gl_linked_shader
);
108 linked
->Stage
= stage
;
111 _mesa_shader_stage_to_program(stage
),
115 sh_prog
->_LinkedShaders
[stage
] = linked
;
117 nir_shader
*nir
= glsl_to_nir(sh_prog
, stage
, options
);
119 return nir_shader_clone(mem_ctx
, nir
);
123 brw_create_nir(struct brw_context
*brw
,
124 const struct gl_shader_program
*shader_prog
,
125 struct gl_program
*prog
,
126 gl_shader_stage stage
,
129 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
130 struct gl_context
*ctx
= &brw
->ctx
;
131 const nir_shader_compiler_options
*options
=
132 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
135 /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
137 if (shader_prog
->data
->spirv
) {
138 nir
= _mesa_spirv_to_nir(ctx
, shader_prog
, stage
, options
);
140 nir
= glsl_to_nir(shader_prog
, stage
, options
);
144 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
145 nir_lower_returns(nir
);
146 nir_validate_shader(nir
, "after glsl_to_nir or spirv_to_nir and "
148 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
149 nir_shader_get_entrypoint(nir
), true, false);
151 nir
= prog_to_nir(prog
, options
);
152 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
154 nir_validate_shader(nir
, "before brw_preprocess_nir");
156 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
158 if (!devinfo
->has_64bit_types
&& nir
->info
.uses_64bit
) {
159 nir_shader
*fp64
= compile_fp64_funcs(ctx
, options
, ralloc_parent(nir
), stage
);
161 nir_validate_shader(fp64
, "fp64");
162 exec_list_append(&nir
->functions
, &fp64
->functions
);
165 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
);
167 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
169 if (stage
== MESA_SHADER_TESS_CTRL
) {
170 /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */
171 static const gl_state_index16 tokens
[STATE_LENGTH
] =
172 { STATE_INTERNAL
, STATE_TCS_PATCH_VERTICES_IN
};
173 nir_lower_patch_vertices(nir
, 0, devinfo
->gen
>= 8 ? tokens
: NULL
);
176 if (stage
== MESA_SHADER_TESS_EVAL
) {
177 /* Lower gl_PatchVerticesIn to a constant if we have a TCS, or
178 * a uniform if we don't.
180 struct gl_linked_shader
*tcs
=
181 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
];
182 uint32_t static_patch_vertices
=
183 tcs
? tcs
->Program
->nir
->info
.tess
.tcs_vertices_out
: 0;
184 static const gl_state_index16 tokens
[STATE_LENGTH
] =
185 { STATE_INTERNAL
, STATE_TES_PATCH_VERTICES_IN
};
186 nir_lower_patch_vertices(nir
, static_patch_vertices
, tokens
);
189 if (stage
== MESA_SHADER_FRAGMENT
) {
190 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
191 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
192 .fs_coord_pixel_center_integer
= 1,
193 .fs_coord_origin_upper_left
= 1,
196 bool progress
= false;
197 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
199 _mesa_add_state_reference(prog
->Parameters
,
200 wpos_options
.state_tokens
);
204 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
210 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
212 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
214 /* Copy the info we just generated back into the gl_program */
215 const char *prog_name
= prog
->info
.name
;
216 const char *prog_label
= prog
->info
.label
;
217 prog
->info
= nir
->info
;
218 prog
->info
.name
= prog_name
;
219 prog
->info
.label
= prog_label
;
223 get_new_program_id(struct intel_screen
*screen
)
225 return p_atomic_inc_return(&screen
->program_id
);
228 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
229 GLuint id
, bool is_arb_asm
)
231 struct brw_context
*brw
= brw_context(ctx
);
232 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
235 prog
->id
= get_new_program_id(brw
->screen
);
237 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
243 static void brwDeleteProgram( struct gl_context
*ctx
,
244 struct gl_program
*prog
)
246 struct brw_context
*brw
= brw_context(ctx
);
248 /* Beware! prog's refcount has reached zero, and it's about to be freed.
250 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
251 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
252 * pointer has changed.
254 * We cannot leave brw->programs[i] as a dangling pointer to the dead
255 * program. malloc() may allocate the same memory for a new gl_program,
256 * causing us to see matching pointers...but totally different programs.
258 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
259 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
260 * would cause us to see matching pointers (NULL == NULL), and fail to
261 * detect that a program has changed since our last draw.
263 * So, set it to a bogus gl_program pointer that will never match,
264 * causing us to properly reevaluate the state on our next draw.
266 * Getting this wrong causes heisenbugs which are very hard to catch,
267 * as you need a very specific allocation pattern to hit the problem.
269 static const struct gl_program deleted_program
;
271 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
272 if (brw
->programs
[i
] == prog
)
273 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
276 _mesa_delete_program( ctx
, prog
);
281 brwProgramStringNotify(struct gl_context
*ctx
,
283 struct gl_program
*prog
)
285 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
287 struct brw_context
*brw
= brw_context(ctx
);
288 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
291 case GL_FRAGMENT_PROGRAM_ARB
: {
292 struct brw_program
*newFP
= brw_program(prog
);
293 const struct brw_program
*curFP
=
294 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
297 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
298 newFP
->id
= get_new_program_id(brw
->screen
);
300 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
302 brw_shader_gather_info(prog
->nir
, prog
);
304 brw_fs_precompile(ctx
, prog
);
307 case GL_VERTEX_PROGRAM_ARB
: {
308 struct brw_program
*newVP
= brw_program(prog
);
309 const struct brw_program
*curVP
=
310 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
313 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
314 if (newVP
->program
.arb
.IsPositionInvariant
) {
315 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
317 newVP
->id
= get_new_program_id(brw
->screen
);
319 /* Also tell tnl about it:
321 _tnl_program_string(ctx
, target
, prog
);
323 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
324 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
326 brw_shader_gather_info(prog
->nir
, prog
);
328 brw_vs_precompile(ctx
, prog
);
333 * driver->ProgramStringNotify is only called for ARB programs, fixed
334 * function vertex programs, and ir_to_mesa (which isn't used by the
335 * i965 back-end). Therefore, even after geometry shaders are added,
336 * this function should only ever be called with a target of
337 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
339 unreachable("Unexpected target in brwProgramStringNotify");
346 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
348 struct brw_context
*brw
= brw_context(ctx
);
349 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
350 unsigned bits
= PIPE_CONTROL_DATA_CACHE_FLUSH
| PIPE_CONTROL_CS_STALL
;
351 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 11);
353 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
354 GL_ELEMENT_ARRAY_BARRIER_BIT
|
355 GL_COMMAND_BARRIER_BIT
))
356 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
358 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
359 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
360 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
362 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
363 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
365 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
366 GL_PIXEL_BUFFER_BARRIER_BIT
))
367 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
368 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
370 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
371 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
372 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
374 /* Typed surface messages are handled by the render cache on IVB, so we
375 * need to flush it too.
377 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
378 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
380 brw_emit_pipe_control_flush(brw
, bits
);
384 brw_framebuffer_fetch_barrier(struct gl_context
*ctx
)
386 struct brw_context
*brw
= brw_context(ctx
);
387 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
389 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
) {
390 if (devinfo
->gen
>= 6) {
391 brw_emit_pipe_control_flush(brw
,
392 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
393 PIPE_CONTROL_CS_STALL
);
394 brw_emit_pipe_control_flush(brw
,
395 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
397 brw_emit_pipe_control_flush(brw
,
398 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
404 brw_get_scratch_bo(struct brw_context
*brw
,
405 struct brw_bo
**scratch_bo
, int size
)
407 struct brw_bo
*old_bo
= *scratch_bo
;
409 if (old_bo
&& old_bo
->size
< size
) {
410 brw_bo_unreference(old_bo
);
416 brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, BRW_MEMZONE_SCRATCH
);
421 * Reserve enough scratch space for the given stage to hold \p per_thread_size
422 * bytes times the given \p thread_count.
425 brw_alloc_stage_scratch(struct brw_context
*brw
,
426 struct brw_stage_state
*stage_state
,
427 unsigned per_thread_size
)
429 if (stage_state
->per_thread_scratch
>= per_thread_size
)
432 stage_state
->per_thread_scratch
= per_thread_size
;
434 if (stage_state
->scratch_bo
)
435 brw_bo_unreference(stage_state
->scratch_bo
);
437 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
438 unsigned thread_count
;
439 switch(stage_state
->stage
) {
440 case MESA_SHADER_VERTEX
:
441 thread_count
= devinfo
->max_vs_threads
;
443 case MESA_SHADER_TESS_CTRL
:
444 thread_count
= devinfo
->max_tcs_threads
;
446 case MESA_SHADER_TESS_EVAL
:
447 thread_count
= devinfo
->max_tes_threads
;
449 case MESA_SHADER_GEOMETRY
:
450 thread_count
= devinfo
->max_gs_threads
;
452 case MESA_SHADER_FRAGMENT
:
453 thread_count
= devinfo
->max_wm_threads
;
455 case MESA_SHADER_COMPUTE
: {
456 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
458 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
460 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
461 * allocate scratch space enough so that each slice has 4 slices
464 * According to the other driver team, this applies to compute shaders
465 * as well. This is not currently documented at all.
467 * brw->screen->subslice_total is the TOTAL number of subslices
468 * and we wish to view that there are 4 subslices per slice
469 * instead of the actual number of subslices per slice.
471 if (devinfo
->gen
>= 9 && devinfo
->gen
< 11)
472 subslices
= 4 * brw
->screen
->devinfo
.num_slices
;
474 unsigned scratch_ids_per_subslice
;
475 if (devinfo
->is_haswell
) {
476 /* WaCSScratchSize:hsw
478 * Haswell's scratch space address calculation appears to be sparse
479 * rather than tightly packed. The Thread ID has bits indicating
480 * which subslice, EU within a subslice, and thread within an EU it
481 * is. There's a maximum of two slices and two subslices, so these
482 * can be stored with a single bit. Even though there are only 10 EUs
483 * per subslice, this is stored in 4 bits, so there's an effective
484 * maximum value of 16 EUs. Similarly, although there are only 7
485 * threads per EU, this is stored in a 3 bit number, giving an
486 * effective maximum value of 8 threads per EU.
488 * This means that we need to use 16 * 8 instead of 10 * 7 for the
489 * number of threads per subslice.
491 scratch_ids_per_subslice
= 16 * 8;
492 } else if (devinfo
->is_cherryview
) {
493 /* Cherryview devices have either 6 or 8 EUs per subslice, and each
494 * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
495 * as if it had 8 EUs.
497 scratch_ids_per_subslice
= 8 * 7;
499 scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
502 thread_count
= scratch_ids_per_subslice
* subslices
;
506 unreachable("Unsupported stage!");
509 stage_state
->scratch_bo
=
510 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
511 per_thread_size
* thread_count
, BRW_MEMZONE_SCRATCH
);
514 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
516 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
518 functions
->NewProgram
= brwNewProgram
;
519 functions
->DeleteProgram
= brwDeleteProgram
;
520 functions
->ProgramStringNotify
= brwProgramStringNotify
;
522 functions
->LinkShader
= brw_link_shader
;
524 functions
->MemoryBarrier
= brw_memory_barrier
;
525 functions
->FramebufferFetchBarrier
= brw_framebuffer_fetch_barrier
;
528 struct shader_times
{
535 brw_init_shader_time(struct brw_context
*brw
)
537 const int max_entries
= 2048;
538 brw
->shader_time
.bo
=
539 brw_bo_alloc(brw
->bufmgr
, "shader time",
540 max_entries
* BRW_SHADER_TIME_STRIDE
* 3,
542 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
543 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
544 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
546 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
548 brw
->shader_time
.max_entries
= max_entries
;
552 compare_time(const void *a
, const void *b
)
554 uint64_t * const *a_val
= a
;
555 uint64_t * const *b_val
= b
;
557 /* We don't just subtract because we're turning the value to an int. */
558 if (**a_val
< **b_val
)
560 else if (**a_val
== **b_val
)
567 print_shader_time_line(const char *stage
, const char *name
,
568 int shader_num
, uint64_t time
, uint64_t total
)
570 fprintf(stderr
, "%-6s%-18s", stage
, name
);
573 fprintf(stderr
, "%4d: ", shader_num
);
575 fprintf(stderr
, " : ");
577 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
579 (double)time
/ 1000000000.0,
580 (double)time
/ total
* 100.0);
584 brw_report_shader_time(struct brw_context
*brw
)
586 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
589 uint64_t scaled
[brw
->shader_time
.num_entries
];
590 uint64_t *sorted
[brw
->shader_time
.num_entries
];
591 uint64_t total_by_type
[ST_CS
+ 1];
592 memset(total_by_type
, 0, sizeof(total_by_type
));
594 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
595 uint64_t written
= 0, reset
= 0;
596 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
598 sorted
[i
] = &scaled
[i
];
609 written
= brw
->shader_time
.cumulative
[i
].written
;
610 reset
= brw
->shader_time
.cumulative
[i
].reset
;
614 /* I sometimes want to print things that aren't the 3 shader times.
615 * Just print the sum in that case.
622 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
624 scaled
[i
] = time
/ written
* (written
+ reset
);
638 total_by_type
[type
] += scaled
[i
];
648 fprintf(stderr
, "No shader time collected yet\n");
652 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
654 fprintf(stderr
, "\n");
655 fprintf(stderr
, "type ID cycles spent %% of total\n");
656 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
658 /* Work back from the sorted pointers times to a time to print. */
659 int i
= sorted
[s
] - scaled
;
664 int shader_num
= brw
->shader_time
.ids
[i
];
665 const char *shader_name
= brw
->shader_time
.names
[i
];
667 switch (brw
->shader_time
.types
[i
]) {
697 print_shader_time_line(stage
, shader_name
, shader_num
,
701 fprintf(stderr
, "\n");
702 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
703 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
704 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
705 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
706 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
707 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
708 print_shader_time_line("total", "fs32", 0, total_by_type
[ST_FS32
], total
);
709 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
713 brw_collect_shader_time(struct brw_context
*brw
)
715 if (!brw
->shader_time
.bo
)
718 /* This probably stalls on the last rendering. We could fix that by
719 * delaying reading the reports, but it doesn't look like it's a big
720 * overhead compared to the cost of tracking the time in the first place.
722 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
724 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
725 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
727 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
728 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
729 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
732 /* Zero the BO out to clear it out for our next collection.
734 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
735 brw_bo_unmap(brw
->shader_time
.bo
);
739 brw_collect_and_report_shader_time(struct brw_context
*brw
)
741 brw_collect_shader_time(brw
);
743 if (brw
->shader_time
.report_time
== 0 ||
744 get_time() - brw
->shader_time
.report_time
>= 1.0) {
745 brw_report_shader_time(brw
);
746 brw
->shader_time
.report_time
= get_time();
751 * Chooses an index in the shader_time buffer and sets up tracking information
754 * Note that this holds on to references to the underlying programs, which may
755 * change their lifetimes compared to normal operation.
758 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
759 enum shader_time_shader_type type
, bool is_glsl_sh
)
761 int shader_time_index
= brw
->shader_time
.num_entries
++;
762 assert(shader_time_index
< brw
->shader_time
.max_entries
);
763 brw
->shader_time
.types
[shader_time_index
] = type
;
768 } else if (is_glsl_sh
) {
769 name
= prog
->info
.label
?
770 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
775 brw
->shader_time
.names
[shader_time_index
] = name
;
776 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
778 return shader_time_index
;
782 brw_destroy_shader_time(struct brw_context
*brw
)
784 brw_bo_unreference(brw
->shader_time
.bo
);
785 brw
->shader_time
.bo
= NULL
;
789 brw_stage_prog_data_free(const void *p
)
791 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
793 ralloc_free(prog_data
->param
);
794 ralloc_free(prog_data
->pull_param
);
798 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
800 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
801 stage
, prog
->Id
, stage
);
802 _mesa_print_program(prog
);
806 brw_setup_tex_for_precompile(const struct gen_device_info
*devinfo
,
807 struct brw_sampler_prog_key_data
*tex
,
808 struct gl_program
*prog
)
810 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
811 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
812 for (unsigned i
= 0; i
< sampler_count
; i
++) {
813 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
814 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
816 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
818 /* Color sampler: assume no swizzling. */
819 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
825 * Sets up the starting offsets for the groups of binding table entries
826 * common to all pipeline stages.
828 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
829 * unused but also make sure that addition of small offsets to them will
830 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
833 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
834 const struct gl_program
*prog
,
835 struct brw_stage_prog_data
*stage_prog_data
,
836 uint32_t next_binding_table_offset
)
838 int num_textures
= util_last_bit(prog
->SamplersUsed
);
840 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
841 next_binding_table_offset
+= num_textures
;
843 if (prog
->info
.num_ubos
) {
844 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
845 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
846 next_binding_table_offset
+= prog
->info
.num_ubos
;
848 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
851 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
852 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
853 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
854 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
855 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
857 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
860 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
861 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
862 next_binding_table_offset
++;
864 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
867 if (prog
->info
.uses_texture_gather
) {
868 if (devinfo
->gen
>= 8) {
869 stage_prog_data
->binding_table
.gather_texture_start
=
870 stage_prog_data
->binding_table
.texture_start
;
872 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
873 next_binding_table_offset
+= num_textures
;
876 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
879 if (prog
->info
.num_images
) {
880 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
881 next_binding_table_offset
+= prog
->info
.num_images
;
883 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
886 /* This may or may not be used depending on how the compile goes. */
887 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
888 next_binding_table_offset
++;
890 /* Plane 0 is just the regular texture section */
891 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
893 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
894 next_binding_table_offset
+= num_textures
;
896 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
897 next_binding_table_offset
+= num_textures
;
899 /* Set the binding table size. Some callers may append new entries
900 * and increase this accordingly.
902 stage_prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
904 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
905 return next_binding_table_offset
;
909 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage stage
,
912 static const unsigned stage_offsets
[] = {
913 offsetof(struct brw_vs_prog_key
, program_string_id
),
914 offsetof(struct brw_tcs_prog_key
, program_string_id
),
915 offsetof(struct brw_tes_prog_key
, program_string_id
),
916 offsetof(struct brw_gs_prog_key
, program_string_id
),
917 offsetof(struct brw_wm_prog_key
, program_string_id
),
918 offsetof(struct brw_cs_prog_key
, program_string_id
),
920 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_offsets
));
921 *(unsigned*)((uint8_t*)key
+ stage_offsets
[stage
]) = id
;
925 brw_populate_default_key(const struct gen_device_info
*devinfo
,
926 union brw_any_prog_key
*prog_key
,
927 struct gl_shader_program
*sh_prog
,
928 struct gl_program
*prog
)
930 switch (prog
->info
.stage
) {
931 case MESA_SHADER_VERTEX
:
932 brw_vs_populate_default_key(devinfo
, &prog_key
->vs
, prog
);
934 case MESA_SHADER_TESS_CTRL
:
935 brw_tcs_populate_default_key(devinfo
, &prog_key
->tcs
, sh_prog
, prog
);
937 case MESA_SHADER_TESS_EVAL
:
938 brw_tes_populate_default_key(devinfo
, &prog_key
->tes
, sh_prog
, prog
);
940 case MESA_SHADER_GEOMETRY
:
941 brw_gs_populate_default_key(devinfo
, &prog_key
->gs
, prog
);
943 case MESA_SHADER_FRAGMENT
:
944 brw_wm_populate_default_key(devinfo
, &prog_key
->wm
, prog
);
946 case MESA_SHADER_COMPUTE
:
947 brw_cs_populate_default_key(devinfo
, &prog_key
->cs
, prog
);
950 unreachable("Unsupported stage!");