2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "main/glspirv.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_to_nir.h"
38 #include "program/program.h"
39 #include "program/programopt.h"
41 #include "util/ralloc.h"
42 #include "compiler/glsl/ir.h"
43 #include "compiler/glsl/glsl_to_nir.h"
45 #include "brw_program.h"
46 #include "brw_context.h"
47 #include "compiler/brw_nir.h"
48 #include "brw_defines.h"
49 #include "intel_batchbuffer.h"
57 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
60 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
61 type_size_scalar_bytes
);
62 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
64 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
65 type_size_vec4_bytes
);
66 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
71 brw_create_nir(struct brw_context
*brw
,
72 const struct gl_shader_program
*shader_prog
,
73 struct gl_program
*prog
,
74 gl_shader_stage stage
,
77 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
78 struct gl_context
*ctx
= &brw
->ctx
;
79 const nir_shader_compiler_options
*options
=
80 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
83 /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
85 if (shader_prog
->data
->spirv
) {
86 nir
= _mesa_spirv_to_nir(ctx
, shader_prog
, stage
, options
);
88 nir
= glsl_to_nir(shader_prog
, stage
, options
);
92 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
93 nir_lower_returns(nir
);
94 nir_validate_shader(nir
, "after glsl_to_nir or spirv_to_nir and "
96 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
97 nir_shader_get_entrypoint(nir
), true, false);
99 nir
= prog_to_nir(prog
, options
);
100 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
102 nir_validate_shader(nir
, "before brw_preprocess_nir");
104 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
);
106 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
108 if (stage
== MESA_SHADER_TESS_CTRL
) {
109 /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */
110 static const gl_state_index16 tokens
[STATE_LENGTH
] =
111 { STATE_INTERNAL
, STATE_TCS_PATCH_VERTICES_IN
};
112 nir_lower_patch_vertices(nir
, 0, devinfo
->gen
>= 8 ? tokens
: NULL
);
115 if (stage
== MESA_SHADER_TESS_EVAL
) {
116 /* Lower gl_PatchVerticesIn to a constant if we have a TCS, or
117 * a uniform if we don't.
119 struct gl_linked_shader
*tcs
=
120 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
];
121 uint32_t static_patch_vertices
=
122 tcs
? tcs
->Program
->nir
->info
.tess
.tcs_vertices_out
: 0;
123 static const gl_state_index16 tokens
[STATE_LENGTH
] =
124 { STATE_INTERNAL
, STATE_TES_PATCH_VERTICES_IN
};
125 nir_lower_patch_vertices(nir
, static_patch_vertices
, tokens
);
128 if (stage
== MESA_SHADER_FRAGMENT
) {
129 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
130 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
131 .fs_coord_pixel_center_integer
= 1,
132 .fs_coord_origin_upper_left
= 1,
135 bool progress
= false;
136 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
138 _mesa_add_state_reference(prog
->Parameters
,
139 wpos_options
.state_tokens
);
143 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
149 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
151 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
153 /* Copy the info we just generated back into the gl_program */
154 const char *prog_name
= prog
->info
.name
;
155 const char *prog_label
= prog
->info
.label
;
156 prog
->info
= nir
->info
;
157 prog
->info
.name
= prog_name
;
158 prog
->info
.label
= prog_label
;
162 get_new_program_id(struct intel_screen
*screen
)
164 return p_atomic_inc_return(&screen
->program_id
);
167 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
168 GLuint id
, bool is_arb_asm
)
170 struct brw_context
*brw
= brw_context(ctx
);
171 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
174 prog
->id
= get_new_program_id(brw
->screen
);
176 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
182 static void brwDeleteProgram( struct gl_context
*ctx
,
183 struct gl_program
*prog
)
185 struct brw_context
*brw
= brw_context(ctx
);
187 /* Beware! prog's refcount has reached zero, and it's about to be freed.
189 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
190 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
191 * pointer has changed.
193 * We cannot leave brw->programs[i] as a dangling pointer to the dead
194 * program. malloc() may allocate the same memory for a new gl_program,
195 * causing us to see matching pointers...but totally different programs.
197 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
198 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
199 * would cause us to see matching pointers (NULL == NULL), and fail to
200 * detect that a program has changed since our last draw.
202 * So, set it to a bogus gl_program pointer that will never match,
203 * causing us to properly reevaluate the state on our next draw.
205 * Getting this wrong causes heisenbugs which are very hard to catch,
206 * as you need a very specific allocation pattern to hit the problem.
208 static const struct gl_program deleted_program
;
210 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
211 if (brw
->programs
[i
] == prog
)
212 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
215 _mesa_delete_program( ctx
, prog
);
220 brwProgramStringNotify(struct gl_context
*ctx
,
222 struct gl_program
*prog
)
224 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
226 struct brw_context
*brw
= brw_context(ctx
);
227 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
230 case GL_FRAGMENT_PROGRAM_ARB
: {
231 struct brw_program
*newFP
= brw_program(prog
);
232 const struct brw_program
*curFP
=
233 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
236 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
237 newFP
->id
= get_new_program_id(brw
->screen
);
239 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
241 brw_shader_gather_info(prog
->nir
, prog
);
243 brw_fs_precompile(ctx
, prog
);
246 case GL_VERTEX_PROGRAM_ARB
: {
247 struct brw_program
*newVP
= brw_program(prog
);
248 const struct brw_program
*curVP
=
249 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
252 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
253 if (newVP
->program
.arb
.IsPositionInvariant
) {
254 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
256 newVP
->id
= get_new_program_id(brw
->screen
);
258 /* Also tell tnl about it:
260 _tnl_program_string(ctx
, target
, prog
);
262 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
263 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
265 brw_shader_gather_info(prog
->nir
, prog
);
267 brw_vs_precompile(ctx
, prog
);
272 * driver->ProgramStringNotify is only called for ARB programs, fixed
273 * function vertex programs, and ir_to_mesa (which isn't used by the
274 * i965 back-end). Therefore, even after geometry shaders are added,
275 * this function should only ever be called with a target of
276 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
278 unreachable("Unexpected target in brwProgramStringNotify");
285 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
287 struct brw_context
*brw
= brw_context(ctx
);
288 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
289 unsigned bits
= PIPE_CONTROL_DATA_CACHE_FLUSH
| PIPE_CONTROL_CS_STALL
;
290 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 11);
292 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
293 GL_ELEMENT_ARRAY_BARRIER_BIT
|
294 GL_COMMAND_BARRIER_BIT
))
295 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
297 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
298 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
299 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
301 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
302 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
304 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
305 GL_PIXEL_BUFFER_BARRIER_BIT
))
306 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
307 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
309 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
310 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
311 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
313 /* Typed surface messages are handled by the render cache on IVB, so we
314 * need to flush it too.
316 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
317 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
319 brw_emit_pipe_control_flush(brw
, bits
);
323 brw_framebuffer_fetch_barrier(struct gl_context
*ctx
)
325 struct brw_context
*brw
= brw_context(ctx
);
326 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
328 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
) {
329 if (devinfo
->gen
>= 6) {
330 brw_emit_pipe_control_flush(brw
,
331 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
332 PIPE_CONTROL_CS_STALL
);
333 brw_emit_pipe_control_flush(brw
,
334 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
336 brw_emit_pipe_control_flush(brw
,
337 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
343 brw_get_scratch_bo(struct brw_context
*brw
,
344 struct brw_bo
**scratch_bo
, int size
)
346 struct brw_bo
*old_bo
= *scratch_bo
;
348 if (old_bo
&& old_bo
->size
< size
) {
349 brw_bo_unreference(old_bo
);
355 brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, BRW_MEMZONE_SCRATCH
);
360 * Reserve enough scratch space for the given stage to hold \p per_thread_size
361 * bytes times the given \p thread_count.
364 brw_alloc_stage_scratch(struct brw_context
*brw
,
365 struct brw_stage_state
*stage_state
,
366 unsigned per_thread_size
)
368 if (stage_state
->per_thread_scratch
>= per_thread_size
)
371 stage_state
->per_thread_scratch
= per_thread_size
;
373 if (stage_state
->scratch_bo
)
374 brw_bo_unreference(stage_state
->scratch_bo
);
376 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
377 unsigned thread_count
;
378 switch(stage_state
->stage
) {
379 case MESA_SHADER_VERTEX
:
380 thread_count
= devinfo
->max_vs_threads
;
382 case MESA_SHADER_TESS_CTRL
:
383 thread_count
= devinfo
->max_tcs_threads
;
385 case MESA_SHADER_TESS_EVAL
:
386 thread_count
= devinfo
->max_tes_threads
;
388 case MESA_SHADER_GEOMETRY
:
389 thread_count
= devinfo
->max_gs_threads
;
391 case MESA_SHADER_FRAGMENT
:
392 thread_count
= devinfo
->max_wm_threads
;
394 case MESA_SHADER_COMPUTE
: {
395 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
397 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
399 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
400 * allocate scratch space enough so that each slice has 4 slices
403 * According to the other driver team, this applies to compute shaders
404 * as well. This is not currently documented at all.
406 * brw->screen->subslice_total is the TOTAL number of subslices
407 * and we wish to view that there are 4 subslices per slice
408 * instead of the actual number of subslices per slice.
410 if (devinfo
->gen
>= 9 && devinfo
->gen
< 11)
411 subslices
= 4 * brw
->screen
->devinfo
.num_slices
;
413 unsigned scratch_ids_per_subslice
;
414 if (devinfo
->is_haswell
) {
415 /* WaCSScratchSize:hsw
417 * Haswell's scratch space address calculation appears to be sparse
418 * rather than tightly packed. The Thread ID has bits indicating
419 * which subslice, EU within a subslice, and thread within an EU it
420 * is. There's a maximum of two slices and two subslices, so these
421 * can be stored with a single bit. Even though there are only 10 EUs
422 * per subslice, this is stored in 4 bits, so there's an effective
423 * maximum value of 16 EUs. Similarly, although there are only 7
424 * threads per EU, this is stored in a 3 bit number, giving an
425 * effective maximum value of 8 threads per EU.
427 * This means that we need to use 16 * 8 instead of 10 * 7 for the
428 * number of threads per subslice.
430 scratch_ids_per_subslice
= 16 * 8;
431 } else if (devinfo
->is_cherryview
) {
432 /* Cherryview devices have either 6 or 8 EUs per subslice, and each
433 * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
434 * as if it had 8 EUs.
436 scratch_ids_per_subslice
= 8 * 7;
438 scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
441 thread_count
= scratch_ids_per_subslice
* subslices
;
445 unreachable("Unsupported stage!");
448 stage_state
->scratch_bo
=
449 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
450 per_thread_size
* thread_count
, BRW_MEMZONE_SCRATCH
);
453 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
455 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
457 functions
->NewProgram
= brwNewProgram
;
458 functions
->DeleteProgram
= brwDeleteProgram
;
459 functions
->ProgramStringNotify
= brwProgramStringNotify
;
461 functions
->LinkShader
= brw_link_shader
;
463 functions
->MemoryBarrier
= brw_memory_barrier
;
464 functions
->FramebufferFetchBarrier
= brw_framebuffer_fetch_barrier
;
467 struct shader_times
{
474 brw_init_shader_time(struct brw_context
*brw
)
476 const int max_entries
= 2048;
477 brw
->shader_time
.bo
=
478 brw_bo_alloc(brw
->bufmgr
, "shader time",
479 max_entries
* BRW_SHADER_TIME_STRIDE
* 3,
481 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
482 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
483 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
485 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
487 brw
->shader_time
.max_entries
= max_entries
;
491 compare_time(const void *a
, const void *b
)
493 uint64_t * const *a_val
= a
;
494 uint64_t * const *b_val
= b
;
496 /* We don't just subtract because we're turning the value to an int. */
497 if (**a_val
< **b_val
)
499 else if (**a_val
== **b_val
)
506 print_shader_time_line(const char *stage
, const char *name
,
507 int shader_num
, uint64_t time
, uint64_t total
)
509 fprintf(stderr
, "%-6s%-18s", stage
, name
);
512 fprintf(stderr
, "%4d: ", shader_num
);
514 fprintf(stderr
, " : ");
516 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
518 (double)time
/ 1000000000.0,
519 (double)time
/ total
* 100.0);
523 brw_report_shader_time(struct brw_context
*brw
)
525 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
528 uint64_t scaled
[brw
->shader_time
.num_entries
];
529 uint64_t *sorted
[brw
->shader_time
.num_entries
];
530 uint64_t total_by_type
[ST_CS
+ 1];
531 memset(total_by_type
, 0, sizeof(total_by_type
));
533 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
534 uint64_t written
= 0, reset
= 0;
535 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
537 sorted
[i
] = &scaled
[i
];
548 written
= brw
->shader_time
.cumulative
[i
].written
;
549 reset
= brw
->shader_time
.cumulative
[i
].reset
;
553 /* I sometimes want to print things that aren't the 3 shader times.
554 * Just print the sum in that case.
561 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
563 scaled
[i
] = time
/ written
* (written
+ reset
);
577 total_by_type
[type
] += scaled
[i
];
587 fprintf(stderr
, "No shader time collected yet\n");
591 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
593 fprintf(stderr
, "\n");
594 fprintf(stderr
, "type ID cycles spent %% of total\n");
595 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
597 /* Work back from the sorted pointers times to a time to print. */
598 int i
= sorted
[s
] - scaled
;
603 int shader_num
= brw
->shader_time
.ids
[i
];
604 const char *shader_name
= brw
->shader_time
.names
[i
];
606 switch (brw
->shader_time
.types
[i
]) {
636 print_shader_time_line(stage
, shader_name
, shader_num
,
640 fprintf(stderr
, "\n");
641 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
642 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
643 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
644 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
645 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
646 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
647 print_shader_time_line("total", "fs32", 0, total_by_type
[ST_FS32
], total
);
648 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
652 brw_collect_shader_time(struct brw_context
*brw
)
654 if (!brw
->shader_time
.bo
)
657 /* This probably stalls on the last rendering. We could fix that by
658 * delaying reading the reports, but it doesn't look like it's a big
659 * overhead compared to the cost of tracking the time in the first place.
661 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
663 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
664 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
666 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
667 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
668 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
671 /* Zero the BO out to clear it out for our next collection.
673 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
674 brw_bo_unmap(brw
->shader_time
.bo
);
678 brw_collect_and_report_shader_time(struct brw_context
*brw
)
680 brw_collect_shader_time(brw
);
682 if (brw
->shader_time
.report_time
== 0 ||
683 get_time() - brw
->shader_time
.report_time
>= 1.0) {
684 brw_report_shader_time(brw
);
685 brw
->shader_time
.report_time
= get_time();
690 * Chooses an index in the shader_time buffer and sets up tracking information
693 * Note that this holds on to references to the underlying programs, which may
694 * change their lifetimes compared to normal operation.
697 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
698 enum shader_time_shader_type type
, bool is_glsl_sh
)
700 int shader_time_index
= brw
->shader_time
.num_entries
++;
701 assert(shader_time_index
< brw
->shader_time
.max_entries
);
702 brw
->shader_time
.types
[shader_time_index
] = type
;
707 } else if (is_glsl_sh
) {
708 name
= prog
->info
.label
?
709 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
714 brw
->shader_time
.names
[shader_time_index
] = name
;
715 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
717 return shader_time_index
;
721 brw_destroy_shader_time(struct brw_context
*brw
)
723 brw_bo_unreference(brw
->shader_time
.bo
);
724 brw
->shader_time
.bo
= NULL
;
728 brw_stage_prog_data_free(const void *p
)
730 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
732 ralloc_free(prog_data
->param
);
733 ralloc_free(prog_data
->pull_param
);
737 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
739 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
740 stage
, prog
->Id
, stage
);
741 _mesa_print_program(prog
);
745 brw_setup_tex_for_precompile(const struct gen_device_info
*devinfo
,
746 struct brw_sampler_prog_key_data
*tex
,
747 struct gl_program
*prog
)
749 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
750 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
751 for (unsigned i
= 0; i
< sampler_count
; i
++) {
752 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
753 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
755 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
757 /* Color sampler: assume no swizzling. */
758 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
764 * Sets up the starting offsets for the groups of binding table entries
765 * common to all pipeline stages.
767 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
768 * unused but also make sure that addition of small offsets to them will
769 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
772 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
773 const struct gl_program
*prog
,
774 struct brw_stage_prog_data
*stage_prog_data
,
775 uint32_t next_binding_table_offset
)
777 int num_textures
= util_last_bit(prog
->SamplersUsed
);
779 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
780 next_binding_table_offset
+= num_textures
;
782 if (prog
->info
.num_ubos
) {
783 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
784 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
785 next_binding_table_offset
+= prog
->info
.num_ubos
;
787 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
790 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
791 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
792 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
793 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
794 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
796 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
799 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
800 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
801 next_binding_table_offset
++;
803 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
806 if (prog
->info
.uses_texture_gather
) {
807 if (devinfo
->gen
>= 8) {
808 stage_prog_data
->binding_table
.gather_texture_start
=
809 stage_prog_data
->binding_table
.texture_start
;
811 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
812 next_binding_table_offset
+= num_textures
;
815 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
818 if (prog
->info
.num_images
) {
819 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
820 next_binding_table_offset
+= prog
->info
.num_images
;
822 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
825 /* This may or may not be used depending on how the compile goes. */
826 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
827 next_binding_table_offset
++;
829 /* Plane 0 is just the regular texture section */
830 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
832 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
833 next_binding_table_offset
+= num_textures
;
835 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
836 next_binding_table_offset
+= num_textures
;
838 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
840 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
841 return next_binding_table_offset
;
845 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage stage
,
848 static const unsigned stage_offsets
[] = {
849 offsetof(struct brw_vs_prog_key
, program_string_id
),
850 offsetof(struct brw_tcs_prog_key
, program_string_id
),
851 offsetof(struct brw_tes_prog_key
, program_string_id
),
852 offsetof(struct brw_gs_prog_key
, program_string_id
),
853 offsetof(struct brw_wm_prog_key
, program_string_id
),
854 offsetof(struct brw_cs_prog_key
, program_string_id
),
856 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_offsets
));
857 *(unsigned*)((uint8_t*)key
+ stage_offsets
[stage
]) = id
;
861 brw_populate_default_key(const struct gen_device_info
*devinfo
,
862 union brw_any_prog_key
*prog_key
,
863 struct gl_shader_program
*sh_prog
,
864 struct gl_program
*prog
)
866 switch (prog
->info
.stage
) {
867 case MESA_SHADER_VERTEX
:
868 brw_vs_populate_default_key(devinfo
, &prog_key
->vs
, prog
);
870 case MESA_SHADER_TESS_CTRL
:
871 brw_tcs_populate_default_key(devinfo
, &prog_key
->tcs
, sh_prog
, prog
);
873 case MESA_SHADER_TESS_EVAL
:
874 brw_tes_populate_default_key(devinfo
, &prog_key
->tes
, sh_prog
, prog
);
876 case MESA_SHADER_GEOMETRY
:
877 brw_gs_populate_default_key(devinfo
, &prog_key
->gs
, prog
);
879 case MESA_SHADER_FRAGMENT
:
880 brw_wm_populate_default_key(devinfo
, &prog_key
->wm
, prog
);
882 case MESA_SHADER_COMPUTE
:
883 brw_cs_populate_default_key(devinfo
, &prog_key
->cs
, prog
);
886 unreachable("Unsupported stage!");