2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "main/glspirv.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_to_nir.h"
38 #include "program/program.h"
39 #include "program/programopt.h"
41 #include "util/ralloc.h"
42 #include "compiler/glsl/ir.h"
43 #include "compiler/glsl/program.h"
44 #include "compiler/glsl/gl_nir.h"
45 #include "compiler/glsl/glsl_to_nir.h"
47 #include "brw_program.h"
48 #include "brw_context.h"
49 #include "compiler/brw_nir.h"
50 #include "brw_defines.h"
51 #include "intel_batchbuffer.h"
57 #include "brw_state.h"
59 #include "main/shaderapi.h"
60 #include "main/shaderobj.h"
63 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
66 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
67 type_size_scalar_bytes
);
68 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
70 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
71 type_size_vec4_bytes
);
72 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
76 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
77 GLuint id
, bool is_arb_asm
);
80 brw_create_nir(struct brw_context
*brw
,
81 const struct gl_shader_program
*shader_prog
,
82 struct gl_program
*prog
,
83 gl_shader_stage stage
,
86 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
87 struct gl_context
*ctx
= &brw
->ctx
;
88 const nir_shader_compiler_options
*options
=
89 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
92 /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
94 if (shader_prog
->data
->spirv
) {
95 nir
= _mesa_spirv_to_nir(ctx
, shader_prog
, stage
, options
);
97 nir
= glsl_to_nir(ctx
, shader_prog
, stage
, options
);
101 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
102 nir_validate_shader(nir
, "after glsl_to_nir or spirv_to_nir");
103 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
104 nir_shader_get_entrypoint(nir
), true, false);
106 nir
= prog_to_nir(prog
, options
);
107 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
109 nir_validate_shader(nir
, "before brw_preprocess_nir");
111 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
113 nir_shader
*softfp64
= NULL
;
114 if ((options
->lower_doubles_options
& nir_lower_fp64_full_software
) &&
115 nir
->info
.uses_64bit
) {
116 softfp64
= glsl_float64_funcs_to_nir(ctx
, options
);
117 ralloc_steal(ralloc_parent(nir
), softfp64
);
120 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
, softfp64
);
122 NIR_PASS_V(nir
, gl_nir_lower_samplers
, shader_prog
);
123 prog
->info
.textures_used
= nir
->info
.textures_used
;
124 prog
->info
.textures_used_by_txf
= nir
->info
.textures_used_by_txf
;
126 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
128 NIR_PASS_V(nir
, gl_nir_lower_buffers
, shader_prog
);
129 /* Do a round of constant folding to clean up address calculations */
130 NIR_PASS_V(nir
, nir_opt_constant_folding
);
132 if (stage
== MESA_SHADER_TESS_CTRL
) {
133 /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */
134 static const gl_state_index16 tokens
[STATE_LENGTH
] =
135 { STATE_INTERNAL
, STATE_TCS_PATCH_VERTICES_IN
};
136 nir_lower_patch_vertices(nir
, 0, devinfo
->gen
>= 8 ? tokens
: NULL
);
139 if (stage
== MESA_SHADER_TESS_EVAL
) {
140 /* Lower gl_PatchVerticesIn to a constant if we have a TCS, or
141 * a uniform if we don't.
143 struct gl_linked_shader
*tcs
=
144 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
];
145 uint32_t static_patch_vertices
=
146 tcs
? tcs
->Program
->nir
->info
.tess
.tcs_vertices_out
: 0;
147 static const gl_state_index16 tokens
[STATE_LENGTH
] =
148 { STATE_INTERNAL
, STATE_TES_PATCH_VERTICES_IN
};
149 nir_lower_patch_vertices(nir
, static_patch_vertices
, tokens
);
152 if (stage
== MESA_SHADER_FRAGMENT
) {
153 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
154 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
155 .fs_coord_pixel_center_integer
= 1,
156 .fs_coord_origin_upper_left
= 1,
159 bool progress
= false;
160 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
162 _mesa_add_state_reference(prog
->Parameters
,
163 wpos_options
.state_tokens
);
167 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
173 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
175 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
177 /* Copy the info we just generated back into the gl_program */
178 const char *prog_name
= prog
->info
.name
;
179 const char *prog_label
= prog
->info
.label
;
180 prog
->info
= nir
->info
;
181 prog
->info
.name
= prog_name
;
182 prog
->info
.label
= prog_label
;
186 get_new_program_id(struct intel_screen
*screen
)
188 return p_atomic_inc_return(&screen
->program_id
);
191 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
192 GLuint id
, bool is_arb_asm
)
194 struct brw_context
*brw
= brw_context(ctx
);
195 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
198 prog
->id
= get_new_program_id(brw
->screen
);
200 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
206 static void brwDeleteProgram( struct gl_context
*ctx
,
207 struct gl_program
*prog
)
209 struct brw_context
*brw
= brw_context(ctx
);
211 /* Beware! prog's refcount has reached zero, and it's about to be freed.
213 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
214 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
215 * pointer has changed.
217 * We cannot leave brw->programs[i] as a dangling pointer to the dead
218 * program. malloc() may allocate the same memory for a new gl_program,
219 * causing us to see matching pointers...but totally different programs.
221 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
222 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
223 * would cause us to see matching pointers (NULL == NULL), and fail to
224 * detect that a program has changed since our last draw.
226 * So, set it to a bogus gl_program pointer that will never match,
227 * causing us to properly reevaluate the state on our next draw.
229 * Getting this wrong causes heisenbugs which are very hard to catch,
230 * as you need a very specific allocation pattern to hit the problem.
232 static const struct gl_program deleted_program
;
234 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
235 if (brw
->programs
[i
] == prog
)
236 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
239 _mesa_delete_program( ctx
, prog
);
244 brwProgramStringNotify(struct gl_context
*ctx
,
246 struct gl_program
*prog
)
248 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
250 struct brw_context
*brw
= brw_context(ctx
);
251 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
254 case GL_FRAGMENT_PROGRAM_ARB
: {
255 struct brw_program
*newFP
= brw_program(prog
);
256 const struct brw_program
*curFP
=
257 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
260 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
261 newFP
->id
= get_new_program_id(brw
->screen
);
263 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
265 brw_shader_gather_info(prog
->nir
, prog
);
267 brw_fs_precompile(ctx
, prog
);
270 case GL_VERTEX_PROGRAM_ARB
: {
271 struct brw_program
*newVP
= brw_program(prog
);
272 const struct brw_program
*curVP
=
273 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
276 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
277 if (newVP
->program
.arb
.IsPositionInvariant
) {
278 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
280 newVP
->id
= get_new_program_id(brw
->screen
);
282 /* Also tell tnl about it:
284 _tnl_program_string(ctx
, target
, prog
);
286 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
287 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
289 brw_shader_gather_info(prog
->nir
, prog
);
291 brw_vs_precompile(ctx
, prog
);
296 * driver->ProgramStringNotify is only called for ARB programs, fixed
297 * function vertex programs, and ir_to_mesa (which isn't used by the
298 * i965 back-end). Therefore, even after geometry shaders are added,
299 * this function should only ever be called with a target of
300 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
302 unreachable("Unexpected target in brwProgramStringNotify");
309 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
311 struct brw_context
*brw
= brw_context(ctx
);
312 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
313 unsigned bits
= PIPE_CONTROL_DATA_CACHE_FLUSH
| PIPE_CONTROL_CS_STALL
;
314 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 11);
316 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
317 GL_ELEMENT_ARRAY_BARRIER_BIT
|
318 GL_COMMAND_BARRIER_BIT
))
319 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
321 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
322 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
323 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
325 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
326 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
328 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
329 GL_PIXEL_BUFFER_BARRIER_BIT
))
330 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
331 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
333 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
334 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
335 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
337 /* Typed surface messages are handled by the render cache on IVB, so we
338 * need to flush it too.
340 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
341 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
343 brw_emit_pipe_control_flush(brw
, bits
);
347 brw_framebuffer_fetch_barrier(struct gl_context
*ctx
)
349 struct brw_context
*brw
= brw_context(ctx
);
350 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
352 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
) {
353 if (devinfo
->gen
>= 6) {
354 brw_emit_pipe_control_flush(brw
,
355 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
356 PIPE_CONTROL_CS_STALL
);
357 brw_emit_pipe_control_flush(brw
,
358 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
360 brw_emit_pipe_control_flush(brw
,
361 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
367 brw_get_scratch_bo(struct brw_context
*brw
,
368 struct brw_bo
**scratch_bo
, int size
)
370 struct brw_bo
*old_bo
= *scratch_bo
;
372 if (old_bo
&& old_bo
->size
< size
) {
373 brw_bo_unreference(old_bo
);
379 brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, BRW_MEMZONE_SCRATCH
);
384 * Reserve enough scratch space for the given stage to hold \p per_thread_size
385 * bytes times the given \p thread_count.
388 brw_alloc_stage_scratch(struct brw_context
*brw
,
389 struct brw_stage_state
*stage_state
,
390 unsigned per_thread_size
)
392 if (stage_state
->per_thread_scratch
>= per_thread_size
)
395 stage_state
->per_thread_scratch
= per_thread_size
;
397 if (stage_state
->scratch_bo
)
398 brw_bo_unreference(stage_state
->scratch_bo
);
400 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
401 unsigned thread_count
;
402 switch(stage_state
->stage
) {
403 case MESA_SHADER_VERTEX
:
404 thread_count
= devinfo
->max_vs_threads
;
406 case MESA_SHADER_TESS_CTRL
:
407 thread_count
= devinfo
->max_tcs_threads
;
409 case MESA_SHADER_TESS_EVAL
:
410 thread_count
= devinfo
->max_tes_threads
;
412 case MESA_SHADER_GEOMETRY
:
413 thread_count
= devinfo
->max_gs_threads
;
415 case MESA_SHADER_FRAGMENT
:
416 thread_count
= devinfo
->max_wm_threads
;
418 case MESA_SHADER_COMPUTE
: {
419 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
421 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
423 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
424 * allocate scratch space enough so that each slice has 4 slices
427 * According to the other driver team, this applies to compute shaders
428 * as well. This is not currently documented at all.
430 * brw->screen->subslice_total is the TOTAL number of subslices
431 * and we wish to view that there are 4 subslices per slice
432 * instead of the actual number of subslices per slice.
434 if (devinfo
->gen
>= 9 && devinfo
->gen
< 11)
435 subslices
= 4 * brw
->screen
->devinfo
.num_slices
;
437 unsigned scratch_ids_per_subslice
;
438 if (devinfo
->is_haswell
) {
439 /* WaCSScratchSize:hsw
441 * Haswell's scratch space address calculation appears to be sparse
442 * rather than tightly packed. The Thread ID has bits indicating
443 * which subslice, EU within a subslice, and thread within an EU it
444 * is. There's a maximum of two slices and two subslices, so these
445 * can be stored with a single bit. Even though there are only 10 EUs
446 * per subslice, this is stored in 4 bits, so there's an effective
447 * maximum value of 16 EUs. Similarly, although there are only 7
448 * threads per EU, this is stored in a 3 bit number, giving an
449 * effective maximum value of 8 threads per EU.
451 * This means that we need to use 16 * 8 instead of 10 * 7 for the
452 * number of threads per subslice.
454 scratch_ids_per_subslice
= 16 * 8;
455 } else if (devinfo
->is_cherryview
) {
456 /* Cherryview devices have either 6 or 8 EUs per subslice, and each
457 * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
458 * as if it had 8 EUs.
460 scratch_ids_per_subslice
= 8 * 7;
462 scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
465 thread_count
= scratch_ids_per_subslice
* subslices
;
469 unreachable("Unsupported stage!");
472 stage_state
->scratch_bo
=
473 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
474 per_thread_size
* thread_count
, BRW_MEMZONE_SCRATCH
);
477 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
479 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
481 functions
->NewProgram
= brwNewProgram
;
482 functions
->DeleteProgram
= brwDeleteProgram
;
483 functions
->ProgramStringNotify
= brwProgramStringNotify
;
485 functions
->LinkShader
= brw_link_shader
;
487 functions
->MemoryBarrier
= brw_memory_barrier
;
488 functions
->FramebufferFetchBarrier
= brw_framebuffer_fetch_barrier
;
491 struct shader_times
{
498 brw_init_shader_time(struct brw_context
*brw
)
500 const int max_entries
= 2048;
501 brw
->shader_time
.bo
=
502 brw_bo_alloc(brw
->bufmgr
, "shader time",
503 max_entries
* BRW_SHADER_TIME_STRIDE
* 3,
505 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
506 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
507 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
509 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
511 brw
->shader_time
.max_entries
= max_entries
;
515 compare_time(const void *a
, const void *b
)
517 uint64_t * const *a_val
= a
;
518 uint64_t * const *b_val
= b
;
520 /* We don't just subtract because we're turning the value to an int. */
521 if (**a_val
< **b_val
)
523 else if (**a_val
== **b_val
)
530 print_shader_time_line(const char *stage
, const char *name
,
531 int shader_num
, uint64_t time
, uint64_t total
)
533 fprintf(stderr
, "%-6s%-18s", stage
, name
);
536 fprintf(stderr
, "%4d: ", shader_num
);
538 fprintf(stderr
, " : ");
540 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
542 (double)time
/ 1000000000.0,
543 (double)time
/ total
* 100.0);
547 brw_report_shader_time(struct brw_context
*brw
)
549 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
552 uint64_t scaled
[brw
->shader_time
.num_entries
];
553 uint64_t *sorted
[brw
->shader_time
.num_entries
];
554 uint64_t total_by_type
[ST_CS
+ 1];
555 memset(total_by_type
, 0, sizeof(total_by_type
));
557 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
558 uint64_t written
= 0, reset
= 0;
559 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
561 sorted
[i
] = &scaled
[i
];
572 written
= brw
->shader_time
.cumulative
[i
].written
;
573 reset
= brw
->shader_time
.cumulative
[i
].reset
;
577 /* I sometimes want to print things that aren't the 3 shader times.
578 * Just print the sum in that case.
585 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
587 scaled
[i
] = time
/ written
* (written
+ reset
);
601 total_by_type
[type
] += scaled
[i
];
611 fprintf(stderr
, "No shader time collected yet\n");
615 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
617 fprintf(stderr
, "\n");
618 fprintf(stderr
, "type ID cycles spent %% of total\n");
619 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
621 /* Work back from the sorted pointers times to a time to print. */
622 int i
= sorted
[s
] - scaled
;
627 int shader_num
= brw
->shader_time
.ids
[i
];
628 const char *shader_name
= brw
->shader_time
.names
[i
];
630 switch (brw
->shader_time
.types
[i
]) {
660 print_shader_time_line(stage
, shader_name
, shader_num
,
664 fprintf(stderr
, "\n");
665 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
666 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
667 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
668 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
669 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
670 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
671 print_shader_time_line("total", "fs32", 0, total_by_type
[ST_FS32
], total
);
672 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
676 brw_collect_shader_time(struct brw_context
*brw
)
678 if (!brw
->shader_time
.bo
)
681 /* This probably stalls on the last rendering. We could fix that by
682 * delaying reading the reports, but it doesn't look like it's a big
683 * overhead compared to the cost of tracking the time in the first place.
685 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
687 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
688 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
690 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
691 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
692 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
695 /* Zero the BO out to clear it out for our next collection.
697 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
698 brw_bo_unmap(brw
->shader_time
.bo
);
702 brw_collect_and_report_shader_time(struct brw_context
*brw
)
704 brw_collect_shader_time(brw
);
706 if (brw
->shader_time
.report_time
== 0 ||
707 get_time() - brw
->shader_time
.report_time
>= 1.0) {
708 brw_report_shader_time(brw
);
709 brw
->shader_time
.report_time
= get_time();
714 * Chooses an index in the shader_time buffer and sets up tracking information
717 * Note that this holds on to references to the underlying programs, which may
718 * change their lifetimes compared to normal operation.
721 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
722 enum shader_time_shader_type type
, bool is_glsl_sh
)
724 int shader_time_index
= brw
->shader_time
.num_entries
++;
725 assert(shader_time_index
< brw
->shader_time
.max_entries
);
726 brw
->shader_time
.types
[shader_time_index
] = type
;
731 } else if (is_glsl_sh
) {
732 name
= prog
->info
.label
?
733 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
738 brw
->shader_time
.names
[shader_time_index
] = name
;
739 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
741 return shader_time_index
;
745 brw_destroy_shader_time(struct brw_context
*brw
)
747 brw_bo_unreference(brw
->shader_time
.bo
);
748 brw
->shader_time
.bo
= NULL
;
752 brw_stage_prog_data_free(const void *p
)
754 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
756 ralloc_free(prog_data
->param
);
757 ralloc_free(prog_data
->pull_param
);
761 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
763 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
764 stage
, prog
->Id
, stage
);
765 _mesa_print_program(prog
);
769 brw_setup_tex_for_precompile(const struct gen_device_info
*devinfo
,
770 struct brw_sampler_prog_key_data
*tex
,
771 struct gl_program
*prog
)
773 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
774 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
775 for (unsigned i
= 0; i
< sampler_count
; i
++) {
776 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
777 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
779 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
781 /* Color sampler: assume no swizzling. */
782 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
788 * Sets up the starting offsets for the groups of binding table entries
789 * common to all pipeline stages.
791 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
792 * unused but also make sure that addition of small offsets to them will
793 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
796 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
797 const struct gl_program
*prog
,
798 struct brw_stage_prog_data
*stage_prog_data
,
799 uint32_t next_binding_table_offset
)
801 int num_textures
= util_last_bit(prog
->SamplersUsed
);
803 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
804 next_binding_table_offset
+= num_textures
;
806 if (prog
->info
.num_ubos
) {
807 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
808 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
809 next_binding_table_offset
+= prog
->info
.num_ubos
;
811 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
814 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
815 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
816 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
817 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
818 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
820 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
823 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
824 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
825 next_binding_table_offset
++;
827 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
830 if (prog
->info
.uses_texture_gather
) {
831 if (devinfo
->gen
>= 8) {
832 stage_prog_data
->binding_table
.gather_texture_start
=
833 stage_prog_data
->binding_table
.texture_start
;
835 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
836 next_binding_table_offset
+= num_textures
;
839 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
842 if (prog
->info
.num_images
) {
843 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
844 next_binding_table_offset
+= prog
->info
.num_images
;
846 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
849 /* This may or may not be used depending on how the compile goes. */
850 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
851 next_binding_table_offset
++;
853 /* Plane 0 is just the regular texture section */
854 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
856 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
857 next_binding_table_offset
+= num_textures
;
859 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
860 next_binding_table_offset
+= num_textures
;
862 /* Set the binding table size. Some callers may append new entries
863 * and increase this accordingly.
865 stage_prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
867 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
868 return next_binding_table_offset
;
872 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage stage
,
875 static const unsigned stage_offsets
[] = {
876 offsetof(struct brw_vs_prog_key
, program_string_id
),
877 offsetof(struct brw_tcs_prog_key
, program_string_id
),
878 offsetof(struct brw_tes_prog_key
, program_string_id
),
879 offsetof(struct brw_gs_prog_key
, program_string_id
),
880 offsetof(struct brw_wm_prog_key
, program_string_id
),
881 offsetof(struct brw_cs_prog_key
, program_string_id
),
883 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_offsets
));
884 *(unsigned*)((uint8_t*)key
+ stage_offsets
[stage
]) = id
;
888 brw_populate_default_key(const struct gen_device_info
*devinfo
,
889 union brw_any_prog_key
*prog_key
,
890 struct gl_shader_program
*sh_prog
,
891 struct gl_program
*prog
)
893 switch (prog
->info
.stage
) {
894 case MESA_SHADER_VERTEX
:
895 brw_vs_populate_default_key(devinfo
, &prog_key
->vs
, prog
);
897 case MESA_SHADER_TESS_CTRL
:
898 brw_tcs_populate_default_key(devinfo
, &prog_key
->tcs
, sh_prog
, prog
);
900 case MESA_SHADER_TESS_EVAL
:
901 brw_tes_populate_default_key(devinfo
, &prog_key
->tes
, sh_prog
, prog
);
903 case MESA_SHADER_GEOMETRY
:
904 brw_gs_populate_default_key(devinfo
, &prog_key
->gs
, prog
);
906 case MESA_SHADER_FRAGMENT
:
907 brw_wm_populate_default_key(devinfo
, &prog_key
->wm
, prog
);
909 case MESA_SHADER_COMPUTE
:
910 brw_cs_populate_default_key(devinfo
, &prog_key
->cs
, prog
);
913 unreachable("Unsupported stage!");
918 brw_debug_recompile(struct brw_context
*brw
,
919 gl_shader_stage stage
,
921 unsigned key_program_string_id
,
924 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
925 enum brw_cache_id cache_id
= brw_stage_cache_id(stage
);
927 compiler
->shader_perf_log(brw
, "Recompiling %s shader for program %d\n",
928 _mesa_shader_stage_to_string(stage
), api_id
);
930 const void *old_key
=
931 brw_find_previous_compile(&brw
->cache
, cache_id
, key_program_string_id
);
933 brw_debug_key_recompile(compiler
, brw
, stage
, old_key
, key
);