2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "main/glspirv.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_to_nir.h"
38 #include "program/program.h"
39 #include "program/programopt.h"
41 #include "util/ralloc.h"
42 #include "compiler/glsl/ir.h"
43 #include "compiler/glsl/program.h"
44 #include "compiler/glsl/gl_nir.h"
45 #include "compiler/glsl/glsl_to_nir.h"
47 #include "brw_program.h"
48 #include "brw_context.h"
49 #include "compiler/brw_nir.h"
50 #include "brw_defines.h"
51 #include "intel_batchbuffer.h"
58 #include "main/shaderapi.h"
59 #include "main/shaderobj.h"
62 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
65 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
66 type_size_scalar_bytes
);
67 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
69 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
70 type_size_vec4_bytes
);
71 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
75 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
76 GLuint id
, bool is_arb_asm
);
79 brw_create_nir(struct brw_context
*brw
,
80 const struct gl_shader_program
*shader_prog
,
81 struct gl_program
*prog
,
82 gl_shader_stage stage
,
85 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
86 struct gl_context
*ctx
= &brw
->ctx
;
87 const nir_shader_compiler_options
*options
=
88 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
91 /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
93 if (shader_prog
->data
->spirv
) {
94 nir
= _mesa_spirv_to_nir(ctx
, shader_prog
, stage
, options
);
96 nir
= glsl_to_nir(ctx
, shader_prog
, stage
, options
);
100 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
101 nir_lower_returns(nir
);
102 nir_validate_shader(nir
, "after glsl_to_nir or spirv_to_nir and "
104 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
105 nir_shader_get_entrypoint(nir
), true, false);
107 nir
= prog_to_nir(prog
, options
);
108 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
109 NIR_PASS_V(nir
, gl_nir_lower_samplers
, NULL
);
111 nir_validate_shader(nir
, "before brw_preprocess_nir");
113 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
115 nir_shader
*softfp64
= NULL
;
116 if ((options
->lower_doubles_options
& nir_lower_fp64_full_software
) &&
117 nir
->info
.uses_64bit
) {
118 softfp64
= glsl_float64_funcs_to_nir(ctx
, options
);
119 ralloc_steal(ralloc_parent(nir
), softfp64
);
122 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
, softfp64
);
124 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
126 if (stage
== MESA_SHADER_TESS_CTRL
) {
127 /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */
128 static const gl_state_index16 tokens
[STATE_LENGTH
] =
129 { STATE_INTERNAL
, STATE_TCS_PATCH_VERTICES_IN
};
130 nir_lower_patch_vertices(nir
, 0, devinfo
->gen
>= 8 ? tokens
: NULL
);
133 if (stage
== MESA_SHADER_TESS_EVAL
) {
134 /* Lower gl_PatchVerticesIn to a constant if we have a TCS, or
135 * a uniform if we don't.
137 struct gl_linked_shader
*tcs
=
138 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
];
139 uint32_t static_patch_vertices
=
140 tcs
? tcs
->Program
->nir
->info
.tess
.tcs_vertices_out
: 0;
141 static const gl_state_index16 tokens
[STATE_LENGTH
] =
142 { STATE_INTERNAL
, STATE_TES_PATCH_VERTICES_IN
};
143 nir_lower_patch_vertices(nir
, static_patch_vertices
, tokens
);
146 if (stage
== MESA_SHADER_FRAGMENT
) {
147 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
148 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
149 .fs_coord_pixel_center_integer
= 1,
150 .fs_coord_origin_upper_left
= 1,
153 bool progress
= false;
154 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
156 _mesa_add_state_reference(prog
->Parameters
,
157 wpos_options
.state_tokens
);
161 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
167 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
169 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
171 /* Copy the info we just generated back into the gl_program */
172 const char *prog_name
= prog
->info
.name
;
173 const char *prog_label
= prog
->info
.label
;
174 prog
->info
= nir
->info
;
175 prog
->info
.name
= prog_name
;
176 prog
->info
.label
= prog_label
;
180 get_new_program_id(struct intel_screen
*screen
)
182 return p_atomic_inc_return(&screen
->program_id
);
185 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
186 GLuint id
, bool is_arb_asm
)
188 struct brw_context
*brw
= brw_context(ctx
);
189 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
192 prog
->id
= get_new_program_id(brw
->screen
);
194 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
200 static void brwDeleteProgram( struct gl_context
*ctx
,
201 struct gl_program
*prog
)
203 struct brw_context
*brw
= brw_context(ctx
);
205 /* Beware! prog's refcount has reached zero, and it's about to be freed.
207 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
208 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
209 * pointer has changed.
211 * We cannot leave brw->programs[i] as a dangling pointer to the dead
212 * program. malloc() may allocate the same memory for a new gl_program,
213 * causing us to see matching pointers...but totally different programs.
215 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
216 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
217 * would cause us to see matching pointers (NULL == NULL), and fail to
218 * detect that a program has changed since our last draw.
220 * So, set it to a bogus gl_program pointer that will never match,
221 * causing us to properly reevaluate the state on our next draw.
223 * Getting this wrong causes heisenbugs which are very hard to catch,
224 * as you need a very specific allocation pattern to hit the problem.
226 static const struct gl_program deleted_program
;
228 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
229 if (brw
->programs
[i
] == prog
)
230 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
233 _mesa_delete_program( ctx
, prog
);
238 brwProgramStringNotify(struct gl_context
*ctx
,
240 struct gl_program
*prog
)
242 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
244 struct brw_context
*brw
= brw_context(ctx
);
245 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
248 case GL_FRAGMENT_PROGRAM_ARB
: {
249 struct brw_program
*newFP
= brw_program(prog
);
250 const struct brw_program
*curFP
=
251 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
254 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
255 newFP
->id
= get_new_program_id(brw
->screen
);
257 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
259 brw_shader_gather_info(prog
->nir
, prog
);
261 brw_fs_precompile(ctx
, prog
);
264 case GL_VERTEX_PROGRAM_ARB
: {
265 struct brw_program
*newVP
= brw_program(prog
);
266 const struct brw_program
*curVP
=
267 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
270 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
271 if (newVP
->program
.arb
.IsPositionInvariant
) {
272 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
274 newVP
->id
= get_new_program_id(brw
->screen
);
276 /* Also tell tnl about it:
278 _tnl_program_string(ctx
, target
, prog
);
280 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
281 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
283 brw_shader_gather_info(prog
->nir
, prog
);
285 brw_vs_precompile(ctx
, prog
);
290 * driver->ProgramStringNotify is only called for ARB programs, fixed
291 * function vertex programs, and ir_to_mesa (which isn't used by the
292 * i965 back-end). Therefore, even after geometry shaders are added,
293 * this function should only ever be called with a target of
294 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
296 unreachable("Unexpected target in brwProgramStringNotify");
303 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
305 struct brw_context
*brw
= brw_context(ctx
);
306 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
307 unsigned bits
= PIPE_CONTROL_DATA_CACHE_FLUSH
| PIPE_CONTROL_CS_STALL
;
308 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 11);
310 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
311 GL_ELEMENT_ARRAY_BARRIER_BIT
|
312 GL_COMMAND_BARRIER_BIT
))
313 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
315 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
316 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
317 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
319 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
320 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
322 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
323 GL_PIXEL_BUFFER_BARRIER_BIT
))
324 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
325 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
327 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
328 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
329 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
331 /* Typed surface messages are handled by the render cache on IVB, so we
332 * need to flush it too.
334 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
335 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
337 brw_emit_pipe_control_flush(brw
, bits
);
341 brw_framebuffer_fetch_barrier(struct gl_context
*ctx
)
343 struct brw_context
*brw
= brw_context(ctx
);
344 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
346 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
) {
347 if (devinfo
->gen
>= 6) {
348 brw_emit_pipe_control_flush(brw
,
349 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
350 PIPE_CONTROL_CS_STALL
);
351 brw_emit_pipe_control_flush(brw
,
352 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
354 brw_emit_pipe_control_flush(brw
,
355 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
361 brw_get_scratch_bo(struct brw_context
*brw
,
362 struct brw_bo
**scratch_bo
, int size
)
364 struct brw_bo
*old_bo
= *scratch_bo
;
366 if (old_bo
&& old_bo
->size
< size
) {
367 brw_bo_unreference(old_bo
);
373 brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, BRW_MEMZONE_SCRATCH
);
378 * Reserve enough scratch space for the given stage to hold \p per_thread_size
379 * bytes times the given \p thread_count.
382 brw_alloc_stage_scratch(struct brw_context
*brw
,
383 struct brw_stage_state
*stage_state
,
384 unsigned per_thread_size
)
386 if (stage_state
->per_thread_scratch
>= per_thread_size
)
389 stage_state
->per_thread_scratch
= per_thread_size
;
391 if (stage_state
->scratch_bo
)
392 brw_bo_unreference(stage_state
->scratch_bo
);
394 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
395 unsigned thread_count
;
396 switch(stage_state
->stage
) {
397 case MESA_SHADER_VERTEX
:
398 thread_count
= devinfo
->max_vs_threads
;
400 case MESA_SHADER_TESS_CTRL
:
401 thread_count
= devinfo
->max_tcs_threads
;
403 case MESA_SHADER_TESS_EVAL
:
404 thread_count
= devinfo
->max_tes_threads
;
406 case MESA_SHADER_GEOMETRY
:
407 thread_count
= devinfo
->max_gs_threads
;
409 case MESA_SHADER_FRAGMENT
:
410 thread_count
= devinfo
->max_wm_threads
;
412 case MESA_SHADER_COMPUTE
: {
413 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
415 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
417 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
418 * allocate scratch space enough so that each slice has 4 slices
421 * According to the other driver team, this applies to compute shaders
422 * as well. This is not currently documented at all.
424 * brw->screen->subslice_total is the TOTAL number of subslices
425 * and we wish to view that there are 4 subslices per slice
426 * instead of the actual number of subslices per slice.
428 if (devinfo
->gen
>= 9 && devinfo
->gen
< 11)
429 subslices
= 4 * brw
->screen
->devinfo
.num_slices
;
431 unsigned scratch_ids_per_subslice
;
432 if (devinfo
->is_haswell
) {
433 /* WaCSScratchSize:hsw
435 * Haswell's scratch space address calculation appears to be sparse
436 * rather than tightly packed. The Thread ID has bits indicating
437 * which subslice, EU within a subslice, and thread within an EU it
438 * is. There's a maximum of two slices and two subslices, so these
439 * can be stored with a single bit. Even though there are only 10 EUs
440 * per subslice, this is stored in 4 bits, so there's an effective
441 * maximum value of 16 EUs. Similarly, although there are only 7
442 * threads per EU, this is stored in a 3 bit number, giving an
443 * effective maximum value of 8 threads per EU.
445 * This means that we need to use 16 * 8 instead of 10 * 7 for the
446 * number of threads per subslice.
448 scratch_ids_per_subslice
= 16 * 8;
449 } else if (devinfo
->is_cherryview
) {
450 /* Cherryview devices have either 6 or 8 EUs per subslice, and each
451 * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
452 * as if it had 8 EUs.
454 scratch_ids_per_subslice
= 8 * 7;
456 scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
459 thread_count
= scratch_ids_per_subslice
* subslices
;
463 unreachable("Unsupported stage!");
466 stage_state
->scratch_bo
=
467 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
468 per_thread_size
* thread_count
, BRW_MEMZONE_SCRATCH
);
471 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
473 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
475 functions
->NewProgram
= brwNewProgram
;
476 functions
->DeleteProgram
= brwDeleteProgram
;
477 functions
->ProgramStringNotify
= brwProgramStringNotify
;
479 functions
->LinkShader
= brw_link_shader
;
481 functions
->MemoryBarrier
= brw_memory_barrier
;
482 functions
->FramebufferFetchBarrier
= brw_framebuffer_fetch_barrier
;
485 struct shader_times
{
492 brw_init_shader_time(struct brw_context
*brw
)
494 const int max_entries
= 2048;
495 brw
->shader_time
.bo
=
496 brw_bo_alloc(brw
->bufmgr
, "shader time",
497 max_entries
* BRW_SHADER_TIME_STRIDE
* 3,
499 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
500 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
501 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
503 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
505 brw
->shader_time
.max_entries
= max_entries
;
509 compare_time(const void *a
, const void *b
)
511 uint64_t * const *a_val
= a
;
512 uint64_t * const *b_val
= b
;
514 /* We don't just subtract because we're turning the value to an int. */
515 if (**a_val
< **b_val
)
517 else if (**a_val
== **b_val
)
524 print_shader_time_line(const char *stage
, const char *name
,
525 int shader_num
, uint64_t time
, uint64_t total
)
527 fprintf(stderr
, "%-6s%-18s", stage
, name
);
530 fprintf(stderr
, "%4d: ", shader_num
);
532 fprintf(stderr
, " : ");
534 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
536 (double)time
/ 1000000000.0,
537 (double)time
/ total
* 100.0);
541 brw_report_shader_time(struct brw_context
*brw
)
543 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
546 uint64_t scaled
[brw
->shader_time
.num_entries
];
547 uint64_t *sorted
[brw
->shader_time
.num_entries
];
548 uint64_t total_by_type
[ST_CS
+ 1];
549 memset(total_by_type
, 0, sizeof(total_by_type
));
551 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
552 uint64_t written
= 0, reset
= 0;
553 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
555 sorted
[i
] = &scaled
[i
];
566 written
= brw
->shader_time
.cumulative
[i
].written
;
567 reset
= brw
->shader_time
.cumulative
[i
].reset
;
571 /* I sometimes want to print things that aren't the 3 shader times.
572 * Just print the sum in that case.
579 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
581 scaled
[i
] = time
/ written
* (written
+ reset
);
595 total_by_type
[type
] += scaled
[i
];
605 fprintf(stderr
, "No shader time collected yet\n");
609 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
611 fprintf(stderr
, "\n");
612 fprintf(stderr
, "type ID cycles spent %% of total\n");
613 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
615 /* Work back from the sorted pointers times to a time to print. */
616 int i
= sorted
[s
] - scaled
;
621 int shader_num
= brw
->shader_time
.ids
[i
];
622 const char *shader_name
= brw
->shader_time
.names
[i
];
624 switch (brw
->shader_time
.types
[i
]) {
654 print_shader_time_line(stage
, shader_name
, shader_num
,
658 fprintf(stderr
, "\n");
659 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
660 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
661 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
662 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
663 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
664 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
665 print_shader_time_line("total", "fs32", 0, total_by_type
[ST_FS32
], total
);
666 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
670 brw_collect_shader_time(struct brw_context
*brw
)
672 if (!brw
->shader_time
.bo
)
675 /* This probably stalls on the last rendering. We could fix that by
676 * delaying reading the reports, but it doesn't look like it's a big
677 * overhead compared to the cost of tracking the time in the first place.
679 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
681 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
682 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
684 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
685 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
686 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
689 /* Zero the BO out to clear it out for our next collection.
691 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
692 brw_bo_unmap(brw
->shader_time
.bo
);
696 brw_collect_and_report_shader_time(struct brw_context
*brw
)
698 brw_collect_shader_time(brw
);
700 if (brw
->shader_time
.report_time
== 0 ||
701 get_time() - brw
->shader_time
.report_time
>= 1.0) {
702 brw_report_shader_time(brw
);
703 brw
->shader_time
.report_time
= get_time();
708 * Chooses an index in the shader_time buffer and sets up tracking information
711 * Note that this holds on to references to the underlying programs, which may
712 * change their lifetimes compared to normal operation.
715 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
716 enum shader_time_shader_type type
, bool is_glsl_sh
)
718 int shader_time_index
= brw
->shader_time
.num_entries
++;
719 assert(shader_time_index
< brw
->shader_time
.max_entries
);
720 brw
->shader_time
.types
[shader_time_index
] = type
;
725 } else if (is_glsl_sh
) {
726 name
= prog
->info
.label
?
727 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
732 brw
->shader_time
.names
[shader_time_index
] = name
;
733 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
735 return shader_time_index
;
739 brw_destroy_shader_time(struct brw_context
*brw
)
741 brw_bo_unreference(brw
->shader_time
.bo
);
742 brw
->shader_time
.bo
= NULL
;
746 brw_stage_prog_data_free(const void *p
)
748 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
750 ralloc_free(prog_data
->param
);
751 ralloc_free(prog_data
->pull_param
);
755 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
757 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
758 stage
, prog
->Id
, stage
);
759 _mesa_print_program(prog
);
763 brw_setup_tex_for_precompile(const struct gen_device_info
*devinfo
,
764 struct brw_sampler_prog_key_data
*tex
,
765 struct gl_program
*prog
)
767 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
768 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
769 for (unsigned i
= 0; i
< sampler_count
; i
++) {
770 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
771 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
773 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
775 /* Color sampler: assume no swizzling. */
776 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
782 * Sets up the starting offsets for the groups of binding table entries
783 * common to all pipeline stages.
785 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
786 * unused but also make sure that addition of small offsets to them will
787 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
790 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
791 const struct gl_program
*prog
,
792 struct brw_stage_prog_data
*stage_prog_data
,
793 uint32_t next_binding_table_offset
)
795 int num_textures
= util_last_bit(prog
->SamplersUsed
);
797 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
798 next_binding_table_offset
+= num_textures
;
800 if (prog
->info
.num_ubos
) {
801 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
802 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
803 next_binding_table_offset
+= prog
->info
.num_ubos
;
805 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
808 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
809 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
810 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
811 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
812 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
814 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
817 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
818 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
819 next_binding_table_offset
++;
821 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
824 if (prog
->info
.uses_texture_gather
) {
825 if (devinfo
->gen
>= 8) {
826 stage_prog_data
->binding_table
.gather_texture_start
=
827 stage_prog_data
->binding_table
.texture_start
;
829 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
830 next_binding_table_offset
+= num_textures
;
833 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
836 if (prog
->info
.num_images
) {
837 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
838 next_binding_table_offset
+= prog
->info
.num_images
;
840 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
843 /* This may or may not be used depending on how the compile goes. */
844 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
845 next_binding_table_offset
++;
847 /* Plane 0 is just the regular texture section */
848 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
850 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
851 next_binding_table_offset
+= num_textures
;
853 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
854 next_binding_table_offset
+= num_textures
;
856 /* Set the binding table size. Some callers may append new entries
857 * and increase this accordingly.
859 stage_prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
861 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
862 return next_binding_table_offset
;
866 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage stage
,
869 static const unsigned stage_offsets
[] = {
870 offsetof(struct brw_vs_prog_key
, program_string_id
),
871 offsetof(struct brw_tcs_prog_key
, program_string_id
),
872 offsetof(struct brw_tes_prog_key
, program_string_id
),
873 offsetof(struct brw_gs_prog_key
, program_string_id
),
874 offsetof(struct brw_wm_prog_key
, program_string_id
),
875 offsetof(struct brw_cs_prog_key
, program_string_id
),
877 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_offsets
));
878 *(unsigned*)((uint8_t*)key
+ stage_offsets
[stage
]) = id
;
882 brw_populate_default_key(const struct gen_device_info
*devinfo
,
883 union brw_any_prog_key
*prog_key
,
884 struct gl_shader_program
*sh_prog
,
885 struct gl_program
*prog
)
887 switch (prog
->info
.stage
) {
888 case MESA_SHADER_VERTEX
:
889 brw_vs_populate_default_key(devinfo
, &prog_key
->vs
, prog
);
891 case MESA_SHADER_TESS_CTRL
:
892 brw_tcs_populate_default_key(devinfo
, &prog_key
->tcs
, sh_prog
, prog
);
894 case MESA_SHADER_TESS_EVAL
:
895 brw_tes_populate_default_key(devinfo
, &prog_key
->tes
, sh_prog
, prog
);
897 case MESA_SHADER_GEOMETRY
:
898 brw_gs_populate_default_key(devinfo
, &prog_key
->gs
, prog
);
900 case MESA_SHADER_FRAGMENT
:
901 brw_wm_populate_default_key(devinfo
, &prog_key
->wm
, prog
);
903 case MESA_SHADER_COMPUTE
:
904 brw_cs_populate_default_key(devinfo
, &prog_key
->cs
, prog
);
907 unreachable("Unsupported stage!");