2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/imports.h"
34 #include "main/glspirv.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_to_nir.h"
38 #include "program/program.h"
39 #include "program/programopt.h"
41 #include "util/ralloc.h"
42 #include "compiler/glsl/ir.h"
43 #include "compiler/glsl/program.h"
44 #include "compiler/glsl/gl_nir.h"
45 #include "compiler/glsl/glsl_to_nir.h"
47 #include "brw_program.h"
48 #include "brw_context.h"
49 #include "compiler/brw_nir.h"
50 #include "brw_defines.h"
51 #include "intel_batchbuffer.h"
58 #include "main/shaderapi.h"
59 #include "main/shaderobj.h"
62 brw_nir_lower_uniforms(nir_shader
*nir
, bool is_scalar
)
65 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
66 type_size_scalar_bytes
);
67 return nir_lower_io(nir
, nir_var_uniform
, type_size_scalar_bytes
, 0);
69 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
,
70 type_size_vec4_bytes
);
71 return nir_lower_io(nir
, nir_var_uniform
, type_size_vec4_bytes
, 0);
75 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
76 GLuint id
, bool is_arb_asm
);
79 brw_create_nir(struct brw_context
*brw
,
80 const struct gl_shader_program
*shader_prog
,
81 struct gl_program
*prog
,
82 gl_shader_stage stage
,
85 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
86 struct gl_context
*ctx
= &brw
->ctx
;
87 const nir_shader_compiler_options
*options
=
88 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
91 /* First, lower the GLSL/Mesa IR or SPIR-V to NIR */
93 if (shader_prog
->data
->spirv
) {
94 nir
= _mesa_spirv_to_nir(ctx
, shader_prog
, stage
, options
);
96 nir
= glsl_to_nir(ctx
, shader_prog
, stage
, options
);
100 nir_remove_dead_variables(nir
, nir_var_shader_in
| nir_var_shader_out
);
101 nir_validate_shader(nir
, "after glsl_to_nir or spirv_to_nir");
102 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
103 nir_shader_get_entrypoint(nir
), true, false);
105 nir
= prog_to_nir(prog
, options
);
106 NIR_PASS_V(nir
, nir_lower_regs_to_ssa
); /* turn registers into SSA */
107 NIR_PASS_V(nir
, gl_nir_lower_samplers
, NULL
);
109 nir_validate_shader(nir
, "before brw_preprocess_nir");
111 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
113 nir_shader
*softfp64
= NULL
;
114 if ((options
->lower_doubles_options
& nir_lower_fp64_full_software
) &&
115 nir
->info
.uses_64bit
) {
116 softfp64
= glsl_float64_funcs_to_nir(ctx
, options
);
117 ralloc_steal(ralloc_parent(nir
), softfp64
);
120 nir
= brw_preprocess_nir(brw
->screen
->compiler
, nir
, softfp64
);
122 NIR_PASS_V(nir
, brw_nir_lower_image_load_store
, devinfo
);
124 NIR_PASS_V(nir
, gl_nir_lower_buffers
, shader_prog
);
125 /* Do a round of constant folding to clean up address calculations */
126 NIR_PASS_V(nir
, nir_opt_constant_folding
);
128 if (stage
== MESA_SHADER_TESS_CTRL
) {
129 /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */
130 static const gl_state_index16 tokens
[STATE_LENGTH
] =
131 { STATE_INTERNAL
, STATE_TCS_PATCH_VERTICES_IN
};
132 nir_lower_patch_vertices(nir
, 0, devinfo
->gen
>= 8 ? tokens
: NULL
);
135 if (stage
== MESA_SHADER_TESS_EVAL
) {
136 /* Lower gl_PatchVerticesIn to a constant if we have a TCS, or
137 * a uniform if we don't.
139 struct gl_linked_shader
*tcs
=
140 shader_prog
->_LinkedShaders
[MESA_SHADER_TESS_CTRL
];
141 uint32_t static_patch_vertices
=
142 tcs
? tcs
->Program
->nir
->info
.tess
.tcs_vertices_out
: 0;
143 static const gl_state_index16 tokens
[STATE_LENGTH
] =
144 { STATE_INTERNAL
, STATE_TES_PATCH_VERTICES_IN
};
145 nir_lower_patch_vertices(nir
, static_patch_vertices
, tokens
);
148 if (stage
== MESA_SHADER_FRAGMENT
) {
149 static const struct nir_lower_wpos_ytransform_options wpos_options
= {
150 .state_tokens
= {STATE_INTERNAL
, STATE_FB_WPOS_Y_TRANSFORM
, 0, 0, 0},
151 .fs_coord_pixel_center_integer
= 1,
152 .fs_coord_origin_upper_left
= 1,
155 bool progress
= false;
156 NIR_PASS(progress
, nir
, nir_lower_wpos_ytransform
, &wpos_options
);
158 _mesa_add_state_reference(prog
->Parameters
,
159 wpos_options
.state_tokens
);
163 NIR_PASS_V(nir
, brw_nir_lower_uniforms
, is_scalar
);
169 brw_shader_gather_info(nir_shader
*nir
, struct gl_program
*prog
)
171 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
173 /* Copy the info we just generated back into the gl_program */
174 const char *prog_name
= prog
->info
.name
;
175 const char *prog_label
= prog
->info
.label
;
176 prog
->info
= nir
->info
;
177 prog
->info
.name
= prog_name
;
178 prog
->info
.label
= prog_label
;
182 get_new_program_id(struct intel_screen
*screen
)
184 return p_atomic_inc_return(&screen
->program_id
);
187 static struct gl_program
*brwNewProgram(struct gl_context
*ctx
, GLenum target
,
188 GLuint id
, bool is_arb_asm
)
190 struct brw_context
*brw
= brw_context(ctx
);
191 struct brw_program
*prog
= rzalloc(NULL
, struct brw_program
);
194 prog
->id
= get_new_program_id(brw
->screen
);
196 return _mesa_init_gl_program(&prog
->program
, target
, id
, is_arb_asm
);
202 static void brwDeleteProgram( struct gl_context
*ctx
,
203 struct gl_program
*prog
)
205 struct brw_context
*brw
= brw_context(ctx
);
207 /* Beware! prog's refcount has reached zero, and it's about to be freed.
209 * In brw_upload_pipeline_state(), we compare brw->programs[i] to
210 * ctx->FooProgram._Current, and flag BRW_NEW_FOO_PROGRAM if the
211 * pointer has changed.
213 * We cannot leave brw->programs[i] as a dangling pointer to the dead
214 * program. malloc() may allocate the same memory for a new gl_program,
215 * causing us to see matching pointers...but totally different programs.
217 * We cannot set brw->programs[i] to NULL, either. If we've deleted the
218 * active program, Mesa may set ctx->FooProgram._Current to NULL. That
219 * would cause us to see matching pointers (NULL == NULL), and fail to
220 * detect that a program has changed since our last draw.
222 * So, set it to a bogus gl_program pointer that will never match,
223 * causing us to properly reevaluate the state on our next draw.
225 * Getting this wrong causes heisenbugs which are very hard to catch,
226 * as you need a very specific allocation pattern to hit the problem.
228 static const struct gl_program deleted_program
;
230 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
231 if (brw
->programs
[i
] == prog
)
232 brw
->programs
[i
] = (struct gl_program
*) &deleted_program
;
235 _mesa_delete_program( ctx
, prog
);
240 brwProgramStringNotify(struct gl_context
*ctx
,
242 struct gl_program
*prog
)
244 assert(target
== GL_VERTEX_PROGRAM_ARB
|| !prog
->arb
.IsPositionInvariant
);
246 struct brw_context
*brw
= brw_context(ctx
);
247 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
250 case GL_FRAGMENT_PROGRAM_ARB
: {
251 struct brw_program
*newFP
= brw_program(prog
);
252 const struct brw_program
*curFP
=
253 brw_program_const(brw
->programs
[MESA_SHADER_FRAGMENT
]);
256 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
257 newFP
->id
= get_new_program_id(brw
->screen
);
259 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_FRAGMENT
, true);
261 brw_shader_gather_info(prog
->nir
, prog
);
263 brw_fs_precompile(ctx
, prog
);
266 case GL_VERTEX_PROGRAM_ARB
: {
267 struct brw_program
*newVP
= brw_program(prog
);
268 const struct brw_program
*curVP
=
269 brw_program_const(brw
->programs
[MESA_SHADER_VERTEX
]);
272 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
273 if (newVP
->program
.arb
.IsPositionInvariant
) {
274 _mesa_insert_mvp_code(ctx
, &newVP
->program
);
276 newVP
->id
= get_new_program_id(brw
->screen
);
278 /* Also tell tnl about it:
280 _tnl_program_string(ctx
, target
, prog
);
282 prog
->nir
= brw_create_nir(brw
, NULL
, prog
, MESA_SHADER_VERTEX
,
283 compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
285 brw_shader_gather_info(prog
->nir
, prog
);
287 brw_vs_precompile(ctx
, prog
);
292 * driver->ProgramStringNotify is only called for ARB programs, fixed
293 * function vertex programs, and ir_to_mesa (which isn't used by the
294 * i965 back-end). Therefore, even after geometry shaders are added,
295 * this function should only ever be called with a target of
296 * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
298 unreachable("Unexpected target in brwProgramStringNotify");
305 brw_memory_barrier(struct gl_context
*ctx
, GLbitfield barriers
)
307 struct brw_context
*brw
= brw_context(ctx
);
308 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
309 unsigned bits
= PIPE_CONTROL_DATA_CACHE_FLUSH
| PIPE_CONTROL_CS_STALL
;
310 assert(devinfo
->gen
>= 7 && devinfo
->gen
<= 11);
312 if (barriers
& (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT
|
313 GL_ELEMENT_ARRAY_BARRIER_BIT
|
314 GL_COMMAND_BARRIER_BIT
))
315 bits
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
317 if (barriers
& GL_UNIFORM_BARRIER_BIT
)
318 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
319 PIPE_CONTROL_CONST_CACHE_INVALIDATE
);
321 if (barriers
& GL_TEXTURE_FETCH_BARRIER_BIT
)
322 bits
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
324 if (barriers
& (GL_TEXTURE_UPDATE_BARRIER_BIT
|
325 GL_PIXEL_BUFFER_BARRIER_BIT
))
326 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
327 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
329 if (barriers
& GL_FRAMEBUFFER_BARRIER_BIT
)
330 bits
|= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
331 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
333 /* Typed surface messages are handled by the render cache on IVB, so we
334 * need to flush it too.
336 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
337 bits
|= PIPE_CONTROL_RENDER_TARGET_FLUSH
;
339 brw_emit_pipe_control_flush(brw
, bits
);
343 brw_framebuffer_fetch_barrier(struct gl_context
*ctx
)
345 struct brw_context
*brw
= brw_context(ctx
);
346 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
348 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
) {
349 if (devinfo
->gen
>= 6) {
350 brw_emit_pipe_control_flush(brw
,
351 PIPE_CONTROL_RENDER_TARGET_FLUSH
|
352 PIPE_CONTROL_CS_STALL
);
353 brw_emit_pipe_control_flush(brw
,
354 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
356 brw_emit_pipe_control_flush(brw
,
357 PIPE_CONTROL_RENDER_TARGET_FLUSH
);
363 brw_get_scratch_bo(struct brw_context
*brw
,
364 struct brw_bo
**scratch_bo
, int size
)
366 struct brw_bo
*old_bo
= *scratch_bo
;
368 if (old_bo
&& old_bo
->size
< size
) {
369 brw_bo_unreference(old_bo
);
375 brw_bo_alloc(brw
->bufmgr
, "scratch bo", size
, BRW_MEMZONE_SCRATCH
);
380 * Reserve enough scratch space for the given stage to hold \p per_thread_size
381 * bytes times the given \p thread_count.
384 brw_alloc_stage_scratch(struct brw_context
*brw
,
385 struct brw_stage_state
*stage_state
,
386 unsigned per_thread_size
)
388 if (stage_state
->per_thread_scratch
>= per_thread_size
)
391 stage_state
->per_thread_scratch
= per_thread_size
;
393 if (stage_state
->scratch_bo
)
394 brw_bo_unreference(stage_state
->scratch_bo
);
396 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
397 unsigned thread_count
;
398 switch(stage_state
->stage
) {
399 case MESA_SHADER_VERTEX
:
400 thread_count
= devinfo
->max_vs_threads
;
402 case MESA_SHADER_TESS_CTRL
:
403 thread_count
= devinfo
->max_tcs_threads
;
405 case MESA_SHADER_TESS_EVAL
:
406 thread_count
= devinfo
->max_tes_threads
;
408 case MESA_SHADER_GEOMETRY
:
409 thread_count
= devinfo
->max_gs_threads
;
411 case MESA_SHADER_FRAGMENT
:
412 thread_count
= devinfo
->max_wm_threads
;
414 case MESA_SHADER_COMPUTE
: {
415 unsigned subslices
= MAX2(brw
->screen
->subslice_total
, 1);
417 /* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
419 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
420 * allocate scratch space enough so that each slice has 4 slices
423 * According to the other driver team, this applies to compute shaders
424 * as well. This is not currently documented at all.
426 * brw->screen->subslice_total is the TOTAL number of subslices
427 * and we wish to view that there are 4 subslices per slice
428 * instead of the actual number of subslices per slice.
430 if (devinfo
->gen
>= 9 && devinfo
->gen
< 11)
431 subslices
= 4 * brw
->screen
->devinfo
.num_slices
;
433 unsigned scratch_ids_per_subslice
;
434 if (devinfo
->is_haswell
) {
435 /* WaCSScratchSize:hsw
437 * Haswell's scratch space address calculation appears to be sparse
438 * rather than tightly packed. The Thread ID has bits indicating
439 * which subslice, EU within a subslice, and thread within an EU it
440 * is. There's a maximum of two slices and two subslices, so these
441 * can be stored with a single bit. Even though there are only 10 EUs
442 * per subslice, this is stored in 4 bits, so there's an effective
443 * maximum value of 16 EUs. Similarly, although there are only 7
444 * threads per EU, this is stored in a 3 bit number, giving an
445 * effective maximum value of 8 threads per EU.
447 * This means that we need to use 16 * 8 instead of 10 * 7 for the
448 * number of threads per subslice.
450 scratch_ids_per_subslice
= 16 * 8;
451 } else if (devinfo
->is_cherryview
) {
452 /* Cherryview devices have either 6 or 8 EUs per subslice, and each
453 * EU has 7 threads. The 6 EU devices appear to calculate thread IDs
454 * as if it had 8 EUs.
456 scratch_ids_per_subslice
= 8 * 7;
458 scratch_ids_per_subslice
= devinfo
->max_cs_threads
;
461 thread_count
= scratch_ids_per_subslice
* subslices
;
465 unreachable("Unsupported stage!");
468 stage_state
->scratch_bo
=
469 brw_bo_alloc(brw
->bufmgr
, "shader scratch space",
470 per_thread_size
* thread_count
, BRW_MEMZONE_SCRATCH
);
473 void brwInitFragProgFuncs( struct dd_function_table
*functions
)
475 assert(functions
->ProgramStringNotify
== _tnl_program_string
);
477 functions
->NewProgram
= brwNewProgram
;
478 functions
->DeleteProgram
= brwDeleteProgram
;
479 functions
->ProgramStringNotify
= brwProgramStringNotify
;
481 functions
->LinkShader
= brw_link_shader
;
483 functions
->MemoryBarrier
= brw_memory_barrier
;
484 functions
->FramebufferFetchBarrier
= brw_framebuffer_fetch_barrier
;
487 struct shader_times
{
494 brw_init_shader_time(struct brw_context
*brw
)
496 const int max_entries
= 2048;
497 brw
->shader_time
.bo
=
498 brw_bo_alloc(brw
->bufmgr
, "shader time",
499 max_entries
* BRW_SHADER_TIME_STRIDE
* 3,
501 brw
->shader_time
.names
= rzalloc_array(brw
, const char *, max_entries
);
502 brw
->shader_time
.ids
= rzalloc_array(brw
, int, max_entries
);
503 brw
->shader_time
.types
= rzalloc_array(brw
, enum shader_time_shader_type
,
505 brw
->shader_time
.cumulative
= rzalloc_array(brw
, struct shader_times
,
507 brw
->shader_time
.max_entries
= max_entries
;
511 compare_time(const void *a
, const void *b
)
513 uint64_t * const *a_val
= a
;
514 uint64_t * const *b_val
= b
;
516 /* We don't just subtract because we're turning the value to an int. */
517 if (**a_val
< **b_val
)
519 else if (**a_val
== **b_val
)
526 print_shader_time_line(const char *stage
, const char *name
,
527 int shader_num
, uint64_t time
, uint64_t total
)
529 fprintf(stderr
, "%-6s%-18s", stage
, name
);
532 fprintf(stderr
, "%4d: ", shader_num
);
534 fprintf(stderr
, " : ");
536 fprintf(stderr
, "%16lld (%7.2f Gcycles) %4.1f%%\n",
538 (double)time
/ 1000000000.0,
539 (double)time
/ total
* 100.0);
543 brw_report_shader_time(struct brw_context
*brw
)
545 if (!brw
->shader_time
.bo
|| !brw
->shader_time
.num_entries
)
548 uint64_t scaled
[brw
->shader_time
.num_entries
];
549 uint64_t *sorted
[brw
->shader_time
.num_entries
];
550 uint64_t total_by_type
[ST_CS
+ 1];
551 memset(total_by_type
, 0, sizeof(total_by_type
));
553 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
554 uint64_t written
= 0, reset
= 0;
555 enum shader_time_shader_type type
= brw
->shader_time
.types
[i
];
557 sorted
[i
] = &scaled
[i
];
568 written
= brw
->shader_time
.cumulative
[i
].written
;
569 reset
= brw
->shader_time
.cumulative
[i
].reset
;
573 /* I sometimes want to print things that aren't the 3 shader times.
574 * Just print the sum in that case.
581 uint64_t time
= brw
->shader_time
.cumulative
[i
].time
;
583 scaled
[i
] = time
/ written
* (written
+ reset
);
597 total_by_type
[type
] += scaled
[i
];
607 fprintf(stderr
, "No shader time collected yet\n");
611 qsort(sorted
, brw
->shader_time
.num_entries
, sizeof(sorted
[0]), compare_time
);
613 fprintf(stderr
, "\n");
614 fprintf(stderr
, "type ID cycles spent %% of total\n");
615 for (int s
= 0; s
< brw
->shader_time
.num_entries
; s
++) {
617 /* Work back from the sorted pointers times to a time to print. */
618 int i
= sorted
[s
] - scaled
;
623 int shader_num
= brw
->shader_time
.ids
[i
];
624 const char *shader_name
= brw
->shader_time
.names
[i
];
626 switch (brw
->shader_time
.types
[i
]) {
656 print_shader_time_line(stage
, shader_name
, shader_num
,
660 fprintf(stderr
, "\n");
661 print_shader_time_line("total", "vs", 0, total_by_type
[ST_VS
], total
);
662 print_shader_time_line("total", "tcs", 0, total_by_type
[ST_TCS
], total
);
663 print_shader_time_line("total", "tes", 0, total_by_type
[ST_TES
], total
);
664 print_shader_time_line("total", "gs", 0, total_by_type
[ST_GS
], total
);
665 print_shader_time_line("total", "fs8", 0, total_by_type
[ST_FS8
], total
);
666 print_shader_time_line("total", "fs16", 0, total_by_type
[ST_FS16
], total
);
667 print_shader_time_line("total", "fs32", 0, total_by_type
[ST_FS32
], total
);
668 print_shader_time_line("total", "cs", 0, total_by_type
[ST_CS
], total
);
672 brw_collect_shader_time(struct brw_context
*brw
)
674 if (!brw
->shader_time
.bo
)
677 /* This probably stalls on the last rendering. We could fix that by
678 * delaying reading the reports, but it doesn't look like it's a big
679 * overhead compared to the cost of tracking the time in the first place.
681 void *bo_map
= brw_bo_map(brw
, brw
->shader_time
.bo
, MAP_READ
| MAP_WRITE
);
683 for (int i
= 0; i
< brw
->shader_time
.num_entries
; i
++) {
684 uint32_t *times
= bo_map
+ i
* 3 * BRW_SHADER_TIME_STRIDE
;
686 brw
->shader_time
.cumulative
[i
].time
+= times
[BRW_SHADER_TIME_STRIDE
* 0 / 4];
687 brw
->shader_time
.cumulative
[i
].written
+= times
[BRW_SHADER_TIME_STRIDE
* 1 / 4];
688 brw
->shader_time
.cumulative
[i
].reset
+= times
[BRW_SHADER_TIME_STRIDE
* 2 / 4];
691 /* Zero the BO out to clear it out for our next collection.
693 memset(bo_map
, 0, brw
->shader_time
.bo
->size
);
694 brw_bo_unmap(brw
->shader_time
.bo
);
698 brw_collect_and_report_shader_time(struct brw_context
*brw
)
700 brw_collect_shader_time(brw
);
702 if (brw
->shader_time
.report_time
== 0 ||
703 get_time() - brw
->shader_time
.report_time
>= 1.0) {
704 brw_report_shader_time(brw
);
705 brw
->shader_time
.report_time
= get_time();
710 * Chooses an index in the shader_time buffer and sets up tracking information
713 * Note that this holds on to references to the underlying programs, which may
714 * change their lifetimes compared to normal operation.
717 brw_get_shader_time_index(struct brw_context
*brw
, struct gl_program
*prog
,
718 enum shader_time_shader_type type
, bool is_glsl_sh
)
720 int shader_time_index
= brw
->shader_time
.num_entries
++;
721 assert(shader_time_index
< brw
->shader_time
.max_entries
);
722 brw
->shader_time
.types
[shader_time_index
] = type
;
727 } else if (is_glsl_sh
) {
728 name
= prog
->info
.label
?
729 ralloc_strdup(brw
->shader_time
.names
, prog
->info
.label
) : "glsl";
734 brw
->shader_time
.names
[shader_time_index
] = name
;
735 brw
->shader_time
.ids
[shader_time_index
] = prog
->Id
;
737 return shader_time_index
;
741 brw_destroy_shader_time(struct brw_context
*brw
)
743 brw_bo_unreference(brw
->shader_time
.bo
);
744 brw
->shader_time
.bo
= NULL
;
748 brw_stage_prog_data_free(const void *p
)
750 struct brw_stage_prog_data
*prog_data
= (struct brw_stage_prog_data
*)p
;
752 ralloc_free(prog_data
->param
);
753 ralloc_free(prog_data
->pull_param
);
757 brw_dump_arb_asm(const char *stage
, struct gl_program
*prog
)
759 fprintf(stderr
, "ARB_%s_program %d ir for native %s shader\n",
760 stage
, prog
->Id
, stage
);
761 _mesa_print_program(prog
);
765 brw_setup_tex_for_precompile(const struct gen_device_info
*devinfo
,
766 struct brw_sampler_prog_key_data
*tex
,
767 struct gl_program
*prog
)
769 const bool has_shader_channel_select
= devinfo
->is_haswell
|| devinfo
->gen
>= 8;
770 unsigned sampler_count
= util_last_bit(prog
->SamplersUsed
);
771 for (unsigned i
= 0; i
< sampler_count
; i
++) {
772 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
773 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
775 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
777 /* Color sampler: assume no swizzling. */
778 tex
->swizzles
[i
] = SWIZZLE_XYZW
;
784 * Sets up the starting offsets for the groups of binding table entries
785 * common to all pipeline stages.
787 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
788 * unused but also make sure that addition of small offsets to them will
789 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
792 brw_assign_common_binding_table_offsets(const struct gen_device_info
*devinfo
,
793 const struct gl_program
*prog
,
794 struct brw_stage_prog_data
*stage_prog_data
,
795 uint32_t next_binding_table_offset
)
797 int num_textures
= util_last_bit(prog
->SamplersUsed
);
799 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
800 next_binding_table_offset
+= num_textures
;
802 if (prog
->info
.num_ubos
) {
803 assert(prog
->info
.num_ubos
<= BRW_MAX_UBO
);
804 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
805 next_binding_table_offset
+= prog
->info
.num_ubos
;
807 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
810 if (prog
->info
.num_ssbos
|| prog
->info
.num_abos
) {
811 assert(prog
->info
.num_abos
<= BRW_MAX_ABO
);
812 assert(prog
->info
.num_ssbos
<= BRW_MAX_SSBO
);
813 stage_prog_data
->binding_table
.ssbo_start
= next_binding_table_offset
;
814 next_binding_table_offset
+= prog
->info
.num_abos
+ prog
->info
.num_ssbos
;
816 stage_prog_data
->binding_table
.ssbo_start
= 0xd0d0d0d0;
819 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
820 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
821 next_binding_table_offset
++;
823 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
826 if (prog
->info
.uses_texture_gather
) {
827 if (devinfo
->gen
>= 8) {
828 stage_prog_data
->binding_table
.gather_texture_start
=
829 stage_prog_data
->binding_table
.texture_start
;
831 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
832 next_binding_table_offset
+= num_textures
;
835 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
838 if (prog
->info
.num_images
) {
839 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
840 next_binding_table_offset
+= prog
->info
.num_images
;
842 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
845 /* This may or may not be used depending on how the compile goes. */
846 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
847 next_binding_table_offset
++;
849 /* Plane 0 is just the regular texture section */
850 stage_prog_data
->binding_table
.plane_start
[0] = stage_prog_data
->binding_table
.texture_start
;
852 stage_prog_data
->binding_table
.plane_start
[1] = next_binding_table_offset
;
853 next_binding_table_offset
+= num_textures
;
855 stage_prog_data
->binding_table
.plane_start
[2] = next_binding_table_offset
;
856 next_binding_table_offset
+= num_textures
;
858 /* Set the binding table size. Some callers may append new entries
859 * and increase this accordingly.
861 stage_prog_data
->binding_table
.size_bytes
= next_binding_table_offset
* 4;
863 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
864 return next_binding_table_offset
;
868 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage stage
,
871 static const unsigned stage_offsets
[] = {
872 offsetof(struct brw_vs_prog_key
, program_string_id
),
873 offsetof(struct brw_tcs_prog_key
, program_string_id
),
874 offsetof(struct brw_tes_prog_key
, program_string_id
),
875 offsetof(struct brw_gs_prog_key
, program_string_id
),
876 offsetof(struct brw_wm_prog_key
, program_string_id
),
877 offsetof(struct brw_cs_prog_key
, program_string_id
),
879 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_offsets
));
880 *(unsigned*)((uint8_t*)key
+ stage_offsets
[stage
]) = id
;
884 brw_populate_default_key(const struct gen_device_info
*devinfo
,
885 union brw_any_prog_key
*prog_key
,
886 struct gl_shader_program
*sh_prog
,
887 struct gl_program
*prog
)
889 switch (prog
->info
.stage
) {
890 case MESA_SHADER_VERTEX
:
891 brw_vs_populate_default_key(devinfo
, &prog_key
->vs
, prog
);
893 case MESA_SHADER_TESS_CTRL
:
894 brw_tcs_populate_default_key(devinfo
, &prog_key
->tcs
, sh_prog
, prog
);
896 case MESA_SHADER_TESS_EVAL
:
897 brw_tes_populate_default_key(devinfo
, &prog_key
->tes
, sh_prog
, prog
);
899 case MESA_SHADER_GEOMETRY
:
900 brw_gs_populate_default_key(devinfo
, &prog_key
->gs
, prog
);
902 case MESA_SHADER_FRAGMENT
:
903 brw_wm_populate_default_key(devinfo
, &prog_key
->wm
, prog
);
905 case MESA_SHADER_COMPUTE
:
906 brw_cs_populate_default_key(devinfo
, &prog_key
->cs
, prog
);
909 unreachable("Unsupported stage!");