2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/macros.h"
25 #include "brw_context.h"
31 #include "glsl/ir_optimization.h"
32 #include "glsl/glsl_parser_extras.h"
33 #include "main/shaderapi.h"
36 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
38 struct brw_context
*brw
= (struct brw_context
*)data
;
43 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
44 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
45 MESA_DEBUG_TYPE_OTHER
,
46 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
51 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
53 struct brw_context
*brw
= (struct brw_context
*)data
;
58 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
60 va_copy(args_copy
, args
);
61 vfprintf(stderr
, fmt
, args_copy
);
65 if (brw
->perf_debug
) {
67 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
68 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
69 MESA_DEBUG_TYPE_PERFORMANCE
,
70 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
76 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
)
78 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
80 compiler
->devinfo
= devinfo
;
81 compiler
->shader_debug_log
= shader_debug_log_mesa
;
82 compiler
->shader_perf_log
= shader_perf_log_mesa
;
84 brw_fs_alloc_reg_sets(compiler
);
85 brw_vec4_alloc_reg_set(compiler
);
87 if (devinfo
->gen
>= 8 && !(INTEL_DEBUG
& DEBUG_VEC4VS
))
88 compiler
->scalar_vs
= true;
90 nir_shader_compiler_options
*nir_options
=
91 rzalloc(compiler
, nir_shader_compiler_options
);
92 nir_options
->native_integers
= true;
93 /* In order to help allow for better CSE at the NIR level we tell NIR
94 * to split all ffma instructions during opt_algebraic and we then
95 * re-combine them as a later step.
97 nir_options
->lower_ffma
= true;
98 nir_options
->lower_sub
= true;
99 nir_options
->lower_fdiv
= true;
101 /* We want the GLSL compiler to emit code that uses condition codes */
102 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
103 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 32;
104 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
105 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
107 compiler
->glsl_compiler_options
[i
].EmitCondCodes
= true;
108 compiler
->glsl_compiler_options
[i
].EmitNoNoise
= true;
109 compiler
->glsl_compiler_options
[i
].EmitNoMainReturn
= true;
110 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
111 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
=
112 (i
== MESA_SHADER_FRAGMENT
);
113 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
=
114 (i
== MESA_SHADER_FRAGMENT
);
115 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
116 compiler
->glsl_compiler_options
[i
].LowerClipDistance
= true;
118 /* !ARB_gpu_shader5 */
119 if (devinfo
->gen
< 7)
120 compiler
->glsl_compiler_options
[i
].EmitNoIndirectSampler
= true;
123 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].OptimizeForAOS
= true;
124 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].OptimizeForAOS
= true;
126 if (compiler
->scalar_vs
|| brw_env_var_as_boolean("INTEL_USE_NIR", true)) {
127 if (compiler
->scalar_vs
) {
128 /* If we're using the scalar backend for vertex shaders, we need to
129 * configure these accordingly.
131 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].EmitNoIndirectOutput
= true;
132 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].EmitNoIndirectTemp
= true;
133 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].OptimizeForAOS
= false;
136 compiler
->glsl_compiler_options
[MESA_SHADER_VERTEX
].NirOptions
= nir_options
;
139 if (brw_env_var_as_boolean("INTEL_USE_NIR", true)) {
140 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].NirOptions
= nir_options
;
143 compiler
->glsl_compiler_options
[MESA_SHADER_FRAGMENT
].NirOptions
= nir_options
;
144 compiler
->glsl_compiler_options
[MESA_SHADER_COMPUTE
].NirOptions
= nir_options
;
150 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
152 struct brw_shader
*shader
;
154 shader
= rzalloc(NULL
, struct brw_shader
);
156 shader
->base
.Type
= type
;
157 shader
->base
.Stage
= _mesa_shader_enum_to_shader_stage(type
);
158 shader
->base
.Name
= name
;
159 _mesa_init_shader(ctx
, &shader
->base
);
162 return &shader
->base
;
166 * Performs a compile of the shader stages even when we don't know
167 * what non-orthogonal state will be set, in the hope that it reflects
168 * the eventual NOS used, and thus allows us to produce link failures.
171 brw_shader_precompile(struct gl_context
*ctx
,
172 struct gl_shader_program
*sh_prog
)
174 struct gl_shader
*vs
= sh_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
175 struct gl_shader
*gs
= sh_prog
->_LinkedShaders
[MESA_SHADER_GEOMETRY
];
176 struct gl_shader
*fs
= sh_prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
177 struct gl_shader
*cs
= sh_prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
];
179 if (fs
&& !brw_fs_precompile(ctx
, sh_prog
, fs
->Program
))
182 if (gs
&& !brw_gs_precompile(ctx
, sh_prog
, gs
->Program
))
185 if (vs
&& !brw_vs_precompile(ctx
, sh_prog
, vs
->Program
))
188 if (cs
&& !brw_cs_precompile(ctx
, sh_prog
, cs
->Program
))
195 is_scalar_shader_stage(struct brw_context
*brw
, int stage
)
198 case MESA_SHADER_FRAGMENT
:
200 case MESA_SHADER_VERTEX
:
201 return brw
->intelScreen
->compiler
->scalar_vs
;
208 brw_lower_packing_builtins(struct brw_context
*brw
,
209 gl_shader_stage shader_type
,
212 int ops
= LOWER_PACK_SNORM_2x16
213 | LOWER_UNPACK_SNORM_2x16
214 | LOWER_PACK_UNORM_2x16
215 | LOWER_UNPACK_UNORM_2x16
;
217 if (is_scalar_shader_stage(brw
, shader_type
)) {
218 ops
|= LOWER_UNPACK_UNORM_4x8
219 | LOWER_UNPACK_SNORM_4x8
220 | LOWER_PACK_UNORM_4x8
221 | LOWER_PACK_SNORM_4x8
;
225 /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
226 * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
227 * lowering is needed. For SOA code, the Half2x16 ops must be
230 if (is_scalar_shader_stage(brw
, shader_type
)) {
231 ops
|= LOWER_PACK_HALF_2x16_TO_SPLIT
232 | LOWER_UNPACK_HALF_2x16_TO_SPLIT
;
235 ops
|= LOWER_PACK_HALF_2x16
236 | LOWER_UNPACK_HALF_2x16
;
239 lower_packing_builtins(ir
, ops
);
243 process_glsl_ir(gl_shader_stage stage
,
244 struct brw_context
*brw
,
245 struct gl_shader_program
*shader_prog
,
246 struct gl_shader
*shader
)
248 struct gl_context
*ctx
= &brw
->ctx
;
249 const struct gl_shader_compiler_options
*options
=
250 &ctx
->Const
.ShaderCompilerOptions
[shader
->Stage
];
252 /* Temporary memory context for any new IR. */
253 void *mem_ctx
= ralloc_context(NULL
);
255 ralloc_adopt(mem_ctx
, shader
->ir
);
257 /* lower_packing_builtins() inserts arithmetic instructions, so it
258 * must precede lower_instructions().
260 brw_lower_packing_builtins(brw
, shader
->Stage
, shader
->ir
);
261 do_mat_op_to_vec(shader
->ir
);
262 const int bitfield_insert
= brw
->gen
>= 7 ? BITFIELD_INSERT_TO_BFM_BFI
: 0;
263 lower_instructions(shader
->ir
,
274 /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
275 * if-statements need to be flattened.
278 lower_if_to_cond_assign(shader
->ir
, 16);
280 do_lower_texture_projection(shader
->ir
);
281 brw_lower_texture_gradients(brw
, shader
->ir
);
282 do_vec_index_to_cond_assign(shader
->ir
);
283 lower_vector_insert(shader
->ir
, true);
284 if (options
->NirOptions
== NULL
)
285 brw_do_cubemap_normalize(shader
->ir
);
286 lower_offset_arrays(shader
->ir
);
287 brw_do_lower_unnormalized_offset(shader
->ir
);
288 lower_noise(shader
->ir
);
289 lower_quadop_vector(shader
->ir
, false);
291 bool lowered_variable_indexing
=
292 lower_variable_index_to_cond_assign((gl_shader_stage
)stage
,
294 options
->EmitNoIndirectInput
,
295 options
->EmitNoIndirectOutput
,
296 options
->EmitNoIndirectTemp
,
297 options
->EmitNoIndirectUniform
);
299 if (unlikely(brw
->perf_debug
&& lowered_variable_indexing
)) {
300 perf_debug("Unsupported form of variable indexing in %s; falling "
301 "back to very inefficient code generation\n",
302 _mesa_shader_stage_to_abbrev(shader
->Stage
));
305 lower_ubo_reference(shader
, shader
->ir
);
311 if (is_scalar_shader_stage(brw
, shader
->Stage
)) {
312 brw_do_channel_expressions(shader
->ir
);
313 brw_do_vector_splitting(shader
->ir
);
316 progress
= do_lower_jumps(shader
->ir
, true, true,
317 true, /* main return */
318 false, /* continue */
322 progress
= do_common_optimization(shader
->ir
, true, true,
323 options
, ctx
->Const
.NativeIntegers
) || progress
;
326 if (options
->NirOptions
!= NULL
)
327 lower_output_reads(stage
, shader
->ir
);
329 validate_ir_tree(shader
->ir
);
331 /* Now that we've finished altering the linked IR, reparent any live IR back
332 * to the permanent memory context, and free the temporary one (discarding any
333 * junk we optimized away).
335 reparent_ir(shader
->ir
, shader
->ir
);
336 ralloc_free(mem_ctx
);
338 if (ctx
->_Shader
->Flags
& GLSL_DUMP
) {
339 fprintf(stderr
, "\n");
340 fprintf(stderr
, "GLSL IR for linked %s program %d:\n",
341 _mesa_shader_stage_to_string(shader
->Stage
),
343 _mesa_print_ir(stderr
, shader
->ir
, NULL
);
344 fprintf(stderr
, "\n");
349 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*shProg
)
351 struct brw_context
*brw
= brw_context(ctx
);
354 for (stage
= 0; stage
< ARRAY_SIZE(shProg
->_LinkedShaders
); stage
++) {
355 struct gl_shader
*shader
= shProg
->_LinkedShaders
[stage
];
356 const struct gl_shader_compiler_options
*options
=
357 &ctx
->Const
.ShaderCompilerOptions
[stage
];
362 struct gl_program
*prog
=
363 ctx
->Driver
.NewProgram(ctx
, _mesa_shader_stage_to_program(stage
),
367 prog
->Parameters
= _mesa_new_parameter_list();
369 _mesa_copy_linked_program_data((gl_shader_stage
) stage
, shProg
, prog
);
371 process_glsl_ir((gl_shader_stage
) stage
, brw
, shProg
, shader
);
373 /* Make a pass over the IR to add state references for any built-in
374 * uniforms that are used. This has to be done now (during linking).
375 * Code generation doesn't happen until the first time this shader is
376 * used for rendering. Waiting until then to generate the parameters is
377 * too late. At that point, the values for the built-in uniforms won't
378 * get sent to the shader.
380 foreach_in_list(ir_instruction
, node
, shader
->ir
) {
381 ir_variable
*var
= node
->as_variable();
383 if ((var
== NULL
) || (var
->data
.mode
!= ir_var_uniform
)
384 || (strncmp(var
->name
, "gl_", 3) != 0))
387 const ir_state_slot
*const slots
= var
->get_state_slots();
388 assert(slots
!= NULL
);
390 for (unsigned int i
= 0; i
< var
->get_num_state_slots(); i
++) {
391 _mesa_add_state_reference(prog
->Parameters
,
392 (gl_state_index
*) slots
[i
].tokens
);
396 do_set_program_inouts(shader
->ir
, prog
, shader
->Stage
);
398 prog
->SamplersUsed
= shader
->active_samplers
;
399 prog
->ShadowSamplers
= shader
->shadow_samplers
;
400 _mesa_update_shader_textures_used(shProg
, prog
);
402 _mesa_reference_program(ctx
, &shader
->Program
, prog
);
404 brw_add_texrect_params(prog
);
406 if (options
->NirOptions
) {
407 prog
->nir
= brw_create_nir(brw
, shProg
, prog
, (gl_shader_stage
) stage
,
408 is_scalar_shader_stage(brw
, stage
));
411 _mesa_reference_program(ctx
, &prog
, NULL
);
414 if ((ctx
->_Shader
->Flags
& GLSL_DUMP
) && shProg
->Name
!= 0) {
415 for (unsigned i
= 0; i
< shProg
->NumShaders
; i
++) {
416 const struct gl_shader
*sh
= shProg
->Shaders
[i
];
420 fprintf(stderr
, "GLSL %s shader %d source for linked program %d:\n",
421 _mesa_shader_stage_to_string(sh
->Stage
),
423 fprintf(stderr
, "%s", sh
->Source
);
424 fprintf(stderr
, "\n");
428 if (brw
->precompile
&& !brw_shader_precompile(ctx
, shProg
))
436 brw_type_for_base_type(const struct glsl_type
*type
)
438 switch (type
->base_type
) {
439 case GLSL_TYPE_FLOAT
:
440 return BRW_REGISTER_TYPE_F
;
443 case GLSL_TYPE_SUBROUTINE
:
444 return BRW_REGISTER_TYPE_D
;
446 return BRW_REGISTER_TYPE_UD
;
447 case GLSL_TYPE_ARRAY
:
448 return brw_type_for_base_type(type
->fields
.array
);
449 case GLSL_TYPE_STRUCT
:
450 case GLSL_TYPE_SAMPLER
:
451 case GLSL_TYPE_ATOMIC_UINT
:
452 /* These should be overridden with the type of the member when
453 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
454 * way to trip up if we don't.
456 return BRW_REGISTER_TYPE_UD
;
457 case GLSL_TYPE_IMAGE
:
458 return BRW_REGISTER_TYPE_UD
;
460 case GLSL_TYPE_ERROR
:
461 case GLSL_TYPE_INTERFACE
:
462 case GLSL_TYPE_DOUBLE
:
463 case GLSL_TYPE_FUNCTION
:
464 unreachable("not reached");
467 return BRW_REGISTER_TYPE_F
;
470 enum brw_conditional_mod
471 brw_conditional_for_comparison(unsigned int op
)
475 return BRW_CONDITIONAL_L
;
476 case ir_binop_greater
:
477 return BRW_CONDITIONAL_G
;
478 case ir_binop_lequal
:
479 return BRW_CONDITIONAL_LE
;
480 case ir_binop_gequal
:
481 return BRW_CONDITIONAL_GE
;
483 case ir_binop_all_equal
: /* same as equal for scalars */
484 return BRW_CONDITIONAL_Z
;
485 case ir_binop_nequal
:
486 case ir_binop_any_nequal
: /* same as nequal for scalars */
487 return BRW_CONDITIONAL_NZ
;
489 unreachable("not reached: bad operation for comparison");
494 brw_math_function(enum opcode op
)
497 case SHADER_OPCODE_RCP
:
498 return BRW_MATH_FUNCTION_INV
;
499 case SHADER_OPCODE_RSQ
:
500 return BRW_MATH_FUNCTION_RSQ
;
501 case SHADER_OPCODE_SQRT
:
502 return BRW_MATH_FUNCTION_SQRT
;
503 case SHADER_OPCODE_EXP2
:
504 return BRW_MATH_FUNCTION_EXP
;
505 case SHADER_OPCODE_LOG2
:
506 return BRW_MATH_FUNCTION_LOG
;
507 case SHADER_OPCODE_POW
:
508 return BRW_MATH_FUNCTION_POW
;
509 case SHADER_OPCODE_SIN
:
510 return BRW_MATH_FUNCTION_SIN
;
511 case SHADER_OPCODE_COS
:
512 return BRW_MATH_FUNCTION_COS
;
513 case SHADER_OPCODE_INT_QUOTIENT
:
514 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
515 case SHADER_OPCODE_INT_REMAINDER
:
516 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
518 unreachable("not reached: unknown math function");
523 brw_texture_offset(int *offsets
, unsigned num_components
)
525 if (!offsets
) return 0; /* nonconstant offset; caller will handle it. */
527 /* Combine all three offsets into a single unsigned dword:
529 * bits 11:8 - U Offset (X component)
530 * bits 7:4 - V Offset (Y component)
531 * bits 3:0 - R Offset (Z component)
533 unsigned offset_bits
= 0;
534 for (unsigned i
= 0; i
< num_components
; i
++) {
535 const unsigned shift
= 4 * (2 - i
);
536 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
542 brw_instruction_name(enum opcode op
)
545 case BRW_OPCODE_MOV
... BRW_OPCODE_NOP
:
546 assert(opcode_descs
[op
].name
);
547 return opcode_descs
[op
].name
;
548 case FS_OPCODE_FB_WRITE
:
550 case FS_OPCODE_FB_WRITE_LOGICAL
:
551 return "fb_write_logical";
552 case FS_OPCODE_BLORP_FB_WRITE
:
553 return "blorp_fb_write";
554 case FS_OPCODE_REP_FB_WRITE
:
555 return "rep_fb_write";
557 case SHADER_OPCODE_RCP
:
559 case SHADER_OPCODE_RSQ
:
561 case SHADER_OPCODE_SQRT
:
563 case SHADER_OPCODE_EXP2
:
565 case SHADER_OPCODE_LOG2
:
567 case SHADER_OPCODE_POW
:
569 case SHADER_OPCODE_INT_QUOTIENT
:
571 case SHADER_OPCODE_INT_REMAINDER
:
573 case SHADER_OPCODE_SIN
:
575 case SHADER_OPCODE_COS
:
578 case SHADER_OPCODE_TEX
:
580 case SHADER_OPCODE_TEX_LOGICAL
:
581 return "tex_logical";
582 case SHADER_OPCODE_TXD
:
584 case SHADER_OPCODE_TXD_LOGICAL
:
585 return "txd_logical";
586 case SHADER_OPCODE_TXF
:
588 case SHADER_OPCODE_TXF_LOGICAL
:
589 return "txf_logical";
590 case SHADER_OPCODE_TXL
:
592 case SHADER_OPCODE_TXL_LOGICAL
:
593 return "txl_logical";
594 case SHADER_OPCODE_TXS
:
596 case SHADER_OPCODE_TXS_LOGICAL
:
597 return "txs_logical";
600 case FS_OPCODE_TXB_LOGICAL
:
601 return "txb_logical";
602 case SHADER_OPCODE_TXF_CMS
:
604 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
605 return "txf_cms_logical";
606 case SHADER_OPCODE_TXF_UMS
:
608 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
609 return "txf_ums_logical";
610 case SHADER_OPCODE_TXF_MCS
:
612 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
613 return "txf_mcs_logical";
614 case SHADER_OPCODE_LOD
:
616 case SHADER_OPCODE_LOD_LOGICAL
:
617 return "lod_logical";
618 case SHADER_OPCODE_TG4
:
620 case SHADER_OPCODE_TG4_LOGICAL
:
621 return "tg4_logical";
622 case SHADER_OPCODE_TG4_OFFSET
:
624 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
625 return "tg4_offset_logical";
627 case SHADER_OPCODE_SHADER_TIME_ADD
:
628 return "shader_time_add";
630 case SHADER_OPCODE_UNTYPED_ATOMIC
:
631 return "untyped_atomic";
632 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
633 return "untyped_atomic_logical";
634 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
635 return "untyped_surface_read";
636 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
637 return "untyped_surface_read_logical";
638 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
639 return "untyped_surface_write";
640 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
641 return "untyped_surface_write_logical";
642 case SHADER_OPCODE_TYPED_ATOMIC
:
643 return "typed_atomic";
644 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
645 return "typed_atomic_logical";
646 case SHADER_OPCODE_TYPED_SURFACE_READ
:
647 return "typed_surface_read";
648 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
649 return "typed_surface_read_logical";
650 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
651 return "typed_surface_write";
652 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
653 return "typed_surface_write_logical";
654 case SHADER_OPCODE_MEMORY_FENCE
:
655 return "memory_fence";
657 case SHADER_OPCODE_LOAD_PAYLOAD
:
658 return "load_payload";
660 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
661 return "gen4_scratch_read";
662 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
663 return "gen4_scratch_write";
664 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
665 return "gen7_scratch_read";
666 case SHADER_OPCODE_URB_WRITE_SIMD8
:
667 return "gen8_urb_write_simd8";
669 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
670 return "find_live_channel";
671 case SHADER_OPCODE_BROADCAST
:
674 case VEC4_OPCODE_MOV_BYTES
:
676 case VEC4_OPCODE_PACK_BYTES
:
678 case VEC4_OPCODE_UNPACK_UNIFORM
:
679 return "unpack_uniform";
681 case FS_OPCODE_DDX_COARSE
:
683 case FS_OPCODE_DDX_FINE
:
685 case FS_OPCODE_DDY_COARSE
:
687 case FS_OPCODE_DDY_FINE
:
690 case FS_OPCODE_CINTERP
:
692 case FS_OPCODE_LINTERP
:
695 case FS_OPCODE_PIXEL_X
:
697 case FS_OPCODE_PIXEL_Y
:
700 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
701 return "uniform_pull_const";
702 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
703 return "uniform_pull_const_gen7";
704 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
705 return "varying_pull_const";
706 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
707 return "varying_pull_const_gen7";
709 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
710 return "mov_dispatch_to_flags";
711 case FS_OPCODE_DISCARD_JUMP
:
712 return "discard_jump";
714 case FS_OPCODE_SET_SAMPLE_ID
:
715 return "set_sample_id";
716 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
717 return "set_simd4x2_offset";
719 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
720 return "pack_half_2x16_split";
721 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
722 return "unpack_half_2x16_split_x";
723 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
724 return "unpack_half_2x16_split_y";
726 case FS_OPCODE_PLACEHOLDER_HALT
:
727 return "placeholder_halt";
729 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
730 return "interp_centroid";
731 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
732 return "interp_sample";
733 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
734 return "interp_shared_offset";
735 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
736 return "interp_per_slot_offset";
738 case VS_OPCODE_URB_WRITE
:
739 return "vs_urb_write";
740 case VS_OPCODE_PULL_CONSTANT_LOAD
:
741 return "pull_constant_load";
742 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
743 return "pull_constant_load_gen7";
745 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
746 return "set_simd4x2_header_gen9";
748 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
749 return "unpack_flags_simd4x2";
751 case GS_OPCODE_URB_WRITE
:
752 return "gs_urb_write";
753 case GS_OPCODE_URB_WRITE_ALLOCATE
:
754 return "gs_urb_write_allocate";
755 case GS_OPCODE_THREAD_END
:
756 return "gs_thread_end";
757 case GS_OPCODE_SET_WRITE_OFFSET
:
758 return "set_write_offset";
759 case GS_OPCODE_SET_VERTEX_COUNT
:
760 return "set_vertex_count";
761 case GS_OPCODE_SET_DWORD_2
:
762 return "set_dword_2";
763 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
764 return "prepare_channel_masks";
765 case GS_OPCODE_SET_CHANNEL_MASKS
:
766 return "set_channel_masks";
767 case GS_OPCODE_GET_INSTANCE_ID
:
768 return "get_instance_id";
769 case GS_OPCODE_FF_SYNC
:
771 case GS_OPCODE_SET_PRIMITIVE_ID
:
772 return "set_primitive_id";
773 case GS_OPCODE_SVB_WRITE
:
774 return "gs_svb_write";
775 case GS_OPCODE_SVB_SET_DST_INDEX
:
776 return "gs_svb_set_dst_index";
777 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
778 return "gs_ff_sync_set_primitives";
779 case CS_OPCODE_CS_TERMINATE
:
780 return "cs_terminate";
781 case SHADER_OPCODE_BARRIER
:
783 case SHADER_OPCODE_MULH
:
787 unreachable("not reached");
791 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
797 } imm
= { reg
->dw1
.ud
}, sat_imm
= { 0 };
800 case BRW_REGISTER_TYPE_UD
:
801 case BRW_REGISTER_TYPE_D
:
802 case BRW_REGISTER_TYPE_UQ
:
803 case BRW_REGISTER_TYPE_Q
:
806 case BRW_REGISTER_TYPE_UW
:
807 sat_imm
.ud
= CLAMP(imm
.ud
, 0, USHRT_MAX
);
809 case BRW_REGISTER_TYPE_W
:
810 sat_imm
.d
= CLAMP(imm
.d
, SHRT_MIN
, SHRT_MAX
);
812 case BRW_REGISTER_TYPE_F
:
813 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
815 case BRW_REGISTER_TYPE_UB
:
816 case BRW_REGISTER_TYPE_B
:
817 unreachable("no UB/B immediates");
818 case BRW_REGISTER_TYPE_V
:
819 case BRW_REGISTER_TYPE_UV
:
820 case BRW_REGISTER_TYPE_VF
:
821 unreachable("unimplemented: saturate vector immediate");
822 case BRW_REGISTER_TYPE_DF
:
823 case BRW_REGISTER_TYPE_HF
:
824 unreachable("unimplemented: saturate DF/HF immediate");
827 if (imm
.ud
!= sat_imm
.ud
) {
828 reg
->dw1
.ud
= sat_imm
.ud
;
835 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
838 case BRW_REGISTER_TYPE_D
:
839 case BRW_REGISTER_TYPE_UD
:
840 reg
->dw1
.d
= -reg
->dw1
.d
;
842 case BRW_REGISTER_TYPE_W
:
843 case BRW_REGISTER_TYPE_UW
:
844 reg
->dw1
.d
= -(int16_t)reg
->dw1
.ud
;
846 case BRW_REGISTER_TYPE_F
:
847 reg
->dw1
.f
= -reg
->dw1
.f
;
849 case BRW_REGISTER_TYPE_VF
:
850 reg
->dw1
.ud
^= 0x80808080;
852 case BRW_REGISTER_TYPE_UB
:
853 case BRW_REGISTER_TYPE_B
:
854 unreachable("no UB/B immediates");
855 case BRW_REGISTER_TYPE_UV
:
856 case BRW_REGISTER_TYPE_V
:
857 assert(!"unimplemented: negate UV/V immediate");
858 case BRW_REGISTER_TYPE_UQ
:
859 case BRW_REGISTER_TYPE_Q
:
860 assert(!"unimplemented: negate UQ/Q immediate");
861 case BRW_REGISTER_TYPE_DF
:
862 case BRW_REGISTER_TYPE_HF
:
863 assert(!"unimplemented: negate DF/HF immediate");
870 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
873 case BRW_REGISTER_TYPE_D
:
874 reg
->dw1
.d
= abs(reg
->dw1
.d
);
876 case BRW_REGISTER_TYPE_W
:
877 reg
->dw1
.d
= abs((int16_t)reg
->dw1
.ud
);
879 case BRW_REGISTER_TYPE_F
:
880 reg
->dw1
.f
= fabsf(reg
->dw1
.f
);
882 case BRW_REGISTER_TYPE_VF
:
883 reg
->dw1
.ud
&= ~0x80808080;
885 case BRW_REGISTER_TYPE_UB
:
886 case BRW_REGISTER_TYPE_B
:
887 unreachable("no UB/B immediates");
888 case BRW_REGISTER_TYPE_UQ
:
889 case BRW_REGISTER_TYPE_UD
:
890 case BRW_REGISTER_TYPE_UW
:
891 case BRW_REGISTER_TYPE_UV
:
892 /* Presumably the absolute value modifier on an unsigned source is a
893 * nop, but it would be nice to confirm.
895 assert(!"unimplemented: abs unsigned immediate");
896 case BRW_REGISTER_TYPE_V
:
897 assert(!"unimplemented: abs V immediate");
898 case BRW_REGISTER_TYPE_Q
:
899 assert(!"unimplemented: abs Q immediate");
900 case BRW_REGISTER_TYPE_DF
:
901 case BRW_REGISTER_TYPE_HF
:
902 assert(!"unimplemented: abs DF/HF immediate");
908 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
911 struct gl_shader_program
*shader_prog
,
912 struct gl_program
*prog
,
913 struct brw_stage_prog_data
*stage_prog_data
,
914 gl_shader_stage stage
)
915 : compiler(compiler
),
917 devinfo(compiler
->devinfo
),
919 (struct brw_shader
*)shader_prog
->_LinkedShaders
[stage
] : NULL
),
920 shader_prog(shader_prog
),
922 stage_prog_data(stage_prog_data
),
927 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
928 stage_name
= _mesa_shader_stage_to_string(stage
);
929 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
933 backend_reg::is_zero() const
938 return fixed_hw_reg
.dw1
.d
== 0;
942 backend_reg::is_one() const
947 return type
== BRW_REGISTER_TYPE_F
948 ? fixed_hw_reg
.dw1
.f
== 1.0
949 : fixed_hw_reg
.dw1
.d
== 1;
953 backend_reg::is_negative_one() const
959 case BRW_REGISTER_TYPE_F
:
960 return fixed_hw_reg
.dw1
.f
== -1.0;
961 case BRW_REGISTER_TYPE_D
:
962 return fixed_hw_reg
.dw1
.d
== -1;
969 backend_reg::is_null() const
971 return file
== HW_REG
&&
972 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
973 fixed_hw_reg
.nr
== BRW_ARF_NULL
;
978 backend_reg::is_accumulator() const
980 return file
== HW_REG
&&
981 fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
982 fixed_hw_reg
.nr
== BRW_ARF_ACCUMULATOR
;
986 backend_reg::in_range(const backend_reg
&r
, unsigned n
) const
988 return (file
== r
.file
&&
990 reg_offset
>= r
.reg_offset
&&
991 reg_offset
< r
.reg_offset
+ n
);
995 backend_instruction::is_commutative() const
1000 case BRW_OPCODE_XOR
:
1001 case BRW_OPCODE_ADD
:
1002 case BRW_OPCODE_MUL
:
1003 case SHADER_OPCODE_MULH
:
1005 case BRW_OPCODE_SEL
:
1006 /* MIN and MAX are commutative. */
1007 if (conditional_mod
== BRW_CONDITIONAL_GE
||
1008 conditional_mod
== BRW_CONDITIONAL_L
) {
1018 backend_instruction::is_3src() const
1020 return opcode
< ARRAY_SIZE(opcode_descs
) && opcode_descs
[opcode
].nsrc
== 3;
1024 backend_instruction::is_tex() const
1026 return (opcode
== SHADER_OPCODE_TEX
||
1027 opcode
== FS_OPCODE_TXB
||
1028 opcode
== SHADER_OPCODE_TXD
||
1029 opcode
== SHADER_OPCODE_TXF
||
1030 opcode
== SHADER_OPCODE_TXF_CMS
||
1031 opcode
== SHADER_OPCODE_TXF_UMS
||
1032 opcode
== SHADER_OPCODE_TXF_MCS
||
1033 opcode
== SHADER_OPCODE_TXL
||
1034 opcode
== SHADER_OPCODE_TXS
||
1035 opcode
== SHADER_OPCODE_LOD
||
1036 opcode
== SHADER_OPCODE_TG4
||
1037 opcode
== SHADER_OPCODE_TG4_OFFSET
);
1041 backend_instruction::is_math() const
1043 return (opcode
== SHADER_OPCODE_RCP
||
1044 opcode
== SHADER_OPCODE_RSQ
||
1045 opcode
== SHADER_OPCODE_SQRT
||
1046 opcode
== SHADER_OPCODE_EXP2
||
1047 opcode
== SHADER_OPCODE_LOG2
||
1048 opcode
== SHADER_OPCODE_SIN
||
1049 opcode
== SHADER_OPCODE_COS
||
1050 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
1051 opcode
== SHADER_OPCODE_INT_REMAINDER
||
1052 opcode
== SHADER_OPCODE_POW
);
1056 backend_instruction::is_control_flow() const
1060 case BRW_OPCODE_WHILE
:
1062 case BRW_OPCODE_ELSE
:
1063 case BRW_OPCODE_ENDIF
:
1064 case BRW_OPCODE_BREAK
:
1065 case BRW_OPCODE_CONTINUE
:
1073 backend_instruction::can_do_source_mods() const
1076 case BRW_OPCODE_ADDC
:
1077 case BRW_OPCODE_BFE
:
1078 case BRW_OPCODE_BFI1
:
1079 case BRW_OPCODE_BFI2
:
1080 case BRW_OPCODE_BFREV
:
1081 case BRW_OPCODE_CBIT
:
1082 case BRW_OPCODE_FBH
:
1083 case BRW_OPCODE_FBL
:
1084 case BRW_OPCODE_SUBB
:
1092 backend_instruction::can_do_saturate() const
1095 case BRW_OPCODE_ADD
:
1096 case BRW_OPCODE_ASR
:
1097 case BRW_OPCODE_AVG
:
1098 case BRW_OPCODE_DP2
:
1099 case BRW_OPCODE_DP3
:
1100 case BRW_OPCODE_DP4
:
1101 case BRW_OPCODE_DPH
:
1102 case BRW_OPCODE_F16TO32
:
1103 case BRW_OPCODE_F32TO16
:
1104 case BRW_OPCODE_LINE
:
1105 case BRW_OPCODE_LRP
:
1106 case BRW_OPCODE_MAC
:
1107 case BRW_OPCODE_MAD
:
1108 case BRW_OPCODE_MATH
:
1109 case BRW_OPCODE_MOV
:
1110 case BRW_OPCODE_MUL
:
1111 case SHADER_OPCODE_MULH
:
1112 case BRW_OPCODE_PLN
:
1113 case BRW_OPCODE_RNDD
:
1114 case BRW_OPCODE_RNDE
:
1115 case BRW_OPCODE_RNDU
:
1116 case BRW_OPCODE_RNDZ
:
1117 case BRW_OPCODE_SEL
:
1118 case BRW_OPCODE_SHL
:
1119 case BRW_OPCODE_SHR
:
1120 case FS_OPCODE_LINTERP
:
1121 case SHADER_OPCODE_COS
:
1122 case SHADER_OPCODE_EXP2
:
1123 case SHADER_OPCODE_LOG2
:
1124 case SHADER_OPCODE_POW
:
1125 case SHADER_OPCODE_RCP
:
1126 case SHADER_OPCODE_RSQ
:
1127 case SHADER_OPCODE_SIN
:
1128 case SHADER_OPCODE_SQRT
:
1136 backend_instruction::can_do_cmod() const
1139 case BRW_OPCODE_ADD
:
1140 case BRW_OPCODE_ADDC
:
1141 case BRW_OPCODE_AND
:
1142 case BRW_OPCODE_ASR
:
1143 case BRW_OPCODE_AVG
:
1144 case BRW_OPCODE_CMP
:
1145 case BRW_OPCODE_CMPN
:
1146 case BRW_OPCODE_DP2
:
1147 case BRW_OPCODE_DP3
:
1148 case BRW_OPCODE_DP4
:
1149 case BRW_OPCODE_DPH
:
1150 case BRW_OPCODE_F16TO32
:
1151 case BRW_OPCODE_F32TO16
:
1152 case BRW_OPCODE_FRC
:
1153 case BRW_OPCODE_LINE
:
1154 case BRW_OPCODE_LRP
:
1155 case BRW_OPCODE_LZD
:
1156 case BRW_OPCODE_MAC
:
1157 case BRW_OPCODE_MACH
:
1158 case BRW_OPCODE_MAD
:
1159 case BRW_OPCODE_MOV
:
1160 case BRW_OPCODE_MUL
:
1161 case BRW_OPCODE_NOT
:
1163 case BRW_OPCODE_PLN
:
1164 case BRW_OPCODE_RNDD
:
1165 case BRW_OPCODE_RNDE
:
1166 case BRW_OPCODE_RNDU
:
1167 case BRW_OPCODE_RNDZ
:
1168 case BRW_OPCODE_SAD2
:
1169 case BRW_OPCODE_SADA2
:
1170 case BRW_OPCODE_SHL
:
1171 case BRW_OPCODE_SHR
:
1172 case BRW_OPCODE_SUBB
:
1173 case BRW_OPCODE_XOR
:
1174 case FS_OPCODE_CINTERP
:
1175 case FS_OPCODE_LINTERP
:
1183 backend_instruction::reads_accumulator_implicitly() const
1186 case BRW_OPCODE_MAC
:
1187 case BRW_OPCODE_MACH
:
1188 case BRW_OPCODE_SADA2
:
1196 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const
1198 return writes_accumulator
||
1199 (devinfo
->gen
< 6 &&
1200 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
1201 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
1202 opcode
!= FS_OPCODE_CINTERP
)));
1206 backend_instruction::has_side_effects() const
1209 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1210 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
1211 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1212 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1213 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
1214 case SHADER_OPCODE_TYPED_ATOMIC
:
1215 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
1216 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1217 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
1218 case SHADER_OPCODE_MEMORY_FENCE
:
1219 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1220 case FS_OPCODE_FB_WRITE
:
1221 case SHADER_OPCODE_BARRIER
:
1230 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1233 foreach_inst_in_block (backend_instruction
, i
, block
) {
1243 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1245 for (bblock_t
*block_iter
= start_block
->next();
1246 !block_iter
->link
.is_tail_sentinel();
1247 block_iter
= block_iter
->next()) {
1248 block_iter
->start_ip
+= ip_adjustment
;
1249 block_iter
->end_ip
+= ip_adjustment
;
1254 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1256 if (!this->is_head_sentinel())
1257 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1261 adjust_later_block_ips(block
, 1);
1263 exec_node::insert_after(inst
);
1267 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1269 if (!this->is_tail_sentinel())
1270 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1274 adjust_later_block_ips(block
, 1);
1276 exec_node::insert_before(inst
);
1280 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1282 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1284 unsigned num_inst
= list
->length();
1286 block
->end_ip
+= num_inst
;
1288 adjust_later_block_ips(block
, num_inst
);
1290 exec_node::insert_before(list
);
1294 backend_instruction::remove(bblock_t
*block
)
1296 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1298 adjust_later_block_ips(block
, -1);
1300 if (block
->start_ip
== block
->end_ip
) {
1301 block
->cfg
->remove_block(block
);
1306 exec_node::remove();
1310 backend_shader::dump_instructions()
1312 dump_instructions(NULL
);
1316 backend_shader::dump_instructions(const char *name
)
1318 FILE *file
= stderr
;
1319 if (name
&& geteuid() != 0) {
1320 file
= fopen(name
, "w");
1327 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1328 fprintf(file
, "%4d: ", ip
++);
1329 dump_instruction(inst
, file
);
1333 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1334 fprintf(file
, "%4d: ", ip
++);
1335 dump_instruction(inst
, file
);
1339 if (file
!= stderr
) {
1345 backend_shader::calculate_cfg()
1349 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1353 backend_shader::invalidate_cfg()
1355 ralloc_free(this->cfg
);
1360 * Sets up the starting offsets for the groups of binding table entries
1361 * commong to all pipeline stages.
1363 * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1364 * unused but also make sure that addition of small offsets to them will
1365 * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1368 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset
)
1370 int num_textures
= _mesa_fls(prog
->SamplersUsed
);
1372 stage_prog_data
->binding_table
.texture_start
= next_binding_table_offset
;
1373 next_binding_table_offset
+= num_textures
;
1376 stage_prog_data
->binding_table
.ubo_start
= next_binding_table_offset
;
1377 next_binding_table_offset
+= shader
->base
.NumUniformBlocks
;
1379 stage_prog_data
->binding_table
.ubo_start
= 0xd0d0d0d0;
1382 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1383 stage_prog_data
->binding_table
.shader_time_start
= next_binding_table_offset
;
1384 next_binding_table_offset
++;
1386 stage_prog_data
->binding_table
.shader_time_start
= 0xd0d0d0d0;
1389 if (prog
->UsesGather
) {
1390 if (devinfo
->gen
>= 8) {
1391 stage_prog_data
->binding_table
.gather_texture_start
=
1392 stage_prog_data
->binding_table
.texture_start
;
1394 stage_prog_data
->binding_table
.gather_texture_start
= next_binding_table_offset
;
1395 next_binding_table_offset
+= num_textures
;
1398 stage_prog_data
->binding_table
.gather_texture_start
= 0xd0d0d0d0;
1401 if (shader_prog
&& shader_prog
->NumAtomicBuffers
) {
1402 stage_prog_data
->binding_table
.abo_start
= next_binding_table_offset
;
1403 next_binding_table_offset
+= shader_prog
->NumAtomicBuffers
;
1405 stage_prog_data
->binding_table
.abo_start
= 0xd0d0d0d0;
1408 if (shader
&& shader
->base
.NumImages
) {
1409 stage_prog_data
->binding_table
.image_start
= next_binding_table_offset
;
1410 next_binding_table_offset
+= shader
->base
.NumImages
;
1412 stage_prog_data
->binding_table
.image_start
= 0xd0d0d0d0;
1415 /* This may or may not be used depending on how the compile goes. */
1416 stage_prog_data
->binding_table
.pull_constants_start
= next_binding_table_offset
;
1417 next_binding_table_offset
++;
1419 assert(next_binding_table_offset
<= BRW_MAX_SURFACES
);
1421 /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1425 backend_shader::setup_image_uniform_values(unsigned param_offset
,
1426 const gl_uniform_storage
*storage
)
1428 const unsigned stage
= _mesa_program_enum_to_shader_stage(prog
->Target
);
1430 for (unsigned i
= 0; i
< MAX2(storage
->array_elements
, 1); i
++) {
1431 const unsigned image_idx
= storage
->image
[stage
].index
+ i
;
1432 const brw_image_param
*param
= &stage_prog_data
->image_param
[image_idx
];
1434 /* Upload the brw_image_param structure. The order is expected to match
1435 * the BRW_IMAGE_PARAM_*_OFFSET defines.
1437 setup_vec4_uniform_value(param_offset
+ BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET
,
1438 (const gl_constant_value
*)¶m
->surface_idx
, 1);
1439 setup_vec4_uniform_value(param_offset
+ BRW_IMAGE_PARAM_OFFSET_OFFSET
,
1440 (const gl_constant_value
*)param
->offset
, 2);
1441 setup_vec4_uniform_value(param_offset
+ BRW_IMAGE_PARAM_SIZE_OFFSET
,
1442 (const gl_constant_value
*)param
->size
, 3);
1443 setup_vec4_uniform_value(param_offset
+ BRW_IMAGE_PARAM_STRIDE_OFFSET
,
1444 (const gl_constant_value
*)param
->stride
, 4);
1445 setup_vec4_uniform_value(param_offset
+ BRW_IMAGE_PARAM_TILING_OFFSET
,
1446 (const gl_constant_value
*)param
->tiling
, 3);
1447 setup_vec4_uniform_value(param_offset
+ BRW_IMAGE_PARAM_SWIZZLING_OFFSET
,
1448 (const gl_constant_value
*)param
->swizzling
, 2);
1449 param_offset
+= BRW_IMAGE_PARAM_SIZE
;
1451 brw_mark_surface_used(
1453 stage_prog_data
->binding_table
.image_start
+ image_idx
);