src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_VERTEX:
  83       return compiler->scalar_vs;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 struct brw_compiler *
  90 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  91 {
  92    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  93
  94    compiler->devinfo = devinfo;
  95    compiler->shader_debug_log = shader_debug_log_mesa;
  96    compiler->shader_perf_log = shader_perf_log_mesa;
  97
  98    brw_fs_alloc_reg_sets(compiler);
  99    brw_vec4_alloc_reg_set(compiler);
 100
 101    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 102       compiler->scalar_vs = true;
 103
 104    nir_shader_compiler_options *nir_options =
 105       rzalloc(compiler, nir_shader_compiler_options);
 106    nir_options->native_integers = true;
 107    /* In order to help allow for better CSE at the NIR level we tell NIR
 108     * to split all ffma instructions during opt_algebraic and we then
 109     * re-combine them as a later step.
 110     */
 111    nir_options->lower_ffma = true;
 112    nir_options->lower_sub = true;
 113    nir_options->lower_fdiv = true;
 114
 115    /* In the vec4 backend, our dpN instruction replicates its result to all
 116     * the components of a vec4.  We would like NIR to give us replicated fdot
 117     * instructions because it can optimize better for us.
 118     *
 119     * For the FS backend, it should be lowered away by the scalarizing pass so
 120     * we should never see fdot anyway.
 121     */
 122    nir_options->fdot_replicates = true;
 123
 124    /* We want the GLSL compiler to emit code that uses condition codes */
 125    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 126       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 127       compiler->glsl_compiler_options[i].MaxIfDepth =
 128          devinfo->gen < 6 ? 16 : UINT_MAX;
 129
 130       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 131       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 132       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 133       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 134       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 135       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 136
 137       bool is_scalar = is_scalar_shader_stage(compiler, i);
 138
 139       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 140       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 141       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 142
 143       /* !ARB_gpu_shader5 */
 144       if (devinfo->gen < 7)
 145          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 146
 147       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 148    }
 149
 150    return compiler;
 151 }
 152
 153 struct gl_shader *
 154 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 155 {
 156    struct brw_shader *shader;
 157
 158    shader = rzalloc(NULL, struct brw_shader);
 159    if (shader) {
 160       shader->base.Type = type;
 161       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 162       shader->base.Name = name;
 163       _mesa_init_shader(ctx, &shader->base);
 164    }
 165
 166    return &shader->base;
 167 }
 168
 169 void
 170 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 171                       unsigned surf_index)
 172 {
 173    assert(surf_index < BRW_MAX_SURFACES);
 174
 175    prog_data->binding_table.size_bytes =
 176       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 177 }
 178
 179 enum brw_reg_type
 180 brw_type_for_base_type(const struct glsl_type *type)
 181 {
 182    switch (type->base_type) {
 183    case GLSL_TYPE_FLOAT:
 184       return BRW_REGISTER_TYPE_F;
 185    case GLSL_TYPE_INT:
 186    case GLSL_TYPE_BOOL:
 187    case GLSL_TYPE_SUBROUTINE:
 188       return BRW_REGISTER_TYPE_D;
 189    case GLSL_TYPE_UINT:
 190       return BRW_REGISTER_TYPE_UD;
 191    case GLSL_TYPE_ARRAY:
 192       return brw_type_for_base_type(type->fields.array);
 193    case GLSL_TYPE_STRUCT:
 194    case GLSL_TYPE_SAMPLER:
 195    case GLSL_TYPE_ATOMIC_UINT:
 196       /* These should be overridden with the type of the member when
 197        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 198        * way to trip up if we don't.
 199        */
 200       return BRW_REGISTER_TYPE_UD;
 201    case GLSL_TYPE_IMAGE:
 202       return BRW_REGISTER_TYPE_UD;
 203    case GLSL_TYPE_VOID:
 204    case GLSL_TYPE_ERROR:
 205    case GLSL_TYPE_INTERFACE:
 206    case GLSL_TYPE_DOUBLE:
 207    case GLSL_TYPE_FUNCTION:
 208       unreachable("not reached");
 209    }
 210
 211    return BRW_REGISTER_TYPE_F;
 212 }
 213
 214 enum brw_conditional_mod
 215 brw_conditional_for_comparison(unsigned int op)
 216 {
 217    switch (op) {
 218    case ir_binop_less:
 219       return BRW_CONDITIONAL_L;
 220    case ir_binop_greater:
 221       return BRW_CONDITIONAL_G;
 222    case ir_binop_lequal:
 223       return BRW_CONDITIONAL_LE;
 224    case ir_binop_gequal:
 225       return BRW_CONDITIONAL_GE;
 226    case ir_binop_equal:
 227    case ir_binop_all_equal: /* same as equal for scalars */
 228       return BRW_CONDITIONAL_Z;
 229    case ir_binop_nequal:
 230    case ir_binop_any_nequal: /* same as nequal for scalars */
 231       return BRW_CONDITIONAL_NZ;
 232    default:
 233       unreachable("not reached: bad operation for comparison");
 234    }
 235 }
 236
 237 uint32_t
 238 brw_math_function(enum opcode op)
 239 {
 240    switch (op) {
 241    case SHADER_OPCODE_RCP:
 242       return BRW_MATH_FUNCTION_INV;
 243    case SHADER_OPCODE_RSQ:
 244       return BRW_MATH_FUNCTION_RSQ;
 245    case SHADER_OPCODE_SQRT:
 246       return BRW_MATH_FUNCTION_SQRT;
 247    case SHADER_OPCODE_EXP2:
 248       return BRW_MATH_FUNCTION_EXP;
 249    case SHADER_OPCODE_LOG2:
 250       return BRW_MATH_FUNCTION_LOG;
 251    case SHADER_OPCODE_POW:
 252       return BRW_MATH_FUNCTION_POW;
 253    case SHADER_OPCODE_SIN:
 254       return BRW_MATH_FUNCTION_SIN;
 255    case SHADER_OPCODE_COS:
 256       return BRW_MATH_FUNCTION_COS;
 257    case SHADER_OPCODE_INT_QUOTIENT:
 258       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 259    case SHADER_OPCODE_INT_REMAINDER:
 260       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 261    default:
 262       unreachable("not reached: unknown math function");
 263    }
 264 }
 265
 266 uint32_t
 267 brw_texture_offset(int *offsets, unsigned num_components)
 268 {
 269    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 270
 271    /* Combine all three offsets into a single unsigned dword:
 272     *
 273     *    bits 11:8 - U Offset (X component)
 274     *    bits  7:4 - V Offset (Y component)
 275     *    bits  3:0 - R Offset (Z component)
 276     */
 277    unsigned offset_bits = 0;
 278    for (unsigned i = 0; i < num_components; i++) {
 279       const unsigned shift = 4 * (2 - i);
 280       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 281    }
 282    return offset_bits;
 283 }
 284
 285 const char *
 286 brw_instruction_name(enum opcode op)
 287 {
 288    switch (op) {
 289    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 290       assert(opcode_descs[op].name);
 291       return opcode_descs[op].name;
 292    case FS_OPCODE_FB_WRITE:
 293       return "fb_write";
 294    case FS_OPCODE_FB_WRITE_LOGICAL:
 295       return "fb_write_logical";
 296    case FS_OPCODE_BLORP_FB_WRITE:
 297       return "blorp_fb_write";
 298    case FS_OPCODE_REP_FB_WRITE:
 299       return "rep_fb_write";
 300
 301    case SHADER_OPCODE_RCP:
 302       return "rcp";
 303    case SHADER_OPCODE_RSQ:
 304       return "rsq";
 305    case SHADER_OPCODE_SQRT:
 306       return "sqrt";
 307    case SHADER_OPCODE_EXP2:
 308       return "exp2";
 309    case SHADER_OPCODE_LOG2:
 310       return "log2";
 311    case SHADER_OPCODE_POW:
 312       return "pow";
 313    case SHADER_OPCODE_INT_QUOTIENT:
 314       return "int_quot";
 315    case SHADER_OPCODE_INT_REMAINDER:
 316       return "int_rem";
 317    case SHADER_OPCODE_SIN:
 318       return "sin";
 319    case SHADER_OPCODE_COS:
 320       return "cos";
 321
 322    case SHADER_OPCODE_TEX:
 323       return "tex";
 324    case SHADER_OPCODE_TEX_LOGICAL:
 325       return "tex_logical";
 326    case SHADER_OPCODE_TXD:
 327       return "txd";
 328    case SHADER_OPCODE_TXD_LOGICAL:
 329       return "txd_logical";
 330    case SHADER_OPCODE_TXF:
 331       return "txf";
 332    case SHADER_OPCODE_TXF_LOGICAL:
 333       return "txf_logical";
 334    case SHADER_OPCODE_TXL:
 335       return "txl";
 336    case SHADER_OPCODE_TXL_LOGICAL:
 337       return "txl_logical";
 338    case SHADER_OPCODE_TXS:
 339       return "txs";
 340    case SHADER_OPCODE_TXS_LOGICAL:
 341       return "txs_logical";
 342    case FS_OPCODE_TXB:
 343       return "txb";
 344    case FS_OPCODE_TXB_LOGICAL:
 345       return "txb_logical";
 346    case SHADER_OPCODE_TXF_CMS:
 347       return "txf_cms";
 348    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 349       return "txf_cms_logical";
 350    case SHADER_OPCODE_TXF_UMS:
 351       return "txf_ums";
 352    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 353       return "txf_ums_logical";
 354    case SHADER_OPCODE_TXF_MCS:
 355       return "txf_mcs";
 356    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 357       return "txf_mcs_logical";
 358    case SHADER_OPCODE_LOD:
 359       return "lod";
 360    case SHADER_OPCODE_LOD_LOGICAL:
 361       return "lod_logical";
 362    case SHADER_OPCODE_TG4:
 363       return "tg4";
 364    case SHADER_OPCODE_TG4_LOGICAL:
 365       return "tg4_logical";
 366    case SHADER_OPCODE_TG4_OFFSET:
 367       return "tg4_offset";
 368    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 369       return "tg4_offset_logical";
 370    case SHADER_OPCODE_SAMPLEINFO:
 371       return "sampleinfo";
 372
 373    case SHADER_OPCODE_SHADER_TIME_ADD:
 374       return "shader_time_add";
 375
 376    case SHADER_OPCODE_UNTYPED_ATOMIC:
 377       return "untyped_atomic";
 378    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 379       return "untyped_atomic_logical";
 380    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 381       return "untyped_surface_read";
 382    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 383       return "untyped_surface_read_logical";
 384    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 385       return "untyped_surface_write";
 386    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 387       return "untyped_surface_write_logical";
 388    case SHADER_OPCODE_TYPED_ATOMIC:
 389       return "typed_atomic";
 390    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 391       return "typed_atomic_logical";
 392    case SHADER_OPCODE_TYPED_SURFACE_READ:
 393       return "typed_surface_read";
 394    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 395       return "typed_surface_read_logical";
 396    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 397       return "typed_surface_write";
 398    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 399       return "typed_surface_write_logical";
 400    case SHADER_OPCODE_MEMORY_FENCE:
 401       return "memory_fence";
 402
 403    case SHADER_OPCODE_LOAD_PAYLOAD:
 404       return "load_payload";
 405
 406    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 407       return "gen4_scratch_read";
 408    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 409       return "gen4_scratch_write";
 410    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 411       return "gen7_scratch_read";
 412    case SHADER_OPCODE_URB_WRITE_SIMD8:
 413       return "gen8_urb_write_simd8";
 414
 415    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 416       return "find_live_channel";
 417    case SHADER_OPCODE_BROADCAST:
 418       return "broadcast";
 419
 420    case VEC4_OPCODE_MOV_BYTES:
 421       return "mov_bytes";
 422    case VEC4_OPCODE_PACK_BYTES:
 423       return "pack_bytes";
 424    case VEC4_OPCODE_UNPACK_UNIFORM:
 425       return "unpack_uniform";
 426
 427    case FS_OPCODE_DDX_COARSE:
 428       return "ddx_coarse";
 429    case FS_OPCODE_DDX_FINE:
 430       return "ddx_fine";
 431    case FS_OPCODE_DDY_COARSE:
 432       return "ddy_coarse";
 433    case FS_OPCODE_DDY_FINE:
 434       return "ddy_fine";
 435
 436    case FS_OPCODE_CINTERP:
 437       return "cinterp";
 438    case FS_OPCODE_LINTERP:
 439       return "linterp";
 440
 441    case FS_OPCODE_PIXEL_X:
 442       return "pixel_x";
 443    case FS_OPCODE_PIXEL_Y:
 444       return "pixel_y";
 445
 446    case FS_OPCODE_GET_BUFFER_SIZE:
 447       return "fs_get_buffer_size";
 448
 449    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 450       return "uniform_pull_const";
 451    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 452       return "uniform_pull_const_gen7";
 453    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 454       return "varying_pull_const";
 455    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 456       return "varying_pull_const_gen7";
 457
 458    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 459       return "mov_dispatch_to_flags";
 460    case FS_OPCODE_DISCARD_JUMP:
 461       return "discard_jump";
 462
 463    case FS_OPCODE_SET_SAMPLE_ID:
 464       return "set_sample_id";
 465    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 466       return "set_simd4x2_offset";
 467
 468    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 469       return "pack_half_2x16_split";
 470    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 471       return "unpack_half_2x16_split_x";
 472    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 473       return "unpack_half_2x16_split_y";
 474
 475    case FS_OPCODE_PLACEHOLDER_HALT:
 476       return "placeholder_halt";
 477
 478    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 479       return "interp_centroid";
 480    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 481       return "interp_sample";
 482    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 483       return "interp_shared_offset";
 484    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 485       return "interp_per_slot_offset";
 486
 487    case VS_OPCODE_URB_WRITE:
 488       return "vs_urb_write";
 489    case VS_OPCODE_PULL_CONSTANT_LOAD:
 490       return "pull_constant_load";
 491    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 492       return "pull_constant_load_gen7";
 493
 494    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 495       return "set_simd4x2_header_gen9";
 496
 497    case VS_OPCODE_GET_BUFFER_SIZE:
 498       return "vs_get_buffer_size";
 499
 500    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 501       return "unpack_flags_simd4x2";
 502
 503    case GS_OPCODE_URB_WRITE:
 504       return "gs_urb_write";
 505    case GS_OPCODE_URB_WRITE_ALLOCATE:
 506       return "gs_urb_write_allocate";
 507    case GS_OPCODE_THREAD_END:
 508       return "gs_thread_end";
 509    case GS_OPCODE_SET_WRITE_OFFSET:
 510       return "set_write_offset";
 511    case GS_OPCODE_SET_VERTEX_COUNT:
 512       return "set_vertex_count";
 513    case GS_OPCODE_SET_DWORD_2:
 514       return "set_dword_2";
 515    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 516       return "prepare_channel_masks";
 517    case GS_OPCODE_SET_CHANNEL_MASKS:
 518       return "set_channel_masks";
 519    case GS_OPCODE_GET_INSTANCE_ID:
 520       return "get_instance_id";
 521    case GS_OPCODE_FF_SYNC:
 522       return "ff_sync";
 523    case GS_OPCODE_SET_PRIMITIVE_ID:
 524       return "set_primitive_id";
 525    case GS_OPCODE_SVB_WRITE:
 526       return "gs_svb_write";
 527    case GS_OPCODE_SVB_SET_DST_INDEX:
 528       return "gs_svb_set_dst_index";
 529    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 530       return "gs_ff_sync_set_primitives";
 531    case CS_OPCODE_CS_TERMINATE:
 532       return "cs_terminate";
 533    case SHADER_OPCODE_BARRIER:
 534       return "barrier";
 535    case SHADER_OPCODE_MULH:
 536       return "mulh";
 537    }
 538
 539    unreachable("not reached");
 540 }
 541
 542 bool
 543 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 544 {
 545    union {
 546       unsigned ud;
 547       int d;
 548       float f;
 549    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 550
 551    switch (type) {
 552    case BRW_REGISTER_TYPE_UD:
 553    case BRW_REGISTER_TYPE_D:
 554    case BRW_REGISTER_TYPE_UQ:
 555    case BRW_REGISTER_TYPE_Q:
 556       /* Nothing to do. */
 557       return false;
 558    case BRW_REGISTER_TYPE_UW:
 559       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 560       break;
 561    case BRW_REGISTER_TYPE_W:
 562       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 563       break;
 564    case BRW_REGISTER_TYPE_F:
 565       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 566       break;
 567    case BRW_REGISTER_TYPE_UB:
 568    case BRW_REGISTER_TYPE_B:
 569       unreachable("no UB/B immediates");
 570    case BRW_REGISTER_TYPE_V:
 571    case BRW_REGISTER_TYPE_UV:
 572    case BRW_REGISTER_TYPE_VF:
 573       unreachable("unimplemented: saturate vector immediate");
 574    case BRW_REGISTER_TYPE_DF:
 575    case BRW_REGISTER_TYPE_HF:
 576       unreachable("unimplemented: saturate DF/HF immediate");
 577    }
 578
 579    if (imm.ud != sat_imm.ud) {
 580       reg->dw1.ud = sat_imm.ud;
 581       return true;
 582    }
 583    return false;
 584 }
 585
 586 bool
 587 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 588 {
 589    switch (type) {
 590    case BRW_REGISTER_TYPE_D:
 591    case BRW_REGISTER_TYPE_UD:
 592       reg->dw1.d = -reg->dw1.d;
 593       return true;
 594    case BRW_REGISTER_TYPE_W:
 595    case BRW_REGISTER_TYPE_UW:
 596       reg->dw1.d = -(int16_t)reg->dw1.ud;
 597       return true;
 598    case BRW_REGISTER_TYPE_F:
 599       reg->dw1.f = -reg->dw1.f;
 600       return true;
 601    case BRW_REGISTER_TYPE_VF:
 602       reg->dw1.ud ^= 0x80808080;
 603       return true;
 604    case BRW_REGISTER_TYPE_UB:
 605    case BRW_REGISTER_TYPE_B:
 606       unreachable("no UB/B immediates");
 607    case BRW_REGISTER_TYPE_UV:
 608    case BRW_REGISTER_TYPE_V:
 609       assert(!"unimplemented: negate UV/V immediate");
 610    case BRW_REGISTER_TYPE_UQ:
 611    case BRW_REGISTER_TYPE_Q:
 612       assert(!"unimplemented: negate UQ/Q immediate");
 613    case BRW_REGISTER_TYPE_DF:
 614    case BRW_REGISTER_TYPE_HF:
 615       assert(!"unimplemented: negate DF/HF immediate");
 616    }
 617
 618    return false;
 619 }
 620
 621 bool
 622 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 623 {
 624    switch (type) {
 625    case BRW_REGISTER_TYPE_D:
 626       reg->dw1.d = abs(reg->dw1.d);
 627       return true;
 628    case BRW_REGISTER_TYPE_W:
 629       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 630       return true;
 631    case BRW_REGISTER_TYPE_F:
 632       reg->dw1.f = fabsf(reg->dw1.f);
 633       return true;
 634    case BRW_REGISTER_TYPE_VF:
 635       reg->dw1.ud &= ~0x80808080;
 636       return true;
 637    case BRW_REGISTER_TYPE_UB:
 638    case BRW_REGISTER_TYPE_B:
 639       unreachable("no UB/B immediates");
 640    case BRW_REGISTER_TYPE_UQ:
 641    case BRW_REGISTER_TYPE_UD:
 642    case BRW_REGISTER_TYPE_UW:
 643    case BRW_REGISTER_TYPE_UV:
 644       /* Presumably the absolute value modifier on an unsigned source is a
 645        * nop, but it would be nice to confirm.
 646        */
 647       assert(!"unimplemented: abs unsigned immediate");
 648    case BRW_REGISTER_TYPE_V:
 649       assert(!"unimplemented: abs V immediate");
 650    case BRW_REGISTER_TYPE_Q:
 651       assert(!"unimplemented: abs Q immediate");
 652    case BRW_REGISTER_TYPE_DF:
 653    case BRW_REGISTER_TYPE_HF:
 654       assert(!"unimplemented: abs DF/HF immediate");
 655    }
 656
 657    return false;
 658 }
 659
 660 backend_shader::backend_shader(const struct brw_compiler *compiler,
 661                                void *log_data,
 662                                void *mem_ctx,
 663                                const nir_shader *shader,
 664                                struct brw_stage_prog_data *stage_prog_data)
 665    : compiler(compiler),
 666      log_data(log_data),
 667      devinfo(compiler->devinfo),
 668      nir(shader),
 669      stage_prog_data(stage_prog_data),
 670      mem_ctx(mem_ctx),
 671      cfg(NULL),
 672      stage(shader->stage)
 673 {
 674    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 675    stage_name = _mesa_shader_stage_to_string(stage);
 676    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 677 }
 678
 679 bool
 680 backend_reg::is_zero() const
 681 {
 682    if (file != IMM)
 683       return false;
 684
 685    return fixed_hw_reg.dw1.d == 0;
 686 }
 687
 688 bool
 689 backend_reg::is_one() const
 690 {
 691    if (file != IMM)
 692       return false;
 693
 694    return type == BRW_REGISTER_TYPE_F
 695           ? fixed_hw_reg.dw1.f == 1.0
 696           : fixed_hw_reg.dw1.d == 1;
 697 }
 698
 699 bool
 700 backend_reg::is_negative_one() const
 701 {
 702    if (file != IMM)
 703       return false;
 704
 705    switch (type) {
 706    case BRW_REGISTER_TYPE_F:
 707       return fixed_hw_reg.dw1.f == -1.0;
 708    case BRW_REGISTER_TYPE_D:
 709       return fixed_hw_reg.dw1.d == -1;
 710    default:
 711       return false;
 712    }
 713 }
 714
 715 bool
 716 backend_reg::is_null() const
 717 {
 718    return file == HW_REG &&
 719           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 720           fixed_hw_reg.nr == BRW_ARF_NULL;
 721 }
 722
 723
 724 bool
 725 backend_reg::is_accumulator() const
 726 {
 727    return file == HW_REG &&
 728           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 729           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 730 }
 731
 732 bool
 733 backend_reg::in_range(const backend_reg &r, unsigned n) const
 734 {
 735    return (file == r.file &&
 736            reg == r.reg &&
 737            reg_offset >= r.reg_offset &&
 738            reg_offset < r.reg_offset + n);
 739 }
 740
 741 bool
 742 backend_instruction::is_commutative() const
 743 {
 744    switch (opcode) {
 745    case BRW_OPCODE_AND:
 746    case BRW_OPCODE_OR:
 747    case BRW_OPCODE_XOR:
 748    case BRW_OPCODE_ADD:
 749    case BRW_OPCODE_MUL:
 750    case SHADER_OPCODE_MULH:
 751       return true;
 752    case BRW_OPCODE_SEL:
 753       /* MIN and MAX are commutative. */
 754       if (conditional_mod == BRW_CONDITIONAL_GE ||
 755           conditional_mod == BRW_CONDITIONAL_L) {
 756          return true;
 757       }
 758       /* fallthrough */
 759    default:
 760       return false;
 761    }
 762 }
 763
 764 bool
 765 backend_instruction::is_3src() const
 766 {
 767    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 768 }
 769
 770 bool
 771 backend_instruction::is_tex() const
 772 {
 773    return (opcode == SHADER_OPCODE_TEX ||
 774            opcode == FS_OPCODE_TXB ||
 775            opcode == SHADER_OPCODE_TXD ||
 776            opcode == SHADER_OPCODE_TXF ||
 777            opcode == SHADER_OPCODE_TXF_CMS ||
 778            opcode == SHADER_OPCODE_TXF_UMS ||
 779            opcode == SHADER_OPCODE_TXF_MCS ||
 780            opcode == SHADER_OPCODE_TXL ||
 781            opcode == SHADER_OPCODE_TXS ||
 782            opcode == SHADER_OPCODE_LOD ||
 783            opcode == SHADER_OPCODE_TG4 ||
 784            opcode == SHADER_OPCODE_TG4_OFFSET);
 785 }
 786
 787 bool
 788 backend_instruction::is_math() const
 789 {
 790    return (opcode == SHADER_OPCODE_RCP ||
 791            opcode == SHADER_OPCODE_RSQ ||
 792            opcode == SHADER_OPCODE_SQRT ||
 793            opcode == SHADER_OPCODE_EXP2 ||
 794            opcode == SHADER_OPCODE_LOG2 ||
 795            opcode == SHADER_OPCODE_SIN ||
 796            opcode == SHADER_OPCODE_COS ||
 797            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 798            opcode == SHADER_OPCODE_INT_REMAINDER ||
 799            opcode == SHADER_OPCODE_POW);
 800 }
 801
 802 bool
 803 backend_instruction::is_control_flow() const
 804 {
 805    switch (opcode) {
 806    case BRW_OPCODE_DO:
 807    case BRW_OPCODE_WHILE:
 808    case BRW_OPCODE_IF:
 809    case BRW_OPCODE_ELSE:
 810    case BRW_OPCODE_ENDIF:
 811    case BRW_OPCODE_BREAK:
 812    case BRW_OPCODE_CONTINUE:
 813       return true;
 814    default:
 815       return false;
 816    }
 817 }
 818
 819 bool
 820 backend_instruction::can_do_source_mods() const
 821 {
 822    switch (opcode) {
 823    case BRW_OPCODE_ADDC:
 824    case BRW_OPCODE_BFE:
 825    case BRW_OPCODE_BFI1:
 826    case BRW_OPCODE_BFI2:
 827    case BRW_OPCODE_BFREV:
 828    case BRW_OPCODE_CBIT:
 829    case BRW_OPCODE_FBH:
 830    case BRW_OPCODE_FBL:
 831    case BRW_OPCODE_SUBB:
 832       return false;
 833    default:
 834       return true;
 835    }
 836 }
 837
 838 bool
 839 backend_instruction::can_do_saturate() const
 840 {
 841    switch (opcode) {
 842    case BRW_OPCODE_ADD:
 843    case BRW_OPCODE_ASR:
 844    case BRW_OPCODE_AVG:
 845    case BRW_OPCODE_DP2:
 846    case BRW_OPCODE_DP3:
 847    case BRW_OPCODE_DP4:
 848    case BRW_OPCODE_DPH:
 849    case BRW_OPCODE_F16TO32:
 850    case BRW_OPCODE_F32TO16:
 851    case BRW_OPCODE_LINE:
 852    case BRW_OPCODE_LRP:
 853    case BRW_OPCODE_MAC:
 854    case BRW_OPCODE_MAD:
 855    case BRW_OPCODE_MATH:
 856    case BRW_OPCODE_MOV:
 857    case BRW_OPCODE_MUL:
 858    case SHADER_OPCODE_MULH:
 859    case BRW_OPCODE_PLN:
 860    case BRW_OPCODE_RNDD:
 861    case BRW_OPCODE_RNDE:
 862    case BRW_OPCODE_RNDU:
 863    case BRW_OPCODE_RNDZ:
 864    case BRW_OPCODE_SEL:
 865    case BRW_OPCODE_SHL:
 866    case BRW_OPCODE_SHR:
 867    case FS_OPCODE_LINTERP:
 868    case SHADER_OPCODE_COS:
 869    case SHADER_OPCODE_EXP2:
 870    case SHADER_OPCODE_LOG2:
 871    case SHADER_OPCODE_POW:
 872    case SHADER_OPCODE_RCP:
 873    case SHADER_OPCODE_RSQ:
 874    case SHADER_OPCODE_SIN:
 875    case SHADER_OPCODE_SQRT:
 876       return true;
 877    default:
 878       return false;
 879    }
 880 }
 881
 882 bool
 883 backend_instruction::can_do_cmod() const
 884 {
 885    switch (opcode) {
 886    case BRW_OPCODE_ADD:
 887    case BRW_OPCODE_ADDC:
 888    case BRW_OPCODE_AND:
 889    case BRW_OPCODE_ASR:
 890    case BRW_OPCODE_AVG:
 891    case BRW_OPCODE_CMP:
 892    case BRW_OPCODE_CMPN:
 893    case BRW_OPCODE_DP2:
 894    case BRW_OPCODE_DP3:
 895    case BRW_OPCODE_DP4:
 896    case BRW_OPCODE_DPH:
 897    case BRW_OPCODE_F16TO32:
 898    case BRW_OPCODE_F32TO16:
 899    case BRW_OPCODE_FRC:
 900    case BRW_OPCODE_LINE:
 901    case BRW_OPCODE_LRP:
 902    case BRW_OPCODE_LZD:
 903    case BRW_OPCODE_MAC:
 904    case BRW_OPCODE_MACH:
 905    case BRW_OPCODE_MAD:
 906    case BRW_OPCODE_MOV:
 907    case BRW_OPCODE_MUL:
 908    case BRW_OPCODE_NOT:
 909    case BRW_OPCODE_OR:
 910    case BRW_OPCODE_PLN:
 911    case BRW_OPCODE_RNDD:
 912    case BRW_OPCODE_RNDE:
 913    case BRW_OPCODE_RNDU:
 914    case BRW_OPCODE_RNDZ:
 915    case BRW_OPCODE_SAD2:
 916    case BRW_OPCODE_SADA2:
 917    case BRW_OPCODE_SHL:
 918    case BRW_OPCODE_SHR:
 919    case BRW_OPCODE_SUBB:
 920    case BRW_OPCODE_XOR:
 921    case FS_OPCODE_CINTERP:
 922    case FS_OPCODE_LINTERP:
 923       return true;
 924    default:
 925       return false;
 926    }
 927 }
 928
 929 bool
 930 backend_instruction::reads_accumulator_implicitly() const
 931 {
 932    switch (opcode) {
 933    case BRW_OPCODE_MAC:
 934    case BRW_OPCODE_MACH:
 935    case BRW_OPCODE_SADA2:
 936       return true;
 937    default:
 938       return false;
 939    }
 940 }
 941
 942 bool
 943 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 944 {
 945    return writes_accumulator ||
 946           (devinfo->gen < 6 &&
 947            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 948             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 949              opcode != FS_OPCODE_CINTERP)));
 950 }
 951
 952 bool
 953 backend_instruction::has_side_effects() const
 954 {
 955    switch (opcode) {
 956    case SHADER_OPCODE_UNTYPED_ATOMIC:
 957    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 958    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 959    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 960    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 961    case SHADER_OPCODE_TYPED_ATOMIC:
 962    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 963    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 964    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 965    case SHADER_OPCODE_MEMORY_FENCE:
 966    case SHADER_OPCODE_URB_WRITE_SIMD8:
 967    case FS_OPCODE_FB_WRITE:
 968    case SHADER_OPCODE_BARRIER:
 969       return true;
 970    default:
 971       return false;
 972    }
 973 }
 974
 975 #ifndef NDEBUG
 976 static bool
 977 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 978 {
 979    bool found = false;
 980    foreach_inst_in_block (backend_instruction, i, block) {
 981       if (inst == i) {
 982          found = true;
 983       }
 984    }
 985    return found;
 986 }
 987 #endif
 988
 989 static void
 990 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
 991 {
 992    for (bblock_t *block_iter = start_block->next();
 993         !block_iter->link.is_tail_sentinel();
 994         block_iter = block_iter->next()) {
 995       block_iter->start_ip += ip_adjustment;
 996       block_iter->end_ip += ip_adjustment;
 997    }
 998 }
 999
1000 void
1001 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1002 {
1003    if (!this->is_head_sentinel())
1004       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1005
1006    block->end_ip++;
1007
1008    adjust_later_block_ips(block, 1);
1009
1010    exec_node::insert_after(inst);
1011 }
1012
1013 void
1014 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1015 {
1016    if (!this->is_tail_sentinel())
1017       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1018
1019    block->end_ip++;
1020
1021    adjust_later_block_ips(block, 1);
1022
1023    exec_node::insert_before(inst);
1024 }
1025
1026 void
1027 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1028 {
1029    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1030
1031    unsigned num_inst = list->length();
1032
1033    block->end_ip += num_inst;
1034
1035    adjust_later_block_ips(block, num_inst);
1036
1037    exec_node::insert_before(list);
1038 }
1039
1040 void
1041 backend_instruction::remove(bblock_t *block)
1042 {
1043    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1044
1045    adjust_later_block_ips(block, -1);
1046
1047    if (block->start_ip == block->end_ip) {
1048       block->cfg->remove_block(block);
1049    } else {
1050       block->end_ip--;
1051    }
1052
1053    exec_node::remove();
1054 }
1055
1056 void
1057 backend_shader::dump_instructions()
1058 {
1059    dump_instructions(NULL);
1060 }
1061
1062 void
1063 backend_shader::dump_instructions(const char *name)
1064 {
1065    FILE *file = stderr;
1066    if (name && geteuid() != 0) {
1067       file = fopen(name, "w");
1068       if (!file)
1069          file = stderr;
1070    }
1071
1072    if (cfg) {
1073       int ip = 0;
1074       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1075          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1076             fprintf(file, "%4d: ", ip++);
1077          dump_instruction(inst, file);
1078       }
1079    } else {
1080       int ip = 0;
1081       foreach_in_list(backend_instruction, inst, &instructions) {
1082          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1083             fprintf(file, "%4d: ", ip++);
1084          dump_instruction(inst, file);
1085       }
1086    }
1087
1088    if (file != stderr) {
1089       fclose(file);
1090    }
1091 }
1092
1093 void
1094 backend_shader::calculate_cfg()
1095 {
1096    if (this->cfg)
1097       return;
1098    cfg = new(mem_ctx) cfg_t(&this->instructions);
1099 }
1100
1101 void
1102 backend_shader::invalidate_cfg()
1103 {
1104    ralloc_free(this->cfg);
1105    this->cfg = NULL;
1106 }
1107
1108 /**
1109  * Sets up the starting offsets for the groups of binding table entries
1110  * commong to all pipeline stages.
1111  *
1112  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1113  * unused but also make sure that addition of small offsets to them will
1114  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1115  */
1116 void
1117 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1118                                         const struct brw_device_info *devinfo,
1119                                         const struct gl_shader_program *shader_prog,
1120                                         const struct gl_program *prog,
1121                                         struct brw_stage_prog_data *stage_prog_data,
1122                                         uint32_t next_binding_table_offset)
1123 {
1124    const struct gl_shader *shader = NULL;
1125    int num_textures = _mesa_fls(prog->SamplersUsed);
1126
1127    if (shader_prog)
1128       shader = shader_prog->_LinkedShaders[stage];
1129
1130    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1131    next_binding_table_offset += num_textures;
1132
1133    if (shader) {
1134       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1135       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1136       next_binding_table_offset += shader->NumUniformBlocks;
1137
1138       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1139       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1140       next_binding_table_offset += shader->NumShaderStorageBlocks;
1141    } else {
1142       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1143       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1144    }
1145
1146    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1147       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1148       next_binding_table_offset++;
1149    } else {
1150       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1151    }
1152
1153    if (prog->UsesGather) {
1154       if (devinfo->gen >= 8) {
1155          stage_prog_data->binding_table.gather_texture_start =
1156             stage_prog_data->binding_table.texture_start;
1157       } else {
1158          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1159          next_binding_table_offset += num_textures;
1160       }
1161    } else {
1162       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1163    }
1164
1165    if (shader_prog && shader_prog->NumAtomicBuffers) {
1166       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1167       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1168    } else {
1169       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1170    }
1171
1172    if (shader && shader->NumImages) {
1173       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1174       next_binding_table_offset += shader->NumImages;
1175    } else {
1176       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1177    }
1178
1179    /* This may or may not be used depending on how the compile goes. */
1180    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1181    next_binding_table_offset++;
1182
1183    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1184
1185    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1186 }
1187
1188 static void
1189 setup_vec4_uniform_value(const gl_constant_value **params,
1190                          const gl_constant_value *values,
1191                          unsigned n)
1192 {
1193    static const gl_constant_value zero = { 0 };
1194
1195    for (unsigned i = 0; i < n; ++i)
1196       params[i] = &values[i];
1197
1198    for (unsigned i = n; i < 4; ++i)
1199       params[i] = &zero;
1200 }
1201
1202 void
1203 brw_setup_image_uniform_values(gl_shader_stage stage,
1204                                struct brw_stage_prog_data *stage_prog_data,
1205                                unsigned param_start_index,
1206                                const gl_uniform_storage *storage)
1207 {
1208    const gl_constant_value **param =
1209       &stage_prog_data->param[param_start_index];
1210
1211    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1212       const unsigned image_idx = storage->opaque[stage].index + i;
1213       const brw_image_param *image_param =
1214          &stage_prog_data->image_param[image_idx];
1215
1216       /* Upload the brw_image_param structure.  The order is expected to match
1217        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1218        */
1219       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1220          (const gl_constant_value *)&image_param->surface_idx, 1);
1221       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1222          (const gl_constant_value *)image_param->offset, 2);
1223       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1224          (const gl_constant_value *)image_param->size, 3);
1225       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1226          (const gl_constant_value *)image_param->stride, 4);
1227       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1228          (const gl_constant_value *)image_param->tiling, 3);
1229       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1230          (const gl_constant_value *)image_param->swizzling, 2);
1231       param += BRW_IMAGE_PARAM_SIZE;
1232
1233       brw_mark_surface_used(
1234          stage_prog_data,
1235          stage_prog_data->binding_table.image_start + image_idx);
1236    }
1237 }
1238
1239 /**
1240  * Decide which set of clip planes should be used when clipping via
1241  * gl_Position or gl_ClipVertex.
1242  */
1243 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1244 {
1245    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1246       /* There is currently a GLSL vertex shader, so clip according to GLSL
1247        * rules, which means compare gl_ClipVertex (or gl_Position, if
1248        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1249        * that were stored in EyeUserPlane at the time the clip planes were
1250        * specified.
1251        */
1252       return ctx->Transform.EyeUserPlane;
1253    } else {
1254       /* Either we are using fixed function or an ARB vertex program.  In
1255        * either case the clip planes are going to be compared against
1256        * gl_Position (which is in clip coordinates) so we have to clip using
1257        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1258        * core.
1259        */
1260       return ctx->Transform._ClipUserPlane;
1261    }
1262 }
1263