src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
  88       compiler->scalar_vs = true;
  89
  90    nir_shader_compiler_options *nir_options =
  91       rzalloc(compiler, nir_shader_compiler_options);
  92    nir_options->native_integers = true;
  93    /* In order to help allow for better CSE at the NIR level we tell NIR
  94     * to split all ffma instructions during opt_algebraic and we then
  95     * re-combine them as a later step.
  96     */
  97    nir_options->lower_ffma = true;
  98    nir_options->lower_sub = true;
  99    /* In the vec4 backend, our dpN instruction replicates its result to all
 100     * the components of a vec4.  We would like NIR to give us replicated fdot
 101     * instructions because it can optimize better for us.
 102     *
 103     * For the FS backend, it should be lowered away by the scalarizing pass so
 104     * we should never see fdot anyway.
 105     */
 106    nir_options->fdot_replicates = true;
 107
 108    /* We want the GLSL compiler to emit code that uses condition codes */
 109    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 110       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 111       compiler->glsl_compiler_options[i].MaxIfDepth =
 112          devinfo->gen < 6 ? 16 : UINT_MAX;
 113
 114       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 115       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 116       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 117       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 118       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 119       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 120
 121       bool is_scalar;
 122       switch (i) {
 123       case MESA_SHADER_FRAGMENT:
 124       case MESA_SHADER_COMPUTE:
 125          is_scalar = true;
 126          break;
 127       case MESA_SHADER_VERTEX:
 128          is_scalar = compiler->scalar_vs;
 129          break;
 130       default:
 131          is_scalar = false;
 132          break;
 133       }
 134
 135       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 136       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 137       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 138
 139       /* !ARB_gpu_shader5 */
 140       if (devinfo->gen < 7)
 141          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 142
 143       if (is_scalar || brw_env_var_as_boolean("INTEL_USE_NIR", true))
 144          compiler->glsl_compiler_options[i].NirOptions = nir_options;
 145    }
 146
 147    return compiler;
 148 }
 149
 150 struct gl_shader *
 151 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 152 {
 153    struct brw_shader *shader;
 154
 155    shader = rzalloc(NULL, struct brw_shader);
 156    if (shader) {
 157       shader->base.Type = type;
 158       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 159       shader->base.Name = name;
 160       _mesa_init_shader(ctx, &shader->base);
 161    }
 162
 163    return &shader->base;
 164 }
 165
 166 /**
 167  * Performs a compile of the shader stages even when we don't know
 168  * what non-orthogonal state will be set, in the hope that it reflects
 169  * the eventual NOS used, and thus allows us to produce link failures.
 170  */
 171 static bool
 172 brw_shader_precompile(struct gl_context *ctx,
 173                       struct gl_shader_program *sh_prog)
 174 {
 175    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 176    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 177    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 178    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 179
 180    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 181       return false;
 182
 183    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 184       return false;
 185
 186    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 187       return false;
 188
 189    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 190       return false;
 191
 192    return true;
 193 }
 194
 195 static inline bool
 196 is_scalar_shader_stage(struct brw_context *brw, int stage)
 197 {
 198    switch (stage) {
 199    case MESA_SHADER_FRAGMENT:
 200    case MESA_SHADER_COMPUTE:
 201       return true;
 202    case MESA_SHADER_VERTEX:
 203       return brw->intelScreen->compiler->scalar_vs;
 204    default:
 205       return false;
 206    }
 207 }
 208
 209 static void
 210 brw_lower_packing_builtins(struct brw_context *brw,
 211                            gl_shader_stage shader_type,
 212                            exec_list *ir)
 213 {
 214    int ops = LOWER_PACK_SNORM_2x16
 215            | LOWER_UNPACK_SNORM_2x16
 216            | LOWER_PACK_UNORM_2x16
 217            | LOWER_UNPACK_UNORM_2x16;
 218
 219    if (is_scalar_shader_stage(brw, shader_type)) {
 220       ops |= LOWER_UNPACK_UNORM_4x8
 221            | LOWER_UNPACK_SNORM_4x8
 222            | LOWER_PACK_UNORM_4x8
 223            | LOWER_PACK_SNORM_4x8;
 224    }
 225
 226    if (brw->gen >= 7) {
 227       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 228        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 229        * lowering is needed. For SOA code, the Half2x16 ops must be
 230        * scalarized.
 231        */
 232       if (is_scalar_shader_stage(brw, shader_type)) {
 233          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 234              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 235       }
 236    } else {
 237       ops |= LOWER_PACK_HALF_2x16
 238           |  LOWER_UNPACK_HALF_2x16;
 239    }
 240
 241    lower_packing_builtins(ir, ops);
 242 }
 243
 244 static void
 245 process_glsl_ir(gl_shader_stage stage,
 246                 struct brw_context *brw,
 247                 struct gl_shader_program *shader_prog,
 248                 struct gl_shader *shader)
 249 {
 250    struct gl_context *ctx = &brw->ctx;
 251    const struct gl_shader_compiler_options *options =
 252       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 253
 254    /* Temporary memory context for any new IR. */
 255    void *mem_ctx = ralloc_context(NULL);
 256
 257    ralloc_adopt(mem_ctx, shader->ir);
 258
 259    /* lower_packing_builtins() inserts arithmetic instructions, so it
 260     * must precede lower_instructions().
 261     */
 262    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 263    do_mat_op_to_vec(shader->ir);
 264    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 265    lower_instructions(shader->ir,
 266                       MOD_TO_FLOOR |
 267                       DIV_TO_MUL_RCP |
 268                       SUB_TO_ADD_NEG |
 269                       EXP_TO_EXP2 |
 270                       LOG_TO_LOG2 |
 271                       bitfield_insert |
 272                       LDEXP_TO_ARITH |
 273                       CARRY_TO_ARITH |
 274                       BORROW_TO_ARITH);
 275
 276    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 277     * if-statements need to be flattened.
 278     */
 279    if (brw->gen < 6)
 280       lower_if_to_cond_assign(shader->ir, 16);
 281
 282    do_lower_texture_projection(shader->ir);
 283    brw_lower_texture_gradients(brw, shader->ir);
 284    do_vec_index_to_cond_assign(shader->ir);
 285    lower_vector_insert(shader->ir, true);
 286    if (options->NirOptions == NULL)
 287       brw_do_cubemap_normalize(shader->ir);
 288    lower_offset_arrays(shader->ir);
 289    brw_do_lower_unnormalized_offset(shader->ir);
 290    lower_noise(shader->ir);
 291    lower_quadop_vector(shader->ir, false);
 292
 293    bool lowered_variable_indexing =
 294       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 295                                           shader->ir,
 296                                           options->EmitNoIndirectInput,
 297                                           options->EmitNoIndirectOutput,
 298                                           options->EmitNoIndirectTemp,
 299                                           options->EmitNoIndirectUniform);
 300
 301    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 302       perf_debug("Unsupported form of variable indexing in %s; falling "
 303                  "back to very inefficient code generation\n",
 304                  _mesa_shader_stage_to_abbrev(shader->Stage));
 305    }
 306
 307    lower_ubo_reference(shader, shader->ir);
 308
 309    bool progress;
 310    do {
 311       progress = false;
 312
 313       if (is_scalar_shader_stage(brw, shader->Stage)) {
 314          brw_do_channel_expressions(shader->ir);
 315          brw_do_vector_splitting(shader->ir);
 316       }
 317
 318       progress = do_lower_jumps(shader->ir, true, true,
 319                                 true, /* main return */
 320                                 false, /* continue */
 321                                 false /* loops */
 322                                 ) || progress;
 323
 324       progress = do_common_optimization(shader->ir, true, true,
 325                                         options, ctx->Const.NativeIntegers) || progress;
 326    } while (progress);
 327
 328    validate_ir_tree(shader->ir);
 329
 330    /* Now that we've finished altering the linked IR, reparent any live IR back
 331     * to the permanent memory context, and free the temporary one (discarding any
 332     * junk we optimized away).
 333     */
 334    reparent_ir(shader->ir, shader->ir);
 335    ralloc_free(mem_ctx);
 336
 337    if (ctx->_Shader->Flags & GLSL_DUMP) {
 338       fprintf(stderr, "\n");
 339       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 340               _mesa_shader_stage_to_string(shader->Stage),
 341               shader_prog->Name);
 342       _mesa_print_ir(stderr, shader->ir, NULL);
 343       fprintf(stderr, "\n");
 344    }
 345 }
 346
 347 GLboolean
 348 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 349 {
 350    struct brw_context *brw = brw_context(ctx);
 351    unsigned int stage;
 352
 353    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 354       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 355       const struct gl_shader_compiler_options *options =
 356          &ctx->Const.ShaderCompilerOptions[stage];
 357
 358       if (!shader)
 359          continue;
 360
 361       struct gl_program *prog =
 362          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 363                                 shader->Name);
 364       if (!prog)
 365         return false;
 366       prog->Parameters = _mesa_new_parameter_list();
 367
 368       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 369
 370       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 371
 372       /* Make a pass over the IR to add state references for any built-in
 373        * uniforms that are used.  This has to be done now (during linking).
 374        * Code generation doesn't happen until the first time this shader is
 375        * used for rendering.  Waiting until then to generate the parameters is
 376        * too late.  At that point, the values for the built-in uniforms won't
 377        * get sent to the shader.
 378        */
 379       foreach_in_list(ir_instruction, node, shader->ir) {
 380          ir_variable *var = node->as_variable();
 381
 382          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 383              || (strncmp(var->name, "gl_", 3) != 0))
 384             continue;
 385
 386          const ir_state_slot *const slots = var->get_state_slots();
 387          assert(slots != NULL);
 388
 389          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 390             _mesa_add_state_reference(prog->Parameters,
 391                                       (gl_state_index *) slots[i].tokens);
 392          }
 393       }
 394
 395       do_set_program_inouts(shader->ir, prog, shader->Stage);
 396
 397       prog->SamplersUsed = shader->active_samplers;
 398       prog->ShadowSamplers = shader->shadow_samplers;
 399       _mesa_update_shader_textures_used(shProg, prog);
 400
 401       _mesa_reference_program(ctx, &shader->Program, prog);
 402
 403       brw_add_texrect_params(prog);
 404
 405       if (options->NirOptions) {
 406          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 407                                     is_scalar_shader_stage(brw, stage));
 408       }
 409
 410       _mesa_reference_program(ctx, &prog, NULL);
 411    }
 412
 413    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 414       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 415          const struct gl_shader *sh = shProg->Shaders[i];
 416          if (!sh)
 417             continue;
 418
 419          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 420                  _mesa_shader_stage_to_string(sh->Stage),
 421                  i, shProg->Name);
 422          fprintf(stderr, "%s", sh->Source);
 423          fprintf(stderr, "\n");
 424       }
 425    }
 426
 427    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 428       return false;
 429
 430    return true;
 431 }
 432
 433
 434 enum brw_reg_type
 435 brw_type_for_base_type(const struct glsl_type *type)
 436 {
 437    switch (type->base_type) {
 438    case GLSL_TYPE_FLOAT:
 439       return BRW_REGISTER_TYPE_F;
 440    case GLSL_TYPE_INT:
 441    case GLSL_TYPE_BOOL:
 442    case GLSL_TYPE_SUBROUTINE:
 443       return BRW_REGISTER_TYPE_D;
 444    case GLSL_TYPE_UINT:
 445       return BRW_REGISTER_TYPE_UD;
 446    case GLSL_TYPE_ARRAY:
 447       return brw_type_for_base_type(type->fields.array);
 448    case GLSL_TYPE_STRUCT:
 449    case GLSL_TYPE_SAMPLER:
 450    case GLSL_TYPE_ATOMIC_UINT:
 451       /* These should be overridden with the type of the member when
 452        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 453        * way to trip up if we don't.
 454        */
 455       return BRW_REGISTER_TYPE_UD;
 456    case GLSL_TYPE_IMAGE:
 457       return BRW_REGISTER_TYPE_UD;
 458    case GLSL_TYPE_VOID:
 459    case GLSL_TYPE_ERROR:
 460    case GLSL_TYPE_INTERFACE:
 461    case GLSL_TYPE_DOUBLE:
 462       unreachable("not reached");
 463    }
 464
 465    return BRW_REGISTER_TYPE_F;
 466 }
 467
 468 enum brw_conditional_mod
 469 brw_conditional_for_comparison(unsigned int op)
 470 {
 471    switch (op) {
 472    case ir_binop_less:
 473       return BRW_CONDITIONAL_L;
 474    case ir_binop_greater:
 475       return BRW_CONDITIONAL_G;
 476    case ir_binop_lequal:
 477       return BRW_CONDITIONAL_LE;
 478    case ir_binop_gequal:
 479       return BRW_CONDITIONAL_GE;
 480    case ir_binop_equal:
 481    case ir_binop_all_equal: /* same as equal for scalars */
 482       return BRW_CONDITIONAL_Z;
 483    case ir_binop_nequal:
 484    case ir_binop_any_nequal: /* same as nequal for scalars */
 485       return BRW_CONDITIONAL_NZ;
 486    default:
 487       unreachable("not reached: bad operation for comparison");
 488    }
 489 }
 490
 491 uint32_t
 492 brw_math_function(enum opcode op)
 493 {
 494    switch (op) {
 495    case SHADER_OPCODE_RCP:
 496       return BRW_MATH_FUNCTION_INV;
 497    case SHADER_OPCODE_RSQ:
 498       return BRW_MATH_FUNCTION_RSQ;
 499    case SHADER_OPCODE_SQRT:
 500       return BRW_MATH_FUNCTION_SQRT;
 501    case SHADER_OPCODE_EXP2:
 502       return BRW_MATH_FUNCTION_EXP;
 503    case SHADER_OPCODE_LOG2:
 504       return BRW_MATH_FUNCTION_LOG;
 505    case SHADER_OPCODE_POW:
 506       return BRW_MATH_FUNCTION_POW;
 507    case SHADER_OPCODE_SIN:
 508       return BRW_MATH_FUNCTION_SIN;
 509    case SHADER_OPCODE_COS:
 510       return BRW_MATH_FUNCTION_COS;
 511    case SHADER_OPCODE_INT_QUOTIENT:
 512       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 513    case SHADER_OPCODE_INT_REMAINDER:
 514       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 515    default:
 516       unreachable("not reached: unknown math function");
 517    }
 518 }
 519
 520 uint32_t
 521 brw_texture_offset(int *offsets, unsigned num_components)
 522 {
 523    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 524
 525    /* Combine all three offsets into a single unsigned dword:
 526     *
 527     *    bits 11:8 - U Offset (X component)
 528     *    bits  7:4 - V Offset (Y component)
 529     *    bits  3:0 - R Offset (Z component)
 530     */
 531    unsigned offset_bits = 0;
 532    for (unsigned i = 0; i < num_components; i++) {
 533       const unsigned shift = 4 * (2 - i);
 534       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 535    }
 536    return offset_bits;
 537 }
 538
 539 const char *
 540 brw_instruction_name(enum opcode op)
 541 {
 542    switch (op) {
 543    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 544       assert(opcode_descs[op].name);
 545       return opcode_descs[op].name;
 546    case FS_OPCODE_FB_WRITE:
 547       return "fb_write";
 548    case FS_OPCODE_FB_WRITE_LOGICAL:
 549       return "fb_write_logical";
 550    case FS_OPCODE_BLORP_FB_WRITE:
 551       return "blorp_fb_write";
 552    case FS_OPCODE_REP_FB_WRITE:
 553       return "rep_fb_write";
 554
 555    case SHADER_OPCODE_RCP:
 556       return "rcp";
 557    case SHADER_OPCODE_RSQ:
 558       return "rsq";
 559    case SHADER_OPCODE_SQRT:
 560       return "sqrt";
 561    case SHADER_OPCODE_EXP2:
 562       return "exp2";
 563    case SHADER_OPCODE_LOG2:
 564       return "log2";
 565    case SHADER_OPCODE_POW:
 566       return "pow";
 567    case SHADER_OPCODE_INT_QUOTIENT:
 568       return "int_quot";
 569    case SHADER_OPCODE_INT_REMAINDER:
 570       return "int_rem";
 571    case SHADER_OPCODE_SIN:
 572       return "sin";
 573    case SHADER_OPCODE_COS:
 574       return "cos";
 575
 576    case SHADER_OPCODE_TEX:
 577       return "tex";
 578    case SHADER_OPCODE_TEX_LOGICAL:
 579       return "tex_logical";
 580    case SHADER_OPCODE_TXD:
 581       return "txd";
 582    case SHADER_OPCODE_TXD_LOGICAL:
 583       return "txd_logical";
 584    case SHADER_OPCODE_TXF:
 585       return "txf";
 586    case SHADER_OPCODE_TXF_LOGICAL:
 587       return "txf_logical";
 588    case SHADER_OPCODE_TXL:
 589       return "txl";
 590    case SHADER_OPCODE_TXL_LOGICAL:
 591       return "txl_logical";
 592    case SHADER_OPCODE_TXS:
 593       return "txs";
 594    case SHADER_OPCODE_TXS_LOGICAL:
 595       return "txs_logical";
 596    case FS_OPCODE_TXB:
 597       return "txb";
 598    case FS_OPCODE_TXB_LOGICAL:
 599       return "txb_logical";
 600    case SHADER_OPCODE_TXF_CMS:
 601       return "txf_cms";
 602    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 603       return "txf_cms_logical";
 604    case SHADER_OPCODE_TXF_UMS:
 605       return "txf_ums";
 606    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 607       return "txf_ums_logical";
 608    case SHADER_OPCODE_TXF_MCS:
 609       return "txf_mcs";
 610    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 611       return "txf_mcs_logical";
 612    case SHADER_OPCODE_LOD:
 613       return "lod";
 614    case SHADER_OPCODE_LOD_LOGICAL:
 615       return "lod_logical";
 616    case SHADER_OPCODE_TG4:
 617       return "tg4";
 618    case SHADER_OPCODE_TG4_LOGICAL:
 619       return "tg4_logical";
 620    case SHADER_OPCODE_TG4_OFFSET:
 621       return "tg4_offset";
 622    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 623       return "tg4_offset_logical";
 624    case SHADER_OPCODE_SAMPLEINFO:
 625       return "sampleinfo";
 626
 627    case SHADER_OPCODE_SHADER_TIME_ADD:
 628       return "shader_time_add";
 629
 630    case SHADER_OPCODE_UNTYPED_ATOMIC:
 631       return "untyped_atomic";
 632    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 633       return "untyped_atomic_logical";
 634    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 635       return "untyped_surface_read";
 636    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 637       return "untyped_surface_read_logical";
 638    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 639       return "untyped_surface_write";
 640    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 641       return "untyped_surface_write_logical";
 642    case SHADER_OPCODE_TYPED_ATOMIC:
 643       return "typed_atomic";
 644    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 645       return "typed_atomic_logical";
 646    case SHADER_OPCODE_TYPED_SURFACE_READ:
 647       return "typed_surface_read";
 648    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 649       return "typed_surface_read_logical";
 650    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 651       return "typed_surface_write";
 652    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 653       return "typed_surface_write_logical";
 654    case SHADER_OPCODE_MEMORY_FENCE:
 655       return "memory_fence";
 656
 657    case SHADER_OPCODE_LOAD_PAYLOAD:
 658       return "load_payload";
 659
 660    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 661       return "gen4_scratch_read";
 662    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 663       return "gen4_scratch_write";
 664    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 665       return "gen7_scratch_read";
 666    case SHADER_OPCODE_URB_WRITE_SIMD8:
 667       return "gen8_urb_write_simd8";
 668
 669    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 670       return "find_live_channel";
 671    case SHADER_OPCODE_BROADCAST:
 672       return "broadcast";
 673
 674    case VEC4_OPCODE_MOV_BYTES:
 675       return "mov_bytes";
 676    case VEC4_OPCODE_PACK_BYTES:
 677       return "pack_bytes";
 678    case VEC4_OPCODE_UNPACK_UNIFORM:
 679       return "unpack_uniform";
 680
 681    case FS_OPCODE_DDX_COARSE:
 682       return "ddx_coarse";
 683    case FS_OPCODE_DDX_FINE:
 684       return "ddx_fine";
 685    case FS_OPCODE_DDY_COARSE:
 686       return "ddy_coarse";
 687    case FS_OPCODE_DDY_FINE:
 688       return "ddy_fine";
 689
 690    case FS_OPCODE_CINTERP:
 691       return "cinterp";
 692    case FS_OPCODE_LINTERP:
 693       return "linterp";
 694
 695    case FS_OPCODE_PIXEL_X:
 696       return "pixel_x";
 697    case FS_OPCODE_PIXEL_Y:
 698       return "pixel_y";
 699
 700    case FS_OPCODE_GET_BUFFER_SIZE:
 701       return "fs_get_buffer_size";
 702
 703    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 704       return "uniform_pull_const";
 705    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 706       return "uniform_pull_const_gen7";
 707    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 708       return "varying_pull_const";
 709    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 710       return "varying_pull_const_gen7";
 711
 712    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 713       return "mov_dispatch_to_flags";
 714    case FS_OPCODE_DISCARD_JUMP:
 715       return "discard_jump";
 716
 717    case FS_OPCODE_SET_SAMPLE_ID:
 718       return "set_sample_id";
 719    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 720       return "set_simd4x2_offset";
 721
 722    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 723       return "pack_half_2x16_split";
 724    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 725       return "unpack_half_2x16_split_x";
 726    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 727       return "unpack_half_2x16_split_y";
 728
 729    case FS_OPCODE_PLACEHOLDER_HALT:
 730       return "placeholder_halt";
 731
 732    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 733       return "interp_centroid";
 734    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 735       return "interp_sample";
 736    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 737       return "interp_shared_offset";
 738    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 739       return "interp_per_slot_offset";
 740
 741    case VS_OPCODE_URB_WRITE:
 742       return "vs_urb_write";
 743    case VS_OPCODE_PULL_CONSTANT_LOAD:
 744       return "pull_constant_load";
 745    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 746       return "pull_constant_load_gen7";
 747
 748    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 749       return "set_simd4x2_header_gen9";
 750
 751    case VS_OPCODE_GET_BUFFER_SIZE:
 752       return "vs_get_buffer_size";
 753
 754    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 755       return "unpack_flags_simd4x2";
 756
 757    case GS_OPCODE_URB_WRITE:
 758       return "gs_urb_write";
 759    case GS_OPCODE_URB_WRITE_ALLOCATE:
 760       return "gs_urb_write_allocate";
 761    case GS_OPCODE_THREAD_END:
 762       return "gs_thread_end";
 763    case GS_OPCODE_SET_WRITE_OFFSET:
 764       return "set_write_offset";
 765    case GS_OPCODE_SET_VERTEX_COUNT:
 766       return "set_vertex_count";
 767    case GS_OPCODE_SET_DWORD_2:
 768       return "set_dword_2";
 769    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 770       return "prepare_channel_masks";
 771    case GS_OPCODE_SET_CHANNEL_MASKS:
 772       return "set_channel_masks";
 773    case GS_OPCODE_GET_INSTANCE_ID:
 774       return "get_instance_id";
 775    case GS_OPCODE_FF_SYNC:
 776       return "ff_sync";
 777    case GS_OPCODE_SET_PRIMITIVE_ID:
 778       return "set_primitive_id";
 779    case GS_OPCODE_SVB_WRITE:
 780       return "gs_svb_write";
 781    case GS_OPCODE_SVB_SET_DST_INDEX:
 782       return "gs_svb_set_dst_index";
 783    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 784       return "gs_ff_sync_set_primitives";
 785    case CS_OPCODE_CS_TERMINATE:
 786       return "cs_terminate";
 787    case SHADER_OPCODE_BARRIER:
 788       return "barrier";
 789    case SHADER_OPCODE_MULH:
 790       return "mulh";
 791    }
 792
 793    unreachable("not reached");
 794 }
 795
 796 bool
 797 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 798 {
 799    union {
 800       unsigned ud;
 801       int d;
 802       float f;
 803    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 804
 805    switch (type) {
 806    case BRW_REGISTER_TYPE_UD:
 807    case BRW_REGISTER_TYPE_D:
 808    case BRW_REGISTER_TYPE_UQ:
 809    case BRW_REGISTER_TYPE_Q:
 810       /* Nothing to do. */
 811       return false;
 812    case BRW_REGISTER_TYPE_UW:
 813       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 814       break;
 815    case BRW_REGISTER_TYPE_W:
 816       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 817       break;
 818    case BRW_REGISTER_TYPE_F:
 819       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 820       break;
 821    case BRW_REGISTER_TYPE_UB:
 822    case BRW_REGISTER_TYPE_B:
 823       unreachable("no UB/B immediates");
 824    case BRW_REGISTER_TYPE_V:
 825    case BRW_REGISTER_TYPE_UV:
 826    case BRW_REGISTER_TYPE_VF:
 827       unreachable("unimplemented: saturate vector immediate");
 828    case BRW_REGISTER_TYPE_DF:
 829    case BRW_REGISTER_TYPE_HF:
 830       unreachable("unimplemented: saturate DF/HF immediate");
 831    }
 832
 833    if (imm.ud != sat_imm.ud) {
 834       reg->dw1.ud = sat_imm.ud;
 835       return true;
 836    }
 837    return false;
 838 }
 839
 840 bool
 841 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 842 {
 843    switch (type) {
 844    case BRW_REGISTER_TYPE_D:
 845    case BRW_REGISTER_TYPE_UD:
 846       reg->dw1.d = -reg->dw1.d;
 847       return true;
 848    case BRW_REGISTER_TYPE_W:
 849    case BRW_REGISTER_TYPE_UW:
 850       reg->dw1.d = -(int16_t)reg->dw1.ud;
 851       return true;
 852    case BRW_REGISTER_TYPE_F:
 853       reg->dw1.f = -reg->dw1.f;
 854       return true;
 855    case BRW_REGISTER_TYPE_VF:
 856       reg->dw1.ud ^= 0x80808080;
 857       return true;
 858    case BRW_REGISTER_TYPE_UB:
 859    case BRW_REGISTER_TYPE_B:
 860       unreachable("no UB/B immediates");
 861    case BRW_REGISTER_TYPE_UV:
 862    case BRW_REGISTER_TYPE_V:
 863       assert(!"unimplemented: negate UV/V immediate");
 864    case BRW_REGISTER_TYPE_UQ:
 865    case BRW_REGISTER_TYPE_Q:
 866       assert(!"unimplemented: negate UQ/Q immediate");
 867    case BRW_REGISTER_TYPE_DF:
 868    case BRW_REGISTER_TYPE_HF:
 869       assert(!"unimplemented: negate DF/HF immediate");
 870    }
 871
 872    return false;
 873 }
 874
 875 bool
 876 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 877 {
 878    switch (type) {
 879    case BRW_REGISTER_TYPE_D:
 880       reg->dw1.d = abs(reg->dw1.d);
 881       return true;
 882    case BRW_REGISTER_TYPE_W:
 883       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 884       return true;
 885    case BRW_REGISTER_TYPE_F:
 886       reg->dw1.f = fabsf(reg->dw1.f);
 887       return true;
 888    case BRW_REGISTER_TYPE_VF:
 889       reg->dw1.ud &= ~0x80808080;
 890       return true;
 891    case BRW_REGISTER_TYPE_UB:
 892    case BRW_REGISTER_TYPE_B:
 893       unreachable("no UB/B immediates");
 894    case BRW_REGISTER_TYPE_UQ:
 895    case BRW_REGISTER_TYPE_UD:
 896    case BRW_REGISTER_TYPE_UW:
 897    case BRW_REGISTER_TYPE_UV:
 898       /* Presumably the absolute value modifier on an unsigned source is a
 899        * nop, but it would be nice to confirm.
 900        */
 901       assert(!"unimplemented: abs unsigned immediate");
 902    case BRW_REGISTER_TYPE_V:
 903       assert(!"unimplemented: abs V immediate");
 904    case BRW_REGISTER_TYPE_Q:
 905       assert(!"unimplemented: abs Q immediate");
 906    case BRW_REGISTER_TYPE_DF:
 907    case BRW_REGISTER_TYPE_HF:
 908       assert(!"unimplemented: abs DF/HF immediate");
 909    }
 910
 911    return false;
 912 }
 913
 914 backend_shader::backend_shader(const struct brw_compiler *compiler,
 915                                void *log_data,
 916                                void *mem_ctx,
 917                                struct gl_shader_program *shader_prog,
 918                                struct gl_program *prog,
 919                                struct brw_stage_prog_data *stage_prog_data,
 920                                gl_shader_stage stage)
 921    : compiler(compiler),
 922      log_data(log_data),
 923      devinfo(compiler->devinfo),
 924      shader(shader_prog ?
 925         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 926      shader_prog(shader_prog),
 927      prog(prog),
 928      stage_prog_data(stage_prog_data),
 929      mem_ctx(mem_ctx),
 930      cfg(NULL),
 931      stage(stage)
 932 {
 933    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 934    stage_name = _mesa_shader_stage_to_string(stage);
 935    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 936 }
 937
 938 bool
 939 backend_reg::is_zero() const
 940 {
 941    if (file != IMM)
 942       return false;
 943
 944    return fixed_hw_reg.dw1.d == 0;
 945 }
 946
 947 bool
 948 backend_reg::is_one() const
 949 {
 950    if (file != IMM)
 951       return false;
 952
 953    return type == BRW_REGISTER_TYPE_F
 954           ? fixed_hw_reg.dw1.f == 1.0
 955           : fixed_hw_reg.dw1.d == 1;
 956 }
 957
 958 bool
 959 backend_reg::is_negative_one() const
 960 {
 961    if (file != IMM)
 962       return false;
 963
 964    switch (type) {
 965    case BRW_REGISTER_TYPE_F:
 966       return fixed_hw_reg.dw1.f == -1.0;
 967    case BRW_REGISTER_TYPE_D:
 968       return fixed_hw_reg.dw1.d == -1;
 969    default:
 970       return false;
 971    }
 972 }
 973
 974 bool
 975 backend_reg::is_null() const
 976 {
 977    return file == HW_REG &&
 978           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 979           fixed_hw_reg.nr == BRW_ARF_NULL;
 980 }
 981
 982
 983 bool
 984 backend_reg::is_accumulator() const
 985 {
 986    return file == HW_REG &&
 987           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 988           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 989 }
 990
 991 bool
 992 backend_reg::in_range(const backend_reg &r, unsigned n) const
 993 {
 994    return (file == r.file &&
 995            reg == r.reg &&
 996            reg_offset >= r.reg_offset &&
 997            reg_offset < r.reg_offset + n);
 998 }
 999
1000 bool
1001 backend_instruction::is_commutative() const
1002 {
1003    switch (opcode) {
1004    case BRW_OPCODE_AND:
1005    case BRW_OPCODE_OR:
1006    case BRW_OPCODE_XOR:
1007    case BRW_OPCODE_ADD:
1008    case BRW_OPCODE_MUL:
1009    case SHADER_OPCODE_MULH:
1010       return true;
1011    case BRW_OPCODE_SEL:
1012       /* MIN and MAX are commutative. */
1013       if (conditional_mod == BRW_CONDITIONAL_GE ||
1014           conditional_mod == BRW_CONDITIONAL_L) {
1015          return true;
1016       }
1017       /* fallthrough */
1018    default:
1019       return false;
1020    }
1021 }
1022
1023 bool
1024 backend_instruction::is_3src() const
1025 {
1026    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
1027 }
1028
1029 bool
1030 backend_instruction::is_tex() const
1031 {
1032    return (opcode == SHADER_OPCODE_TEX ||
1033            opcode == FS_OPCODE_TXB ||
1034            opcode == SHADER_OPCODE_TXD ||
1035            opcode == SHADER_OPCODE_TXF ||
1036            opcode == SHADER_OPCODE_TXF_CMS ||
1037            opcode == SHADER_OPCODE_TXF_UMS ||
1038            opcode == SHADER_OPCODE_TXF_MCS ||
1039            opcode == SHADER_OPCODE_TXL ||
1040            opcode == SHADER_OPCODE_TXS ||
1041            opcode == SHADER_OPCODE_LOD ||
1042            opcode == SHADER_OPCODE_TG4 ||
1043            opcode == SHADER_OPCODE_TG4_OFFSET);
1044 }
1045
1046 bool
1047 backend_instruction::is_math() const
1048 {
1049    return (opcode == SHADER_OPCODE_RCP ||
1050            opcode == SHADER_OPCODE_RSQ ||
1051            opcode == SHADER_OPCODE_SQRT ||
1052            opcode == SHADER_OPCODE_EXP2 ||
1053            opcode == SHADER_OPCODE_LOG2 ||
1054            opcode == SHADER_OPCODE_SIN ||
1055            opcode == SHADER_OPCODE_COS ||
1056            opcode == SHADER_OPCODE_INT_QUOTIENT ||
1057            opcode == SHADER_OPCODE_INT_REMAINDER ||
1058            opcode == SHADER_OPCODE_POW);
1059 }
1060
1061 bool
1062 backend_instruction::is_control_flow() const
1063 {
1064    switch (opcode) {
1065    case BRW_OPCODE_DO:
1066    case BRW_OPCODE_WHILE:
1067    case BRW_OPCODE_IF:
1068    case BRW_OPCODE_ELSE:
1069    case BRW_OPCODE_ENDIF:
1070    case BRW_OPCODE_BREAK:
1071    case BRW_OPCODE_CONTINUE:
1072       return true;
1073    default:
1074       return false;
1075    }
1076 }
1077
1078 bool
1079 backend_instruction::can_do_source_mods() const
1080 {
1081    switch (opcode) {
1082    case BRW_OPCODE_ADDC:
1083    case BRW_OPCODE_BFE:
1084    case BRW_OPCODE_BFI1:
1085    case BRW_OPCODE_BFI2:
1086    case BRW_OPCODE_BFREV:
1087    case BRW_OPCODE_CBIT:
1088    case BRW_OPCODE_FBH:
1089    case BRW_OPCODE_FBL:
1090    case BRW_OPCODE_SUBB:
1091       return false;
1092    default:
1093       return true;
1094    }
1095 }
1096
1097 bool
1098 backend_instruction::can_do_saturate() const
1099 {
1100    switch (opcode) {
1101    case BRW_OPCODE_ADD:
1102    case BRW_OPCODE_ASR:
1103    case BRW_OPCODE_AVG:
1104    case BRW_OPCODE_DP2:
1105    case BRW_OPCODE_DP3:
1106    case BRW_OPCODE_DP4:
1107    case BRW_OPCODE_DPH:
1108    case BRW_OPCODE_F16TO32:
1109    case BRW_OPCODE_F32TO16:
1110    case BRW_OPCODE_LINE:
1111    case BRW_OPCODE_LRP:
1112    case BRW_OPCODE_MAC:
1113    case BRW_OPCODE_MAD:
1114    case BRW_OPCODE_MATH:
1115    case BRW_OPCODE_MOV:
1116    case BRW_OPCODE_MUL:
1117    case SHADER_OPCODE_MULH:
1118    case BRW_OPCODE_PLN:
1119    case BRW_OPCODE_RNDD:
1120    case BRW_OPCODE_RNDE:
1121    case BRW_OPCODE_RNDU:
1122    case BRW_OPCODE_RNDZ:
1123    case BRW_OPCODE_SEL:
1124    case BRW_OPCODE_SHL:
1125    case BRW_OPCODE_SHR:
1126    case FS_OPCODE_LINTERP:
1127    case SHADER_OPCODE_COS:
1128    case SHADER_OPCODE_EXP2:
1129    case SHADER_OPCODE_LOG2:
1130    case SHADER_OPCODE_POW:
1131    case SHADER_OPCODE_RCP:
1132    case SHADER_OPCODE_RSQ:
1133    case SHADER_OPCODE_SIN:
1134    case SHADER_OPCODE_SQRT:
1135       return true;
1136    default:
1137       return false;
1138    }
1139 }
1140
1141 bool
1142 backend_instruction::can_do_cmod() const
1143 {
1144    switch (opcode) {
1145    case BRW_OPCODE_ADD:
1146    case BRW_OPCODE_ADDC:
1147    case BRW_OPCODE_AND:
1148    case BRW_OPCODE_ASR:
1149    case BRW_OPCODE_AVG:
1150    case BRW_OPCODE_CMP:
1151    case BRW_OPCODE_CMPN:
1152    case BRW_OPCODE_DP2:
1153    case BRW_OPCODE_DP3:
1154    case BRW_OPCODE_DP4:
1155    case BRW_OPCODE_DPH:
1156    case BRW_OPCODE_F16TO32:
1157    case BRW_OPCODE_F32TO16:
1158    case BRW_OPCODE_FRC:
1159    case BRW_OPCODE_LINE:
1160    case BRW_OPCODE_LRP:
1161    case BRW_OPCODE_LZD:
1162    case BRW_OPCODE_MAC:
1163    case BRW_OPCODE_MACH:
1164    case BRW_OPCODE_MAD:
1165    case BRW_OPCODE_MOV:
1166    case BRW_OPCODE_MUL:
1167    case BRW_OPCODE_NOT:
1168    case BRW_OPCODE_OR:
1169    case BRW_OPCODE_PLN:
1170    case BRW_OPCODE_RNDD:
1171    case BRW_OPCODE_RNDE:
1172    case BRW_OPCODE_RNDU:
1173    case BRW_OPCODE_RNDZ:
1174    case BRW_OPCODE_SAD2:
1175    case BRW_OPCODE_SADA2:
1176    case BRW_OPCODE_SHL:
1177    case BRW_OPCODE_SHR:
1178    case BRW_OPCODE_SUBB:
1179    case BRW_OPCODE_XOR:
1180    case FS_OPCODE_CINTERP:
1181    case FS_OPCODE_LINTERP:
1182       return true;
1183    default:
1184       return false;
1185    }
1186 }
1187
1188 bool
1189 backend_instruction::reads_accumulator_implicitly() const
1190 {
1191    switch (opcode) {
1192    case BRW_OPCODE_MAC:
1193    case BRW_OPCODE_MACH:
1194    case BRW_OPCODE_SADA2:
1195       return true;
1196    default:
1197       return false;
1198    }
1199 }
1200
1201 bool
1202 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1203 {
1204    return writes_accumulator ||
1205           (devinfo->gen < 6 &&
1206            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1207             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1208              opcode != FS_OPCODE_CINTERP)));
1209 }
1210
1211 bool
1212 backend_instruction::has_side_effects() const
1213 {
1214    switch (opcode) {
1215    case SHADER_OPCODE_UNTYPED_ATOMIC:
1216    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1217    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1218    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1219    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1220    case SHADER_OPCODE_TYPED_ATOMIC:
1221    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1222    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1223    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1224    case SHADER_OPCODE_MEMORY_FENCE:
1225    case SHADER_OPCODE_URB_WRITE_SIMD8:
1226    case FS_OPCODE_FB_WRITE:
1227    case SHADER_OPCODE_BARRIER:
1228       return true;
1229    default:
1230       return false;
1231    }
1232 }
1233
1234 #ifndef NDEBUG
1235 static bool
1236 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1237 {
1238    bool found = false;
1239    foreach_inst_in_block (backend_instruction, i, block) {
1240       if (inst == i) {
1241          found = true;
1242       }
1243    }
1244    return found;
1245 }
1246 #endif
1247
1248 static void
1249 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1250 {
1251    for (bblock_t *block_iter = start_block->next();
1252         !block_iter->link.is_tail_sentinel();
1253         block_iter = block_iter->next()) {
1254       block_iter->start_ip += ip_adjustment;
1255       block_iter->end_ip += ip_adjustment;
1256    }
1257 }
1258
1259 void
1260 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1261 {
1262    if (!this->is_head_sentinel())
1263       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1264
1265    block->end_ip++;
1266
1267    adjust_later_block_ips(block, 1);
1268
1269    exec_node::insert_after(inst);
1270 }
1271
1272 void
1273 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1274 {
1275    if (!this->is_tail_sentinel())
1276       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1277
1278    block->end_ip++;
1279
1280    adjust_later_block_ips(block, 1);
1281
1282    exec_node::insert_before(inst);
1283 }
1284
1285 void
1286 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1287 {
1288    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1289
1290    unsigned num_inst = list->length();
1291
1292    block->end_ip += num_inst;
1293
1294    adjust_later_block_ips(block, num_inst);
1295
1296    exec_node::insert_before(list);
1297 }
1298
1299 void
1300 backend_instruction::remove(bblock_t *block)
1301 {
1302    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1303
1304    adjust_later_block_ips(block, -1);
1305
1306    if (block->start_ip == block->end_ip) {
1307       block->cfg->remove_block(block);
1308    } else {
1309       block->end_ip--;
1310    }
1311
1312    exec_node::remove();
1313 }
1314
1315 void
1316 backend_shader::dump_instructions()
1317 {
1318    dump_instructions(NULL);
1319 }
1320
1321 void
1322 backend_shader::dump_instructions(const char *name)
1323 {
1324    FILE *file = stderr;
1325    if (name && geteuid() != 0) {
1326       file = fopen(name, "w");
1327       if (!file)
1328          file = stderr;
1329    }
1330
1331    if (cfg) {
1332       int ip = 0;
1333       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1334          fprintf(file, "%4d: ", ip++);
1335          dump_instruction(inst, file);
1336       }
1337    } else {
1338       int ip = 0;
1339       foreach_in_list(backend_instruction, inst, &instructions) {
1340          fprintf(file, "%4d: ", ip++);
1341          dump_instruction(inst, file);
1342       }
1343    }
1344
1345    if (file != stderr) {
1346       fclose(file);
1347    }
1348 }
1349
1350 void
1351 backend_shader::calculate_cfg()
1352 {
1353    if (this->cfg)
1354       return;
1355    cfg = new(mem_ctx) cfg_t(&this->instructions);
1356 }
1357
1358 void
1359 backend_shader::invalidate_cfg()
1360 {
1361    ralloc_free(this->cfg);
1362    this->cfg = NULL;
1363 }
1364
1365 /**
1366  * Sets up the starting offsets for the groups of binding table entries
1367  * commong to all pipeline stages.
1368  *
1369  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1370  * unused but also make sure that addition of small offsets to them will
1371  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1372  */
1373 void
1374 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1375 {
1376    int num_textures = _mesa_fls(prog->SamplersUsed);
1377
1378    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1379    next_binding_table_offset += num_textures;
1380
1381    if (shader) {
1382       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1383       next_binding_table_offset += shader->base.NumUniformBlocks;
1384    } else {
1385       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1386    }
1387
1388    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1389       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1390       next_binding_table_offset++;
1391    } else {
1392       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1393    }
1394
1395    if (prog->UsesGather) {
1396       if (devinfo->gen >= 8) {
1397          stage_prog_data->binding_table.gather_texture_start =
1398             stage_prog_data->binding_table.texture_start;
1399       } else {
1400          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1401          next_binding_table_offset += num_textures;
1402       }
1403    } else {
1404       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1405    }
1406
1407    if (shader_prog && shader_prog->NumAtomicBuffers) {
1408       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1409       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1410    } else {
1411       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1412    }
1413
1414    if (shader && shader->base.NumImages) {
1415       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1416       next_binding_table_offset += shader->base.NumImages;
1417    } else {
1418       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1419    }
1420
1421    /* This may or may not be used depending on how the compile goes. */
1422    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1423    next_binding_table_offset++;
1424
1425    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1426
1427    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1428 }
1429
1430 void
1431 backend_shader::setup_image_uniform_values(unsigned param_offset,
1432                                            const gl_uniform_storage *storage)
1433 {
1434    const unsigned stage = _mesa_program_enum_to_shader_stage(prog->Target);
1435
1436    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1437       const unsigned image_idx = storage->image[stage].index + i;
1438       const brw_image_param *param = &stage_prog_data->image_param[image_idx];
1439
1440       /* Upload the brw_image_param structure.  The order is expected to match
1441        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1442        */
1443       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1444          (const gl_constant_value *)&param->surface_idx, 1);
1445       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1446          (const gl_constant_value *)param->offset, 2);
1447       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SIZE_OFFSET,
1448          (const gl_constant_value *)param->size, 3);
1449       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1450          (const gl_constant_value *)param->stride, 4);
1451       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_TILING_OFFSET,
1452          (const gl_constant_value *)param->tiling, 3);
1453       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1454          (const gl_constant_value *)param->swizzling, 2);
1455       param_offset += BRW_IMAGE_PARAM_SIZE;
1456
1457       brw_mark_surface_used(
1458          stage_prog_data,
1459          stage_prog_data->binding_table.image_start + image_idx);
1460    }
1461 }