src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_nir.h"
  28 #include "glsl/glsl_parser_extras.h"
  29 #include "main/shaderobj.h"
  30 #include "main/uniforms.h"
  31 #include "util/debug.h"
  32
  33 static void
  34 shader_debug_log_mesa(void *data, const char *fmt, ...)
  35 {
  36    struct brw_context *brw = (struct brw_context *)data;
  37    va_list args;
  38
  39    va_start(args, fmt);
  40    GLuint msg_id = 0;
  41    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  42                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  43                    MESA_DEBUG_TYPE_OTHER,
  44                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  45    va_end(args);
  46 }
  47
  48 static void
  49 shader_perf_log_mesa(void *data, const char *fmt, ...)
  50 {
  51    struct brw_context *brw = (struct brw_context *)data;
  52
  53    va_list args;
  54    va_start(args, fmt);
  55
  56    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  57       va_list args_copy;
  58       va_copy(args_copy, args);
  59       vfprintf(stderr, fmt, args_copy);
  60       va_end(args_copy);
  61    }
  62
  63    if (brw->perf_debug) {
  64       GLuint msg_id = 0;
  65       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  66                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  67                       MESA_DEBUG_TYPE_PERFORMANCE,
  68                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  69    }
  70    va_end(args);
  71 }
  72
  73 struct brw_compiler *
  74 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  75 {
  76    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  77
  78    compiler->devinfo = devinfo;
  79    compiler->shader_debug_log = shader_debug_log_mesa;
  80    compiler->shader_perf_log = shader_perf_log_mesa;
  81
  82    brw_fs_alloc_reg_sets(compiler);
  83    brw_vec4_alloc_reg_set(compiler);
  84
  85    compiler->scalar_stage[MESA_SHADER_VERTEX] =
  86       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
  87    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
  88       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", false);
  89    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
  90    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
  91
  92    nir_shader_compiler_options *nir_options =
  93       rzalloc(compiler, nir_shader_compiler_options);
  94    nir_options->native_integers = true;
  95    /* In order to help allow for better CSE at the NIR level we tell NIR
  96     * to split all ffma instructions during opt_algebraic and we then
  97     * re-combine them as a later step.
  98     */
  99    nir_options->lower_ffma = true;
 100    nir_options->lower_sub = true;
 101    nir_options->lower_fdiv = true;
 102
 103    /* In the vec4 backend, our dpN instruction replicates its result to all
 104     * the components of a vec4.  We would like NIR to give us replicated fdot
 105     * instructions because it can optimize better for us.
 106     *
 107     * For the FS backend, it should be lowered away by the scalarizing pass so
 108     * we should never see fdot anyway.
 109     */
 110    nir_options->fdot_replicates = true;
 111
 112    /* We want the GLSL compiler to emit code that uses condition codes */
 113    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 114       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 115       compiler->glsl_compiler_options[i].MaxIfDepth =
 116          devinfo->gen < 6 ? 16 : UINT_MAX;
 117
 118       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 119       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 120       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 121       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 122       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 123       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 124
 125       bool is_scalar = compiler->scalar_stage[i];
 126
 127       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 128       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 129       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 130
 131       /* !ARB_gpu_shader5 */
 132       if (devinfo->gen < 7)
 133          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 134
 135       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 136
 137       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 138    }
 139
 140    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 141       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 142
 143    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 144       .LowerShaderSharedVariables = true;
 145
 146    return compiler;
 147 }
 148
 149 extern "C" struct gl_shader *
 150 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 151 {
 152    struct brw_shader *shader;
 153
 154    shader = rzalloc(NULL, struct brw_shader);
 155    if (shader) {
 156       shader->base.Type = type;
 157       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 158       shader->base.Name = name;
 159       _mesa_init_shader(ctx, &shader->base);
 160    }
 161
 162    return &shader->base;
 163 }
 164
 165 extern "C" void
 166 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 167                       unsigned surf_index)
 168 {
 169    assert(surf_index < BRW_MAX_SURFACES);
 170
 171    prog_data->binding_table.size_bytes =
 172       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 173 }
 174
 175 enum brw_reg_type
 176 brw_type_for_base_type(const struct glsl_type *type)
 177 {
 178    switch (type->base_type) {
 179    case GLSL_TYPE_FLOAT:
 180       return BRW_REGISTER_TYPE_F;
 181    case GLSL_TYPE_INT:
 182    case GLSL_TYPE_BOOL:
 183    case GLSL_TYPE_SUBROUTINE:
 184       return BRW_REGISTER_TYPE_D;
 185    case GLSL_TYPE_UINT:
 186       return BRW_REGISTER_TYPE_UD;
 187    case GLSL_TYPE_ARRAY:
 188       return brw_type_for_base_type(type->fields.array);
 189    case GLSL_TYPE_STRUCT:
 190    case GLSL_TYPE_SAMPLER:
 191    case GLSL_TYPE_ATOMIC_UINT:
 192       /* These should be overridden with the type of the member when
 193        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 194        * way to trip up if we don't.
 195        */
 196       return BRW_REGISTER_TYPE_UD;
 197    case GLSL_TYPE_IMAGE:
 198       return BRW_REGISTER_TYPE_UD;
 199    case GLSL_TYPE_VOID:
 200    case GLSL_TYPE_ERROR:
 201    case GLSL_TYPE_INTERFACE:
 202    case GLSL_TYPE_DOUBLE:
 203    case GLSL_TYPE_FUNCTION:
 204       unreachable("not reached");
 205    }
 206
 207    return BRW_REGISTER_TYPE_F;
 208 }
 209
 210 enum brw_conditional_mod
 211 brw_conditional_for_comparison(unsigned int op)
 212 {
 213    switch (op) {
 214    case ir_binop_less:
 215       return BRW_CONDITIONAL_L;
 216    case ir_binop_greater:
 217       return BRW_CONDITIONAL_G;
 218    case ir_binop_lequal:
 219       return BRW_CONDITIONAL_LE;
 220    case ir_binop_gequal:
 221       return BRW_CONDITIONAL_GE;
 222    case ir_binop_equal:
 223    case ir_binop_all_equal: /* same as equal for scalars */
 224       return BRW_CONDITIONAL_Z;
 225    case ir_binop_nequal:
 226    case ir_binop_any_nequal: /* same as nequal for scalars */
 227       return BRW_CONDITIONAL_NZ;
 228    default:
 229       unreachable("not reached: bad operation for comparison");
 230    }
 231 }
 232
 233 uint32_t
 234 brw_math_function(enum opcode op)
 235 {
 236    switch (op) {
 237    case SHADER_OPCODE_RCP:
 238       return BRW_MATH_FUNCTION_INV;
 239    case SHADER_OPCODE_RSQ:
 240       return BRW_MATH_FUNCTION_RSQ;
 241    case SHADER_OPCODE_SQRT:
 242       return BRW_MATH_FUNCTION_SQRT;
 243    case SHADER_OPCODE_EXP2:
 244       return BRW_MATH_FUNCTION_EXP;
 245    case SHADER_OPCODE_LOG2:
 246       return BRW_MATH_FUNCTION_LOG;
 247    case SHADER_OPCODE_POW:
 248       return BRW_MATH_FUNCTION_POW;
 249    case SHADER_OPCODE_SIN:
 250       return BRW_MATH_FUNCTION_SIN;
 251    case SHADER_OPCODE_COS:
 252       return BRW_MATH_FUNCTION_COS;
 253    case SHADER_OPCODE_INT_QUOTIENT:
 254       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 255    case SHADER_OPCODE_INT_REMAINDER:
 256       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 257    default:
 258       unreachable("not reached: unknown math function");
 259    }
 260 }
 261
 262 uint32_t
 263 brw_texture_offset(int *offsets, unsigned num_components)
 264 {
 265    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 266
 267    /* Combine all three offsets into a single unsigned dword:
 268     *
 269     *    bits 11:8 - U Offset (X component)
 270     *    bits  7:4 - V Offset (Y component)
 271     *    bits  3:0 - R Offset (Z component)
 272     */
 273    unsigned offset_bits = 0;
 274    for (unsigned i = 0; i < num_components; i++) {
 275       const unsigned shift = 4 * (2 - i);
 276       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 277    }
 278    return offset_bits;
 279 }
 280
 281 const char *
 282 brw_instruction_name(enum opcode op)
 283 {
 284    switch (op) {
 285    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 286       assert(opcode_descs[op].name);
 287       return opcode_descs[op].name;
 288    case FS_OPCODE_FB_WRITE:
 289       return "fb_write";
 290    case FS_OPCODE_FB_WRITE_LOGICAL:
 291       return "fb_write_logical";
 292    case FS_OPCODE_PACK_STENCIL_REF:
 293       return "pack_stencil_ref";
 294    case FS_OPCODE_BLORP_FB_WRITE:
 295       return "blorp_fb_write";
 296    case FS_OPCODE_REP_FB_WRITE:
 297       return "rep_fb_write";
 298
 299    case SHADER_OPCODE_RCP:
 300       return "rcp";
 301    case SHADER_OPCODE_RSQ:
 302       return "rsq";
 303    case SHADER_OPCODE_SQRT:
 304       return "sqrt";
 305    case SHADER_OPCODE_EXP2:
 306       return "exp2";
 307    case SHADER_OPCODE_LOG2:
 308       return "log2";
 309    case SHADER_OPCODE_POW:
 310       return "pow";
 311    case SHADER_OPCODE_INT_QUOTIENT:
 312       return "int_quot";
 313    case SHADER_OPCODE_INT_REMAINDER:
 314       return "int_rem";
 315    case SHADER_OPCODE_SIN:
 316       return "sin";
 317    case SHADER_OPCODE_COS:
 318       return "cos";
 319
 320    case SHADER_OPCODE_TEX:
 321       return "tex";
 322    case SHADER_OPCODE_TEX_LOGICAL:
 323       return "tex_logical";
 324    case SHADER_OPCODE_TXD:
 325       return "txd";
 326    case SHADER_OPCODE_TXD_LOGICAL:
 327       return "txd_logical";
 328    case SHADER_OPCODE_TXF:
 329       return "txf";
 330    case SHADER_OPCODE_TXF_LOGICAL:
 331       return "txf_logical";
 332    case SHADER_OPCODE_TXL:
 333       return "txl";
 334    case SHADER_OPCODE_TXL_LOGICAL:
 335       return "txl_logical";
 336    case SHADER_OPCODE_TXS:
 337       return "txs";
 338    case SHADER_OPCODE_TXS_LOGICAL:
 339       return "txs_logical";
 340    case FS_OPCODE_TXB:
 341       return "txb";
 342    case FS_OPCODE_TXB_LOGICAL:
 343       return "txb_logical";
 344    case SHADER_OPCODE_TXF_CMS:
 345       return "txf_cms";
 346    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 347       return "txf_cms_logical";
 348    case SHADER_OPCODE_TXF_CMS_W:
 349       return "txf_cms_w";
 350    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 351       return "txf_cms_w_logical";
 352    case SHADER_OPCODE_TXF_UMS:
 353       return "txf_ums";
 354    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 355       return "txf_ums_logical";
 356    case SHADER_OPCODE_TXF_MCS:
 357       return "txf_mcs";
 358    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 359       return "txf_mcs_logical";
 360    case SHADER_OPCODE_LOD:
 361       return "lod";
 362    case SHADER_OPCODE_LOD_LOGICAL:
 363       return "lod_logical";
 364    case SHADER_OPCODE_TG4:
 365       return "tg4";
 366    case SHADER_OPCODE_TG4_LOGICAL:
 367       return "tg4_logical";
 368    case SHADER_OPCODE_TG4_OFFSET:
 369       return "tg4_offset";
 370    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 371       return "tg4_offset_logical";
 372    case SHADER_OPCODE_SAMPLEINFO:
 373       return "sampleinfo";
 374
 375    case SHADER_OPCODE_SHADER_TIME_ADD:
 376       return "shader_time_add";
 377
 378    case SHADER_OPCODE_UNTYPED_ATOMIC:
 379       return "untyped_atomic";
 380    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 381       return "untyped_atomic_logical";
 382    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 383       return "untyped_surface_read";
 384    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 385       return "untyped_surface_read_logical";
 386    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 387       return "untyped_surface_write";
 388    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 389       return "untyped_surface_write_logical";
 390    case SHADER_OPCODE_TYPED_ATOMIC:
 391       return "typed_atomic";
 392    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 393       return "typed_atomic_logical";
 394    case SHADER_OPCODE_TYPED_SURFACE_READ:
 395       return "typed_surface_read";
 396    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 397       return "typed_surface_read_logical";
 398    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 399       return "typed_surface_write";
 400    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 401       return "typed_surface_write_logical";
 402    case SHADER_OPCODE_MEMORY_FENCE:
 403       return "memory_fence";
 404
 405    case SHADER_OPCODE_LOAD_PAYLOAD:
 406       return "load_payload";
 407
 408    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 409       return "gen4_scratch_read";
 410    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 411       return "gen4_scratch_write";
 412    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 413       return "gen7_scratch_read";
 414    case SHADER_OPCODE_URB_WRITE_SIMD8:
 415       return "gen8_urb_write_simd8";
 416    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 417       return "gen8_urb_write_simd8_per_slot";
 418    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 419       return "gen8_urb_write_simd8_masked";
 420    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 421       return "gen8_urb_write_simd8_masked_per_slot";
 422    case SHADER_OPCODE_URB_READ_SIMD8:
 423       return "urb_read_simd8";
 424    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 425       return "urb_read_simd8_per_slot";
 426
 427    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 428       return "find_live_channel";
 429    case SHADER_OPCODE_BROADCAST:
 430       return "broadcast";
 431
 432    case VEC4_OPCODE_MOV_BYTES:
 433       return "mov_bytes";
 434    case VEC4_OPCODE_PACK_BYTES:
 435       return "pack_bytes";
 436    case VEC4_OPCODE_UNPACK_UNIFORM:
 437       return "unpack_uniform";
 438
 439    case FS_OPCODE_DDX_COARSE:
 440       return "ddx_coarse";
 441    case FS_OPCODE_DDX_FINE:
 442       return "ddx_fine";
 443    case FS_OPCODE_DDY_COARSE:
 444       return "ddy_coarse";
 445    case FS_OPCODE_DDY_FINE:
 446       return "ddy_fine";
 447
 448    case FS_OPCODE_CINTERP:
 449       return "cinterp";
 450    case FS_OPCODE_LINTERP:
 451       return "linterp";
 452
 453    case FS_OPCODE_PIXEL_X:
 454       return "pixel_x";
 455    case FS_OPCODE_PIXEL_Y:
 456       return "pixel_y";
 457
 458    case FS_OPCODE_GET_BUFFER_SIZE:
 459       return "fs_get_buffer_size";
 460
 461    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 462       return "uniform_pull_const";
 463    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 464       return "uniform_pull_const_gen7";
 465    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 466       return "varying_pull_const";
 467    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 468       return "varying_pull_const_gen7";
 469
 470    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 471       return "mov_dispatch_to_flags";
 472    case FS_OPCODE_DISCARD_JUMP:
 473       return "discard_jump";
 474
 475    case FS_OPCODE_SET_SAMPLE_ID:
 476       return "set_sample_id";
 477    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 478       return "set_simd4x2_offset";
 479
 480    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 481       return "pack_half_2x16_split";
 482    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 483       return "unpack_half_2x16_split_x";
 484    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 485       return "unpack_half_2x16_split_y";
 486
 487    case FS_OPCODE_PLACEHOLDER_HALT:
 488       return "placeholder_halt";
 489
 490    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 491       return "interp_centroid";
 492    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 493       return "interp_sample";
 494    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 495       return "interp_shared_offset";
 496    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 497       return "interp_per_slot_offset";
 498
 499    case VS_OPCODE_URB_WRITE:
 500       return "vs_urb_write";
 501    case VS_OPCODE_PULL_CONSTANT_LOAD:
 502       return "pull_constant_load";
 503    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 504       return "pull_constant_load_gen7";
 505
 506    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 507       return "set_simd4x2_header_gen9";
 508
 509    case VS_OPCODE_GET_BUFFER_SIZE:
 510       return "vs_get_buffer_size";
 511
 512    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 513       return "unpack_flags_simd4x2";
 514
 515    case GS_OPCODE_URB_WRITE:
 516       return "gs_urb_write";
 517    case GS_OPCODE_URB_WRITE_ALLOCATE:
 518       return "gs_urb_write_allocate";
 519    case GS_OPCODE_THREAD_END:
 520       return "gs_thread_end";
 521    case GS_OPCODE_SET_WRITE_OFFSET:
 522       return "set_write_offset";
 523    case GS_OPCODE_SET_VERTEX_COUNT:
 524       return "set_vertex_count";
 525    case GS_OPCODE_SET_DWORD_2:
 526       return "set_dword_2";
 527    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 528       return "prepare_channel_masks";
 529    case GS_OPCODE_SET_CHANNEL_MASKS:
 530       return "set_channel_masks";
 531    case GS_OPCODE_GET_INSTANCE_ID:
 532       return "get_instance_id";
 533    case GS_OPCODE_FF_SYNC:
 534       return "ff_sync";
 535    case GS_OPCODE_SET_PRIMITIVE_ID:
 536       return "set_primitive_id";
 537    case GS_OPCODE_SVB_WRITE:
 538       return "gs_svb_write";
 539    case GS_OPCODE_SVB_SET_DST_INDEX:
 540       return "gs_svb_set_dst_index";
 541    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 542       return "gs_ff_sync_set_primitives";
 543    case CS_OPCODE_CS_TERMINATE:
 544       return "cs_terminate";
 545    case SHADER_OPCODE_BARRIER:
 546       return "barrier";
 547    case SHADER_OPCODE_MULH:
 548       return "mulh";
 549    case SHADER_OPCODE_MOV_INDIRECT:
 550       return "mov_indirect";
 551    }
 552
 553    unreachable("not reached");
 554 }
 555
 556 bool
 557 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 558 {
 559    union {
 560       unsigned ud;
 561       int d;
 562       float f;
 563    } imm = { reg->ud }, sat_imm = { 0 };
 564
 565    switch (type) {
 566    case BRW_REGISTER_TYPE_UD:
 567    case BRW_REGISTER_TYPE_D:
 568    case BRW_REGISTER_TYPE_UW:
 569    case BRW_REGISTER_TYPE_W:
 570    case BRW_REGISTER_TYPE_UQ:
 571    case BRW_REGISTER_TYPE_Q:
 572       /* Nothing to do. */
 573       return false;
 574    case BRW_REGISTER_TYPE_F:
 575       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 576       break;
 577    case BRW_REGISTER_TYPE_UB:
 578    case BRW_REGISTER_TYPE_B:
 579       unreachable("no UB/B immediates");
 580    case BRW_REGISTER_TYPE_V:
 581    case BRW_REGISTER_TYPE_UV:
 582    case BRW_REGISTER_TYPE_VF:
 583       unreachable("unimplemented: saturate vector immediate");
 584    case BRW_REGISTER_TYPE_DF:
 585    case BRW_REGISTER_TYPE_HF:
 586       unreachable("unimplemented: saturate DF/HF immediate");
 587    }
 588
 589    if (imm.ud != sat_imm.ud) {
 590       reg->ud = sat_imm.ud;
 591       return true;
 592    }
 593    return false;
 594 }
 595
 596 bool
 597 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 598 {
 599    switch (type) {
 600    case BRW_REGISTER_TYPE_D:
 601    case BRW_REGISTER_TYPE_UD:
 602       reg->d = -reg->d;
 603       return true;
 604    case BRW_REGISTER_TYPE_W:
 605    case BRW_REGISTER_TYPE_UW:
 606       reg->d = -(int16_t)reg->ud;
 607       return true;
 608    case BRW_REGISTER_TYPE_F:
 609       reg->f = -reg->f;
 610       return true;
 611    case BRW_REGISTER_TYPE_VF:
 612       reg->ud ^= 0x80808080;
 613       return true;
 614    case BRW_REGISTER_TYPE_UB:
 615    case BRW_REGISTER_TYPE_B:
 616       unreachable("no UB/B immediates");
 617    case BRW_REGISTER_TYPE_UV:
 618    case BRW_REGISTER_TYPE_V:
 619       assert(!"unimplemented: negate UV/V immediate");
 620    case BRW_REGISTER_TYPE_UQ:
 621    case BRW_REGISTER_TYPE_Q:
 622       assert(!"unimplemented: negate UQ/Q immediate");
 623    case BRW_REGISTER_TYPE_DF:
 624    case BRW_REGISTER_TYPE_HF:
 625       assert(!"unimplemented: negate DF/HF immediate");
 626    }
 627
 628    return false;
 629 }
 630
 631 bool
 632 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 633 {
 634    switch (type) {
 635    case BRW_REGISTER_TYPE_D:
 636       reg->d = abs(reg->d);
 637       return true;
 638    case BRW_REGISTER_TYPE_W:
 639       reg->d = abs((int16_t)reg->ud);
 640       return true;
 641    case BRW_REGISTER_TYPE_F:
 642       reg->f = fabsf(reg->f);
 643       return true;
 644    case BRW_REGISTER_TYPE_VF:
 645       reg->ud &= ~0x80808080;
 646       return true;
 647    case BRW_REGISTER_TYPE_UB:
 648    case BRW_REGISTER_TYPE_B:
 649       unreachable("no UB/B immediates");
 650    case BRW_REGISTER_TYPE_UQ:
 651    case BRW_REGISTER_TYPE_UD:
 652    case BRW_REGISTER_TYPE_UW:
 653    case BRW_REGISTER_TYPE_UV:
 654       /* Presumably the absolute value modifier on an unsigned source is a
 655        * nop, but it would be nice to confirm.
 656        */
 657       assert(!"unimplemented: abs unsigned immediate");
 658    case BRW_REGISTER_TYPE_V:
 659       assert(!"unimplemented: abs V immediate");
 660    case BRW_REGISTER_TYPE_Q:
 661       assert(!"unimplemented: abs Q immediate");
 662    case BRW_REGISTER_TYPE_DF:
 663    case BRW_REGISTER_TYPE_HF:
 664       assert(!"unimplemented: abs DF/HF immediate");
 665    }
 666
 667    return false;
 668 }
 669
 670 backend_shader::backend_shader(const struct brw_compiler *compiler,
 671                                void *log_data,
 672                                void *mem_ctx,
 673                                const nir_shader *shader,
 674                                struct brw_stage_prog_data *stage_prog_data)
 675    : compiler(compiler),
 676      log_data(log_data),
 677      devinfo(compiler->devinfo),
 678      nir(shader),
 679      stage_prog_data(stage_prog_data),
 680      mem_ctx(mem_ctx),
 681      cfg(NULL),
 682      stage(shader->stage)
 683 {
 684    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 685    stage_name = _mesa_shader_stage_to_string(stage);
 686    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 687 }
 688
 689 bool
 690 backend_reg::equals(const backend_reg &r) const
 691 {
 692    return memcmp((brw_reg *)this, (brw_reg *)&r, sizeof(brw_reg)) == 0 &&
 693           reg_offset == r.reg_offset;
 694 }
 695
 696 bool
 697 backend_reg::is_zero() const
 698 {
 699    if (file != IMM)
 700       return false;
 701
 702    return d == 0;
 703 }
 704
 705 bool
 706 backend_reg::is_one() const
 707 {
 708    if (file != IMM)
 709       return false;
 710
 711    return type == BRW_REGISTER_TYPE_F
 712           ? f == 1.0
 713           : d == 1;
 714 }
 715
 716 bool
 717 backend_reg::is_negative_one() const
 718 {
 719    if (file != IMM)
 720       return false;
 721
 722    switch (type) {
 723    case BRW_REGISTER_TYPE_F:
 724       return f == -1.0;
 725    case BRW_REGISTER_TYPE_D:
 726       return d == -1;
 727    default:
 728       return false;
 729    }
 730 }
 731
 732 bool
 733 backend_reg::is_null() const
 734 {
 735    return file == ARF && nr == BRW_ARF_NULL;
 736 }
 737
 738
 739 bool
 740 backend_reg::is_accumulator() const
 741 {
 742    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 743 }
 744
 745 bool
 746 backend_reg::in_range(const backend_reg &r, unsigned n) const
 747 {
 748    return (file == r.file &&
 749            nr == r.nr &&
 750            reg_offset >= r.reg_offset &&
 751            reg_offset < r.reg_offset + n);
 752 }
 753
 754 bool
 755 backend_instruction::is_commutative() const
 756 {
 757    switch (opcode) {
 758    case BRW_OPCODE_AND:
 759    case BRW_OPCODE_OR:
 760    case BRW_OPCODE_XOR:
 761    case BRW_OPCODE_ADD:
 762    case BRW_OPCODE_MUL:
 763    case SHADER_OPCODE_MULH:
 764       return true;
 765    case BRW_OPCODE_SEL:
 766       /* MIN and MAX are commutative. */
 767       if (conditional_mod == BRW_CONDITIONAL_GE ||
 768           conditional_mod == BRW_CONDITIONAL_L) {
 769          return true;
 770       }
 771       /* fallthrough */
 772    default:
 773       return false;
 774    }
 775 }
 776
 777 bool
 778 backend_instruction::is_3src() const
 779 {
 780    return ::is_3src(opcode);
 781 }
 782
 783 bool
 784 backend_instruction::is_tex() const
 785 {
 786    return (opcode == SHADER_OPCODE_TEX ||
 787            opcode == FS_OPCODE_TXB ||
 788            opcode == SHADER_OPCODE_TXD ||
 789            opcode == SHADER_OPCODE_TXF ||
 790            opcode == SHADER_OPCODE_TXF_CMS ||
 791            opcode == SHADER_OPCODE_TXF_CMS_W ||
 792            opcode == SHADER_OPCODE_TXF_UMS ||
 793            opcode == SHADER_OPCODE_TXF_MCS ||
 794            opcode == SHADER_OPCODE_TXL ||
 795            opcode == SHADER_OPCODE_TXS ||
 796            opcode == SHADER_OPCODE_LOD ||
 797            opcode == SHADER_OPCODE_TG4 ||
 798            opcode == SHADER_OPCODE_TG4_OFFSET);
 799 }
 800
 801 bool
 802 backend_instruction::is_math() const
 803 {
 804    return (opcode == SHADER_OPCODE_RCP ||
 805            opcode == SHADER_OPCODE_RSQ ||
 806            opcode == SHADER_OPCODE_SQRT ||
 807            opcode == SHADER_OPCODE_EXP2 ||
 808            opcode == SHADER_OPCODE_LOG2 ||
 809            opcode == SHADER_OPCODE_SIN ||
 810            opcode == SHADER_OPCODE_COS ||
 811            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 812            opcode == SHADER_OPCODE_INT_REMAINDER ||
 813            opcode == SHADER_OPCODE_POW);
 814 }
 815
 816 bool
 817 backend_instruction::is_control_flow() const
 818 {
 819    switch (opcode) {
 820    case BRW_OPCODE_DO:
 821    case BRW_OPCODE_WHILE:
 822    case BRW_OPCODE_IF:
 823    case BRW_OPCODE_ELSE:
 824    case BRW_OPCODE_ENDIF:
 825    case BRW_OPCODE_BREAK:
 826    case BRW_OPCODE_CONTINUE:
 827       return true;
 828    default:
 829       return false;
 830    }
 831 }
 832
 833 bool
 834 backend_instruction::can_do_source_mods() const
 835 {
 836    switch (opcode) {
 837    case BRW_OPCODE_ADDC:
 838    case BRW_OPCODE_BFE:
 839    case BRW_OPCODE_BFI1:
 840    case BRW_OPCODE_BFI2:
 841    case BRW_OPCODE_BFREV:
 842    case BRW_OPCODE_CBIT:
 843    case BRW_OPCODE_FBH:
 844    case BRW_OPCODE_FBL:
 845    case BRW_OPCODE_SUBB:
 846       return false;
 847    default:
 848       return true;
 849    }
 850 }
 851
 852 bool
 853 backend_instruction::can_do_saturate() const
 854 {
 855    switch (opcode) {
 856    case BRW_OPCODE_ADD:
 857    case BRW_OPCODE_ASR:
 858    case BRW_OPCODE_AVG:
 859    case BRW_OPCODE_DP2:
 860    case BRW_OPCODE_DP3:
 861    case BRW_OPCODE_DP4:
 862    case BRW_OPCODE_DPH:
 863    case BRW_OPCODE_F16TO32:
 864    case BRW_OPCODE_F32TO16:
 865    case BRW_OPCODE_LINE:
 866    case BRW_OPCODE_LRP:
 867    case BRW_OPCODE_MAC:
 868    case BRW_OPCODE_MAD:
 869    case BRW_OPCODE_MATH:
 870    case BRW_OPCODE_MOV:
 871    case BRW_OPCODE_MUL:
 872    case SHADER_OPCODE_MULH:
 873    case BRW_OPCODE_PLN:
 874    case BRW_OPCODE_RNDD:
 875    case BRW_OPCODE_RNDE:
 876    case BRW_OPCODE_RNDU:
 877    case BRW_OPCODE_RNDZ:
 878    case BRW_OPCODE_SEL:
 879    case BRW_OPCODE_SHL:
 880    case BRW_OPCODE_SHR:
 881    case FS_OPCODE_LINTERP:
 882    case SHADER_OPCODE_COS:
 883    case SHADER_OPCODE_EXP2:
 884    case SHADER_OPCODE_LOG2:
 885    case SHADER_OPCODE_POW:
 886    case SHADER_OPCODE_RCP:
 887    case SHADER_OPCODE_RSQ:
 888    case SHADER_OPCODE_SIN:
 889    case SHADER_OPCODE_SQRT:
 890       return true;
 891    default:
 892       return false;
 893    }
 894 }
 895
 896 bool
 897 backend_instruction::can_do_cmod() const
 898 {
 899    switch (opcode) {
 900    case BRW_OPCODE_ADD:
 901    case BRW_OPCODE_ADDC:
 902    case BRW_OPCODE_AND:
 903    case BRW_OPCODE_ASR:
 904    case BRW_OPCODE_AVG:
 905    case BRW_OPCODE_CMP:
 906    case BRW_OPCODE_CMPN:
 907    case BRW_OPCODE_DP2:
 908    case BRW_OPCODE_DP3:
 909    case BRW_OPCODE_DP4:
 910    case BRW_OPCODE_DPH:
 911    case BRW_OPCODE_F16TO32:
 912    case BRW_OPCODE_F32TO16:
 913    case BRW_OPCODE_FRC:
 914    case BRW_OPCODE_LINE:
 915    case BRW_OPCODE_LRP:
 916    case BRW_OPCODE_LZD:
 917    case BRW_OPCODE_MAC:
 918    case BRW_OPCODE_MACH:
 919    case BRW_OPCODE_MAD:
 920    case BRW_OPCODE_MOV:
 921    case BRW_OPCODE_MUL:
 922    case BRW_OPCODE_NOT:
 923    case BRW_OPCODE_OR:
 924    case BRW_OPCODE_PLN:
 925    case BRW_OPCODE_RNDD:
 926    case BRW_OPCODE_RNDE:
 927    case BRW_OPCODE_RNDU:
 928    case BRW_OPCODE_RNDZ:
 929    case BRW_OPCODE_SAD2:
 930    case BRW_OPCODE_SADA2:
 931    case BRW_OPCODE_SHL:
 932    case BRW_OPCODE_SHR:
 933    case BRW_OPCODE_SUBB:
 934    case BRW_OPCODE_XOR:
 935    case FS_OPCODE_CINTERP:
 936    case FS_OPCODE_LINTERP:
 937       return true;
 938    default:
 939       return false;
 940    }
 941 }
 942
 943 bool
 944 backend_instruction::reads_accumulator_implicitly() const
 945 {
 946    switch (opcode) {
 947    case BRW_OPCODE_MAC:
 948    case BRW_OPCODE_MACH:
 949    case BRW_OPCODE_SADA2:
 950       return true;
 951    default:
 952       return false;
 953    }
 954 }
 955
 956 bool
 957 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 958 {
 959    return writes_accumulator ||
 960           (devinfo->gen < 6 &&
 961            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 962             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 963              opcode != FS_OPCODE_CINTERP)));
 964 }
 965
 966 bool
 967 backend_instruction::has_side_effects() const
 968 {
 969    switch (opcode) {
 970    case SHADER_OPCODE_UNTYPED_ATOMIC:
 971    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 972    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 973    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 974    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 975    case SHADER_OPCODE_TYPED_ATOMIC:
 976    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 977    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 978    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 979    case SHADER_OPCODE_MEMORY_FENCE:
 980    case SHADER_OPCODE_URB_WRITE_SIMD8:
 981    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 982    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 983    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 984    case FS_OPCODE_FB_WRITE:
 985    case SHADER_OPCODE_BARRIER:
 986       return true;
 987    default:
 988       return false;
 989    }
 990 }
 991
 992 bool
 993 backend_instruction::is_volatile() const
 994 {
 995    switch (opcode) {
 996    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 997    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 998    case SHADER_OPCODE_TYPED_SURFACE_READ:
 999    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1000       return true;
1001    default:
1002       return false;
1003    }
1004 }
1005
1006 #ifndef NDEBUG
1007 static bool
1008 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1009 {
1010    bool found = false;
1011    foreach_inst_in_block (backend_instruction, i, block) {
1012       if (inst == i) {
1013          found = true;
1014       }
1015    }
1016    return found;
1017 }
1018 #endif
1019
1020 static void
1021 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1022 {
1023    for (bblock_t *block_iter = start_block->next();
1024         !block_iter->link.is_tail_sentinel();
1025         block_iter = block_iter->next()) {
1026       block_iter->start_ip += ip_adjustment;
1027       block_iter->end_ip += ip_adjustment;
1028    }
1029 }
1030
1031 void
1032 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1033 {
1034    if (!this->is_head_sentinel())
1035       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1036
1037    block->end_ip++;
1038
1039    adjust_later_block_ips(block, 1);
1040
1041    exec_node::insert_after(inst);
1042 }
1043
1044 void
1045 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1046 {
1047    if (!this->is_tail_sentinel())
1048       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1049
1050    block->end_ip++;
1051
1052    adjust_later_block_ips(block, 1);
1053
1054    exec_node::insert_before(inst);
1055 }
1056
1057 void
1058 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1059 {
1060    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1061
1062    unsigned num_inst = list->length();
1063
1064    block->end_ip += num_inst;
1065
1066    adjust_later_block_ips(block, num_inst);
1067
1068    exec_node::insert_before(list);
1069 }
1070
1071 void
1072 backend_instruction::remove(bblock_t *block)
1073 {
1074    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1075
1076    adjust_later_block_ips(block, -1);
1077
1078    if (block->start_ip == block->end_ip) {
1079       block->cfg->remove_block(block);
1080    } else {
1081       block->end_ip--;
1082    }
1083
1084    exec_node::remove();
1085 }
1086
1087 void
1088 backend_shader::dump_instructions()
1089 {
1090    dump_instructions(NULL);
1091 }
1092
1093 void
1094 backend_shader::dump_instructions(const char *name)
1095 {
1096    FILE *file = stderr;
1097    if (name && geteuid() != 0) {
1098       file = fopen(name, "w");
1099       if (!file)
1100          file = stderr;
1101    }
1102
1103    if (cfg) {
1104       int ip = 0;
1105       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1106          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1107             fprintf(file, "%4d: ", ip++);
1108          dump_instruction(inst, file);
1109       }
1110    } else {
1111       int ip = 0;
1112       foreach_in_list(backend_instruction, inst, &instructions) {
1113          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1114             fprintf(file, "%4d: ", ip++);
1115          dump_instruction(inst, file);
1116       }
1117    }
1118
1119    if (file != stderr) {
1120       fclose(file);
1121    }
1122 }
1123
1124 void
1125 backend_shader::calculate_cfg()
1126 {
1127    if (this->cfg)
1128       return;
1129    cfg = new(mem_ctx) cfg_t(&this->instructions);
1130 }
1131
1132 void
1133 backend_shader::invalidate_cfg()
1134 {
1135    ralloc_free(this->cfg);
1136    this->cfg = NULL;
1137 }
1138
1139 /**
1140  * Sets up the starting offsets for the groups of binding table entries
1141  * commong to all pipeline stages.
1142  *
1143  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1144  * unused but also make sure that addition of small offsets to them will
1145  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1146  */
1147 void
1148 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1149                                         const struct brw_device_info *devinfo,
1150                                         const struct gl_shader_program *shader_prog,
1151                                         const struct gl_program *prog,
1152                                         struct brw_stage_prog_data *stage_prog_data,
1153                                         uint32_t next_binding_table_offset)
1154 {
1155    const struct gl_shader *shader = NULL;
1156    int num_textures = _mesa_fls(prog->SamplersUsed);
1157
1158    if (shader_prog)
1159       shader = shader_prog->_LinkedShaders[stage];
1160
1161    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1162    next_binding_table_offset += num_textures;
1163
1164    if (shader) {
1165       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1166       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1167       next_binding_table_offset += shader->NumUniformBlocks;
1168
1169       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1170       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1171       next_binding_table_offset += shader->NumShaderStorageBlocks;
1172    } else {
1173       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1174       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1175    }
1176
1177    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1178       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1179       next_binding_table_offset++;
1180    } else {
1181       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1182    }
1183
1184    if (prog->UsesGather) {
1185       if (devinfo->gen >= 8) {
1186          stage_prog_data->binding_table.gather_texture_start =
1187             stage_prog_data->binding_table.texture_start;
1188       } else {
1189          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1190          next_binding_table_offset += num_textures;
1191       }
1192    } else {
1193       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1194    }
1195
1196    if (shader && shader->NumAtomicBuffers) {
1197       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1198       next_binding_table_offset += shader->NumAtomicBuffers;
1199    } else {
1200       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1201    }
1202
1203    if (shader && shader->NumImages) {
1204       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1205       next_binding_table_offset += shader->NumImages;
1206    } else {
1207       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1208    }
1209
1210    /* This may or may not be used depending on how the compile goes. */
1211    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1212    next_binding_table_offset++;
1213
1214    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1215
1216    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1217 }
1218
1219 static void
1220 setup_vec4_uniform_value(const gl_constant_value **params,
1221                          const gl_constant_value *values,
1222                          unsigned n)
1223 {
1224    static const gl_constant_value zero = { 0 };
1225
1226    for (unsigned i = 0; i < n; ++i)
1227       params[i] = &values[i];
1228
1229    for (unsigned i = n; i < 4; ++i)
1230       params[i] = &zero;
1231 }
1232
1233 void
1234 brw_setup_image_uniform_values(gl_shader_stage stage,
1235                                struct brw_stage_prog_data *stage_prog_data,
1236                                unsigned param_start_index,
1237                                const gl_uniform_storage *storage)
1238 {
1239    const gl_constant_value **param =
1240       &stage_prog_data->param[param_start_index];
1241
1242    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1243       const unsigned image_idx = storage->opaque[stage].index + i;
1244       const brw_image_param *image_param =
1245          &stage_prog_data->image_param[image_idx];
1246
1247       /* Upload the brw_image_param structure.  The order is expected to match
1248        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1249        */
1250       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1251          (const gl_constant_value *)&image_param->surface_idx, 1);
1252       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1253          (const gl_constant_value *)image_param->offset, 2);
1254       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1255          (const gl_constant_value *)image_param->size, 3);
1256       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1257          (const gl_constant_value *)image_param->stride, 4);
1258       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1259          (const gl_constant_value *)image_param->tiling, 3);
1260       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1261          (const gl_constant_value *)image_param->swizzling, 2);
1262       param += BRW_IMAGE_PARAM_SIZE;
1263
1264       brw_mark_surface_used(
1265          stage_prog_data,
1266          stage_prog_data->binding_table.image_start + image_idx);
1267    }
1268 }
1269
1270 /**
1271  * Decide which set of clip planes should be used when clipping via
1272  * gl_Position or gl_ClipVertex.
1273  */
1274 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1275 {
1276    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1277       /* There is currently a GLSL vertex shader, so clip according to GLSL
1278        * rules, which means compare gl_ClipVertex (or gl_Position, if
1279        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1280        * that were stored in EyeUserPlane at the time the clip planes were
1281        * specified.
1282        */
1283       return ctx->Transform.EyeUserPlane;
1284    } else {
1285       /* Either we are using fixed function or an ARB vertex program.  In
1286        * either case the clip planes are going to be compared against
1287        * gl_Position (which is in clip coordinates) so we have to clip using
1288        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1289        * core.
1290        */
1291       return ctx->Transform._ClipUserPlane;
1292    }
1293 }
1294