Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_shader.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #pragma once
25
26 #include <stdint.h>
27 #include "brw_reg.h"
28 #include "brw_defines.h"
29 #include "brw_context.h"
30
31 #ifdef __cplusplus
32 #include "brw_ir_allocator.h"
33 #endif
34
35 #define MAX_SAMPLER_MESSAGE_SIZE 11
36 #define MAX_VGRF_SIZE 16
37
38 #ifdef __cplusplus
39 struct backend_reg : private brw_reg
40 {
41 backend_reg() {}
42 backend_reg(const struct brw_reg &reg) : brw_reg(reg) {}
43
44 const brw_reg &as_brw_reg() const
45 {
46 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
47 assert(reg_offset == 0);
48 return static_cast<const brw_reg &>(*this);
49 }
50
51 brw_reg &as_brw_reg()
52 {
53 assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
54 assert(reg_offset == 0);
55 return static_cast<brw_reg &>(*this);
56 }
57
58 bool equals(const backend_reg &r) const;
59
60 bool is_zero() const;
61 bool is_one() const;
62 bool is_negative_one() const;
63 bool is_null() const;
64 bool is_accumulator() const;
65 bool in_range(const backend_reg &r, unsigned n) const;
66
67 /**
68 * Offset within the virtual register.
69 *
70 * In the scalar backend, this is in units of a float per pixel for pre-
71 * register allocation registers (i.e., one register in SIMD8 mode and two
72 * registers in SIMD16 mode).
73 *
74 * For uniforms, this is in units of 1 float.
75 */
76 uint16_t reg_offset;
77
78 using brw_reg::type;
79 using brw_reg::file;
80 using brw_reg::negate;
81 using brw_reg::abs;
82 using brw_reg::address_mode;
83 using brw_reg::subnr;
84 using brw_reg::nr;
85
86 using brw_reg::swizzle;
87 using brw_reg::writemask;
88 using brw_reg::indirect_offset;
89 using brw_reg::vstride;
90 using brw_reg::width;
91 using brw_reg::hstride;
92
93 using brw_reg::f;
94 using brw_reg::d;
95 using brw_reg::ud;
96 };
97 #endif
98
99 struct cfg_t;
100 struct bblock_t;
101
102 #ifdef __cplusplus
103 struct backend_instruction : public exec_node {
104 bool is_3src() const;
105 bool is_tex() const;
106 bool is_math() const;
107 bool is_control_flow() const;
108 bool is_commutative() const;
109 bool can_do_source_mods() const;
110 bool can_do_saturate() const;
111 bool can_do_cmod() const;
112 bool reads_accumulator_implicitly() const;
113 bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
114
115 void remove(bblock_t *block);
116 void insert_after(bblock_t *block, backend_instruction *inst);
117 void insert_before(bblock_t *block, backend_instruction *inst);
118 void insert_before(bblock_t *block, exec_list *list);
119
120 /**
121 * True if the instruction has side effects other than writing to
122 * its destination registers. You are expected not to reorder or
123 * optimize these out unless you know what you are doing.
124 */
125 bool has_side_effects() const;
126
127 /**
128 * True if the instruction might be affected by side effects of other
129 * instructions.
130 */
131 bool is_volatile() const;
132 #else
133 struct backend_instruction {
134 struct exec_node link;
135 #endif
136 /** @{
137 * Annotation for the generated IR. One of the two can be set.
138 */
139 const void *ir;
140 const char *annotation;
141 /** @} */
142
143 uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
144 uint8_t mlen; /**< SEND message length */
145 int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
146 uint8_t target; /**< MRT target. */
147 uint8_t regs_written; /**< Number of registers written by the instruction. */
148
149 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
150 enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
151 enum brw_predicate predicate;
152 bool predicate_inverse:1;
153 bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
154 bool force_writemask_all:1;
155 bool no_dd_clear:1;
156 bool no_dd_check:1;
157 bool saturate:1;
158 bool shadow_compare:1;
159
160 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
161 * mod and predication.
162 */
163 unsigned flag_subreg:1;
164
165 /** The number of hardware registers used for a message header. */
166 uint8_t header_size;
167 };
168
169 #ifdef __cplusplus
170
171 enum instruction_scheduler_mode {
172 SCHEDULE_PRE,
173 SCHEDULE_PRE_NON_LIFO,
174 SCHEDULE_PRE_LIFO,
175 SCHEDULE_POST,
176 };
177
178 struct backend_shader {
179 protected:
180
181 backend_shader(const struct brw_compiler *compiler,
182 void *log_data,
183 void *mem_ctx,
184 const nir_shader *shader,
185 struct brw_stage_prog_data *stage_prog_data);
186
187 public:
188
189 const struct brw_compiler *compiler;
190 void *log_data; /* Passed to compiler->*_log functions */
191
192 const struct brw_device_info * const devinfo;
193 const nir_shader *nir;
194 struct brw_stage_prog_data * const stage_prog_data;
195
196 /** ralloc context for temporary data used during compile */
197 void *mem_ctx;
198
199 /**
200 * List of either fs_inst or vec4_instruction (inheriting from
201 * backend_instruction)
202 */
203 exec_list instructions;
204
205 cfg_t *cfg;
206
207 gl_shader_stage stage;
208 bool debug_enabled;
209 const char *stage_name;
210 const char *stage_abbrev;
211
212 brw::simple_allocator alloc;
213
214 virtual void dump_instruction(backend_instruction *inst) = 0;
215 virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
216 virtual void dump_instructions();
217 virtual void dump_instructions(const char *name);
218
219 void calculate_cfg();
220 void invalidate_cfg();
221
222 virtual void invalidate_live_intervals() = 0;
223 };
224
225 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
226
227 void brw_setup_image_uniform_values(gl_shader_stage stage,
228 struct brw_stage_prog_data *stage_prog_data,
229 unsigned param_start_index,
230 const gl_uniform_storage *storage);
231
232 #else
233 struct backend_shader;
234 #endif /* __cplusplus */
235
236 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
237 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
238 uint32_t brw_math_function(enum opcode op);
239 const char *brw_instruction_name(enum opcode op);
240 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
241 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
242 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
243
244 bool opt_predicated_break(struct backend_shader *s);
245
246 #ifdef __cplusplus
247 extern "C" {
248 #endif
249
250 /**
251 * Scratch data used when compiling a GLSL geometry shader.
252 */
253 struct brw_gs_compile
254 {
255 struct brw_gs_prog_key key;
256 struct brw_vue_map input_vue_map;
257
258 unsigned control_data_bits_per_vertex;
259 unsigned control_data_header_size_bits;
260 };
261
262 void
263 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
264 const struct brw_device_info *devinfo,
265 const struct gl_shader_program *shader_prog,
266 const struct gl_program *prog,
267 struct brw_stage_prog_data *stage_prog_data,
268 uint32_t next_binding_table_offset);
269
270 bool brw_vs_precompile(struct gl_context *ctx,
271 struct gl_shader_program *shader_prog,
272 struct gl_program *prog);
273 bool brw_gs_precompile(struct gl_context *ctx,
274 struct gl_shader_program *shader_prog,
275 struct gl_program *prog);
276 bool brw_fs_precompile(struct gl_context *ctx,
277 struct gl_shader_program *shader_prog,
278 struct gl_program *prog);
279 bool brw_cs_precompile(struct gl_context *ctx,
280 struct gl_shader_program *shader_prog,
281 struct gl_program *prog);
282
283 GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog);
284 struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type);
285
286 int type_size_scalar(const struct glsl_type *type);
287 int type_size_vec4(const struct glsl_type *type);
288 int type_size_vec4_times_4(const struct glsl_type *type);
289
290 #ifdef __cplusplus
291 }
292 #endif