src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_ff_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_wm_push_constants, /* Before wm_state */
 132
 133    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 134     * table upload must be last.
 135     */
 136    &brw_vs_pull_constants,
 137    &brw_vs_ubo_surfaces,
 138    &brw_wm_pull_constants,
 139    &brw_wm_ubo_surfaces,
 140    &gen6_renderbuffer_surfaces,
 141    &brw_texture_surfaces,
 142    &gen6_sol_surface,
 143    &brw_vs_binding_table,
 144    &gen6_gs_binding_table,
 145    &brw_wm_binding_table,
 146
 147    &brw_fs_samplers,
 148    &brw_vs_samplers,
 149    &gen6_sampler_state,
 150    &gen6_multisample_state,
 151
 152    &gen6_vs_state,
 153    &gen6_gs_state,
 154    &gen6_clip_state,
 155    &gen6_sf_state,
 156    &gen6_wm_state,
 157
 158    &gen6_scissor_state,
 159
 160    &gen6_binding_table_pointers,
 161
 162    &brw_depthbuffer,
 163
 164    &brw_polygon_stipple,
 165    &brw_polygon_stipple_offset,
 166
 167    &brw_line_stipple,
 168    &brw_aa_line_parameters,
 169
 170    &brw_drawing_rect,
 171
 172    &brw_indices,
 173    &brw_index_buffer,
 174    &brw_vertices,
 175 };
 176
 177 static const struct brw_tracked_state *gen7_atoms[] =
 178 {
 179    &brw_vs_prog,
 180    &brw_gs_prog,
 181    &brw_wm_prog,
 182
 183    /* Command packets: */
 184
 185    /* must do before binding table pointers, cc state ptrs */
 186    &brw_state_base_address,
 187
 188    &brw_cc_vp,
 189    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 190    &gen7_sf_clip_viewport,
 191
 192    &gen7_push_constant_space,
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197
 198    &gen6_vs_push_constants, /* Before vs_state */
 199    &gen7_gs_push_constants, /* Before gs_state */
 200    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 201
 202    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 203     * table upload must be last.
 204     */
 205    &brw_vs_pull_constants,
 206    &brw_vs_ubo_surfaces,
 207    &brw_vs_abo_surfaces,
 208    &brw_gs_pull_constants,
 209    &brw_gs_ubo_surfaces,
 210    &brw_gs_abo_surfaces,
 211    &brw_wm_pull_constants,
 212    &brw_wm_ubo_surfaces,
 213    &brw_wm_abo_surfaces,
 214    &gen6_renderbuffer_surfaces,
 215    &brw_texture_surfaces,
 216    &brw_vs_binding_table,
 217    &brw_gs_binding_table,
 218    &brw_wm_binding_table,
 219
 220    &brw_fs_samplers,
 221    &brw_vs_samplers,
 222    &brw_gs_samplers,
 223    &gen6_multisample_state,
 224
 225    &gen7_disable_stages,
 226    &gen7_vs_state,
 227    &gen7_gs_state,
 228    &gen7_sol_state,
 229    &gen7_clip_state,
 230    &gen7_sbe_state,
 231    &gen7_sf_state,
 232    &gen7_wm_state,
 233    &gen7_ps_state,
 234
 235    &gen6_scissor_state,
 236
 237    &gen7_depthbuffer,
 238
 239    &brw_polygon_stipple,
 240    &brw_polygon_stipple_offset,
 241
 242    &brw_line_stipple,
 243    &brw_aa_line_parameters,
 244
 245    &brw_drawing_rect,
 246
 247    &brw_indices,
 248    &brw_index_buffer,
 249    &brw_vertices,
 250
 251    &haswell_cut_index,
 252 };
 253
 254 static void
 255 brw_upload_initial_gpu_state(struct brw_context *brw)
 256 {
 257    /* On platforms with hardware contexts, we can set our initial GPU state
 258     * right away rather than doing it via state atoms.  This saves a small
 259     * amount of overhead on every draw call.
 260     */
 261    if (!brw->hw_ctx)
 262       return;
 263
 264    brw_upload_invariant_state(brw);
 265 }
 266
 267 void brw_init_state( struct brw_context *brw )
 268 {
 269    struct gl_context *ctx = &brw->ctx;
 270    const struct brw_tracked_state **atoms;
 271    int num_atoms;
 272
 273    brw_init_caches(brw);
 274
 275    if (brw->gen >= 7) {
 276       atoms = gen7_atoms;
 277       num_atoms = ARRAY_SIZE(gen7_atoms);
 278    } else if (brw->gen == 6) {
 279       atoms = gen6_atoms;
 280       num_atoms = ARRAY_SIZE(gen6_atoms);
 281    } else {
 282       atoms = gen4_atoms;
 283       num_atoms = ARRAY_SIZE(gen4_atoms);
 284    }
 285
 286    brw->atoms = atoms;
 287    brw->num_atoms = num_atoms;
 288
 289    while (num_atoms--) {
 290       assert((*atoms)->dirty.mesa |
 291              (*atoms)->dirty.brw |
 292              (*atoms)->dirty.cache);
 293       assert((*atoms)->emit);
 294       atoms++;
 295    }
 296
 297    brw_upload_initial_gpu_state(brw);
 298
 299    brw->state.dirty.mesa = ~0;
 300    brw->state.dirty.brw = ~0;
 301
 302    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
 303     * dirty flags.
 304     */
 305    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->state.dirty.brw));
 306
 307    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 308    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 309    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 310    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 311 }
 312
 313
 314 void brw_destroy_state( struct brw_context *brw )
 315 {
 316    brw_destroy_caches(brw);
 317 }
 318
 319 /***********************************************************************
 320  */
 321
 322 static bool
 323 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 324 {
 325    return ((a->mesa & b->mesa) |
 326            (a->brw & b->brw) |
 327            (a->cache & b->cache)) != 0;
 328 }
 329
 330 static void accumulate_state( struct brw_state_flags *a,
 331                               const struct brw_state_flags *b )
 332 {
 333    a->mesa |= b->mesa;
 334    a->brw |= b->brw;
 335    a->cache |= b->cache;
 336 }
 337
 338
 339 static void xor_states( struct brw_state_flags *result,
 340                              const struct brw_state_flags *a,
 341                               const struct brw_state_flags *b )
 342 {
 343    result->mesa = a->mesa ^ b->mesa;
 344    result->brw = a->brw ^ b->brw;
 345    result->cache = a->cache ^ b->cache;
 346 }
 347
 348 struct dirty_bit_map {
 349    uint32_t bit;
 350    char *name;
 351    uint32_t count;
 352 };
 353
 354 #define DEFINE_BIT(name) {name, #name, 0}
 355
 356 static struct dirty_bit_map mesa_bits[] = {
 357    DEFINE_BIT(_NEW_MODELVIEW),
 358    DEFINE_BIT(_NEW_PROJECTION),
 359    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 360    DEFINE_BIT(_NEW_COLOR),
 361    DEFINE_BIT(_NEW_DEPTH),
 362    DEFINE_BIT(_NEW_EVAL),
 363    DEFINE_BIT(_NEW_FOG),
 364    DEFINE_BIT(_NEW_HINT),
 365    DEFINE_BIT(_NEW_LIGHT),
 366    DEFINE_BIT(_NEW_LINE),
 367    DEFINE_BIT(_NEW_PIXEL),
 368    DEFINE_BIT(_NEW_POINT),
 369    DEFINE_BIT(_NEW_POLYGON),
 370    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 371    DEFINE_BIT(_NEW_SCISSOR),
 372    DEFINE_BIT(_NEW_STENCIL),
 373    DEFINE_BIT(_NEW_TEXTURE),
 374    DEFINE_BIT(_NEW_TRANSFORM),
 375    DEFINE_BIT(_NEW_VIEWPORT),
 376    DEFINE_BIT(_NEW_ARRAY),
 377    DEFINE_BIT(_NEW_RENDERMODE),
 378    DEFINE_BIT(_NEW_BUFFERS),
 379    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 380    DEFINE_BIT(_NEW_MULTISAMPLE),
 381    DEFINE_BIT(_NEW_TRACK_MATRIX),
 382    DEFINE_BIT(_NEW_PROGRAM),
 383    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 384    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 385    DEFINE_BIT(_NEW_FRAG_CLAMP),
 386    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 387    {0, 0, 0}
 388 };
 389
 390 static struct dirty_bit_map brw_bits[] = {
 391    DEFINE_BIT(BRW_NEW_URB_FENCE),
 392    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 393    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 394    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 395    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 396    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 397    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 398    DEFINE_BIT(BRW_NEW_CONTEXT),
 399    DEFINE_BIT(BRW_NEW_PSP),
 400    DEFINE_BIT(BRW_NEW_SURFACES),
 401    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 402    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 403    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 404    DEFINE_BIT(BRW_NEW_INDICES),
 405    DEFINE_BIT(BRW_NEW_VERTICES),
 406    DEFINE_BIT(BRW_NEW_BATCH),
 407    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 408    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 409    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 410    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 411    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 412    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 413    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 414    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 415    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 416    DEFINE_BIT(BRW_NEW_STATS_WM),
 417    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 418    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 419    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 420    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 421    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 422    {0, 0, 0}
 423 };
 424
 425 static struct dirty_bit_map cache_bits[] = {
 426    DEFINE_BIT(CACHE_NEW_CC_VP),
 427    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 428    DEFINE_BIT(CACHE_NEW_WM_PROG),
 429    DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
 430    DEFINE_BIT(CACHE_NEW_BLORP_CONST_COLOR_PROG),
 431    DEFINE_BIT(CACHE_NEW_SAMPLER),
 432    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 433    DEFINE_BIT(CACHE_NEW_SF_PROG),
 434    DEFINE_BIT(CACHE_NEW_SF_VP),
 435    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 436    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 437    DEFINE_BIT(CACHE_NEW_VS_PROG),
 438    DEFINE_BIT(CACHE_NEW_FF_GS_UNIT),
 439    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 440    DEFINE_BIT(CACHE_NEW_GS_PROG),
 441    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 442    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 443    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 444    {0, 0, 0}
 445 };
 446
 447
 448 static void
 449 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 450 {
 451    int i;
 452
 453    for (i = 0; i < 32; i++) {
 454       if (bit_map[i].bit == 0)
 455          return;
 456
 457       if (bit_map[i].bit & bits)
 458          bit_map[i].count++;
 459    }
 460 }
 461
 462 static void
 463 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 464 {
 465    int i;
 466
 467    for (i = 0; i < 32; i++) {
 468       if (bit_map[i].bit == 0)
 469          return;
 470
 471       fprintf(stderr, "0x%08x: %12d (%s)\n",
 472               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 473    }
 474 }
 475
 476 /***********************************************************************
 477  * Emit all state:
 478  */
 479 void brw_upload_state(struct brw_context *brw)
 480 {
 481    struct gl_context *ctx = &brw->ctx;
 482    struct brw_state_flags *state = &brw->state.dirty;
 483    int i;
 484    static int dirty_count = 0;
 485
 486    state->mesa |= brw->NewGLState;
 487    brw->NewGLState = 0;
 488
 489    state->brw |= ctx->NewDriverState;
 490    ctx->NewDriverState = 0;
 491
 492    if (0) {
 493       /* Always re-emit all state. */
 494       state->mesa |= ~0;
 495       state->brw |= ~0;
 496       state->cache |= ~0;
 497    }
 498
 499    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 500       brw->fragment_program = ctx->FragmentProgram._Current;
 501       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 502    }
 503
 504    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 505       brw->geometry_program = ctx->GeometryProgram._Current;
 506       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 507    }
 508
 509    if (brw->vertex_program != ctx->VertexProgram._Current) {
 510       brw->vertex_program = ctx->VertexProgram._Current;
 511       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 512    }
 513
 514    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 515       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 516       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 517    }
 518
 519    if ((state->mesa | state->cache | state->brw) == 0)
 520       return;
 521
 522    intel_check_front_buffer_rendering(brw);
 523
 524    if (unlikely(INTEL_DEBUG)) {
 525       /* Debug version which enforces various sanity checks on the
 526        * state flags which are generated and checked to help ensure
 527        * state atoms are ordered correctly in the list.
 528        */
 529       struct brw_state_flags examined, prev;
 530       memset(&examined, 0, sizeof(examined));
 531       prev = *state;
 532
 533       for (i = 0; i < brw->num_atoms; i++) {
 534          const struct brw_tracked_state *atom = brw->atoms[i];
 535          struct brw_state_flags generated;
 536
 537          if (check_state(state, &atom->dirty)) {
 538             atom->emit(brw);
 539          }
 540
 541          accumulate_state(&examined, &atom->dirty);
 542
 543          /* generated = (prev ^ state)
 544           * if (examined & generated)
 545           *     fail;
 546           */
 547          xor_states(&generated, &prev, state);
 548          assert(!check_state(&examined, &generated));
 549          prev = *state;
 550       }
 551    }
 552    else {
 553       for (i = 0; i < brw->num_atoms; i++) {
 554          const struct brw_tracked_state *atom = brw->atoms[i];
 555
 556          if (check_state(state, &atom->dirty)) {
 557             atom->emit(brw);
 558          }
 559       }
 560    }
 561
 562    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 563       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 564       STATIC_ASSERT(ARRAY_SIZE(cache_bits) == BRW_MAX_CACHE + 1);
 565
 566       brw_update_dirty_count(mesa_bits, state->mesa);
 567       brw_update_dirty_count(brw_bits, state->brw);
 568       brw_update_dirty_count(cache_bits, state->cache);
 569       if (dirty_count++ % 1000 == 0) {
 570          brw_print_dirty_count(mesa_bits);
 571          brw_print_dirty_count(brw_bits);
 572          brw_print_dirty_count(cache_bits);
 573          fprintf(stderr, "\n");
 574       }
 575    }
 576 }
 577
 578
 579 /**
 580  * Clear dirty bits to account for the fact that the state emitted by
 581  * brw_upload_state() has been committed to the hardware.  This is a separate
 582  * call from brw_upload_state() because it's possible that after the call to
 583  * brw_upload_state(), we will discover that we've run out of aperture space,
 584  * and need to rewind the batch buffer to the state it had before the
 585  * brw_upload_state() call.
 586  */
 587 void
 588 brw_clear_dirty_bits(struct brw_context *brw)
 589 {
 590    struct brw_state_flags *state = &brw->state.dirty;
 591    memset(state, 0, sizeof(*state));
 592 }