src/mesa/drivers/dri/i965/brw_structs.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_STRUCTS_H
  34 #define BRW_STRUCTS_H
  35
  36
  37 /** Number of general purpose registers (VS, WM, etc) */
  38 #define BRW_MAX_GRF 128
  39
  40 /** Number of message register file registers */
  41 #define BRW_MAX_MRF 16
  42
  43 /* These seem to be passed around as function args, so it works out
  44  * better to keep them as #defines:
  45  */
  46 #define BRW_FLUSH_READ_CACHE           0x1
  47 #define BRW_FLUSH_STATE_CACHE          0x2
  48 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
  49 #define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
  50
  51 struct brw_urb_fence
  52 {
  53    struct
  54    {
  55       GLuint length:8;
  56       GLuint vs_realloc:1;
  57       GLuint gs_realloc:1;
  58       GLuint clp_realloc:1;
  59       GLuint sf_realloc:1;
  60       GLuint vfe_realloc:1;
  61       GLuint cs_realloc:1;
  62       GLuint pad:2;
  63       GLuint opcode:16;
  64    } header;
  65
  66    struct
  67    {
  68       GLuint vs_fence:10;
  69       GLuint gs_fence:10;
  70       GLuint clp_fence:10;
  71       GLuint pad:2;
  72    } bits0;
  73
  74    struct
  75    {
  76       GLuint sf_fence:10;
  77       GLuint vf_fence:10;
  78       GLuint cs_fence:11;
  79       GLuint pad:1;
  80    } bits1;
  81 };
  82
  83 /* State structs for the various fixed function units:
  84  */
  85
  86
  87 struct thread0
  88 {
  89    GLuint pad0:1;
  90    GLuint grf_reg_count:3;
  91    GLuint pad1:2;
  92    GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */
  93 };
  94
  95 struct thread1
  96 {
  97    GLuint ext_halt_exception_enable:1;
  98    GLuint sw_exception_enable:1;
  99    GLuint mask_stack_exception_enable:1;
 100    GLuint timeout_exception_enable:1;
 101    GLuint illegal_op_exception_enable:1;
 102    GLuint pad0:3;
 103    GLuint depth_coef_urb_read_offset:6; /* WM only */
 104    GLuint pad1:2;
 105    GLuint floating_point_mode:1;
 106    GLuint thread_priority:1;
 107    GLuint binding_table_entry_count:8;
 108    GLuint pad3:5;
 109    GLuint single_program_flow:1;
 110 };
 111
 112 struct thread2
 113 {
 114    GLuint per_thread_scratch_space:4;
 115    GLuint pad0:6;
 116    GLuint scratch_space_base_pointer:22;
 117 };
 118
 119
 120 struct thread3
 121 {
 122    GLuint dispatch_grf_start_reg:4;
 123    GLuint urb_entry_read_offset:6;
 124    GLuint pad0:1;
 125    GLuint urb_entry_read_length:6;
 126    GLuint pad1:1;
 127    GLuint const_urb_entry_read_offset:6;
 128    GLuint pad2:1;
 129    GLuint const_urb_entry_read_length:6;
 130    GLuint pad3:1;
 131 };
 132
 133
 134
 135 struct brw_clip_unit_state
 136 {
 137    struct thread0 thread0;
 138    struct
 139    {
 140       GLuint pad0:7;
 141       GLuint sw_exception_enable:1;
 142       GLuint pad1:3;
 143       GLuint mask_stack_exception_enable:1;
 144       GLuint pad2:1;
 145       GLuint illegal_op_exception_enable:1;
 146       GLuint pad3:2;
 147       GLuint floating_point_mode:1;
 148       GLuint thread_priority:1;
 149       GLuint binding_table_entry_count:8;
 150       GLuint pad4:5;
 151       GLuint single_program_flow:1;
 152    } thread1;
 153
 154    struct thread2 thread2;
 155    struct thread3 thread3;
 156
 157    struct
 158    {
 159       GLuint pad0:9;
 160       GLuint gs_output_stats:1; /* not always */
 161       GLuint stats_enable:1;
 162       GLuint nr_urb_entries:7;
 163       GLuint pad1:1;
 164       GLuint urb_entry_allocation_size:5;
 165       GLuint pad2:1;
 166       GLuint max_threads:5;     /* may be less */
 167       GLuint pad3:2;
 168    } thread4;
 169
 170    struct
 171    {
 172       GLuint pad0:13;
 173       GLuint clip_mode:3;
 174       GLuint userclip_enable_flags:8;
 175       GLuint userclip_must_clip:1;
 176       GLuint negative_w_clip_test:1;
 177       GLuint guard_band_enable:1;
 178       GLuint viewport_z_clip_enable:1;
 179       GLuint viewport_xy_clip_enable:1;
 180       GLuint vertex_position_space:1;
 181       GLuint api_mode:1;
 182       GLuint pad2:1;
 183    } clip5;
 184
 185    struct
 186    {
 187       GLuint pad0:5;
 188       GLuint clipper_viewport_state_ptr:27;
 189    } clip6;
 190
 191
 192    GLfloat viewport_xmin;
 193    GLfloat viewport_xmax;
 194    GLfloat viewport_ymin;
 195    GLfloat viewport_ymax;
 196 };
 197
 198 struct gen6_blend_state
 199 {
 200    struct {
 201       GLuint dest_blend_factor:5;
 202       GLuint source_blend_factor:5;
 203       GLuint pad3:1;
 204       GLuint blend_func:3;
 205       GLuint pad2:1;
 206       GLuint ia_dest_blend_factor:5;
 207       GLuint ia_source_blend_factor:5;
 208       GLuint pad1:1;
 209       GLuint ia_blend_func:3;
 210       GLuint pad0:1;
 211       GLuint ia_blend_enable:1;
 212       GLuint blend_enable:1;
 213    } blend0;
 214
 215    struct {
 216       GLuint post_blend_clamp_enable:1;
 217       GLuint pre_blend_clamp_enable:1;
 218       GLuint clamp_range:2;
 219       GLuint pad0:4;
 220       GLuint x_dither_offset:2;
 221       GLuint y_dither_offset:2;
 222       GLuint dither_enable:1;
 223       GLuint alpha_test_func:3;
 224       GLuint alpha_test_enable:1;
 225       GLuint pad1:1;
 226       GLuint logic_op_func:4;
 227       GLuint logic_op_enable:1;
 228       GLuint pad2:1;
 229       GLuint write_disable_b:1;
 230       GLuint write_disable_g:1;
 231       GLuint write_disable_r:1;
 232       GLuint write_disable_a:1;
 233       GLuint pad3:1;
 234       GLuint alpha_to_coverage_dither:1;
 235       GLuint alpha_to_one:1;
 236       GLuint alpha_to_coverage:1;
 237    } blend1;
 238 };
 239
 240 struct gen6_color_calc_state
 241 {
 242    struct {
 243       GLuint alpha_test_format:1;
 244       GLuint pad0:14;
 245       GLuint round_disable:1;
 246       GLuint bf_stencil_ref:8;
 247       GLuint stencil_ref:8;
 248    } cc0;
 249
 250    union {
 251       GLfloat alpha_ref_f;
 252       struct {
 253          GLuint ui:8;
 254          GLuint pad0:24;
 255       } alpha_ref_fi;
 256    } cc1;
 257
 258    GLfloat constant_r;
 259    GLfloat constant_g;
 260    GLfloat constant_b;
 261    GLfloat constant_a;
 262 };
 263
 264 struct gen6_depth_stencil_state
 265 {
 266    struct {
 267       GLuint pad0:3;
 268       GLuint bf_stencil_pass_depth_pass_op:3;
 269       GLuint bf_stencil_pass_depth_fail_op:3;
 270       GLuint bf_stencil_fail_op:3;
 271       GLuint bf_stencil_func:3;
 272       GLuint bf_stencil_enable:1;
 273       GLuint pad1:2;
 274       GLuint stencil_write_enable:1;
 275       GLuint stencil_pass_depth_pass_op:3;
 276       GLuint stencil_pass_depth_fail_op:3;
 277       GLuint stencil_fail_op:3;
 278       GLuint stencil_func:3;
 279       GLuint stencil_enable:1;
 280    } ds0;
 281
 282    struct {
 283       GLuint bf_stencil_write_mask:8;
 284       GLuint bf_stencil_test_mask:8;
 285       GLuint stencil_write_mask:8;
 286       GLuint stencil_test_mask:8;
 287    } ds1;
 288
 289    struct {
 290       GLuint pad0:26;
 291       GLuint depth_write_enable:1;
 292       GLuint depth_test_func:3;
 293       GLuint pad1:1;
 294       GLuint depth_test_enable:1;
 295    } ds2;
 296 };
 297
 298 struct brw_cc_unit_state
 299 {
 300    struct
 301    {
 302       GLuint pad0:3;
 303       GLuint bf_stencil_pass_depth_pass_op:3;
 304       GLuint bf_stencil_pass_depth_fail_op:3;
 305       GLuint bf_stencil_fail_op:3;
 306       GLuint bf_stencil_func:3;
 307       GLuint bf_stencil_enable:1;
 308       GLuint pad1:2;
 309       GLuint stencil_write_enable:1;
 310       GLuint stencil_pass_depth_pass_op:3;
 311       GLuint stencil_pass_depth_fail_op:3;
 312       GLuint stencil_fail_op:3;
 313       GLuint stencil_func:3;
 314       GLuint stencil_enable:1;
 315    } cc0;
 316
 317
 318    struct
 319    {
 320       GLuint bf_stencil_ref:8;
 321       GLuint stencil_write_mask:8;
 322       GLuint stencil_test_mask:8;
 323       GLuint stencil_ref:8;
 324    } cc1;
 325
 326
 327    struct
 328    {
 329       GLuint logicop_enable:1;
 330       GLuint pad0:10;
 331       GLuint depth_write_enable:1;
 332       GLuint depth_test_function:3;
 333       GLuint depth_test:1;
 334       GLuint bf_stencil_write_mask:8;
 335       GLuint bf_stencil_test_mask:8;
 336    } cc2;
 337
 338
 339    struct
 340    {
 341       GLuint pad0:8;
 342       GLuint alpha_test_func:3;
 343       GLuint alpha_test:1;
 344       GLuint blend_enable:1;
 345       GLuint ia_blend_enable:1;
 346       GLuint pad1:1;
 347       GLuint alpha_test_format:1;
 348       GLuint pad2:16;
 349    } cc3;
 350
 351    struct
 352    {
 353       GLuint pad0:5;
 354       GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 355    } cc4;
 356
 357    struct
 358    {
 359       GLuint pad0:2;
 360       GLuint ia_dest_blend_factor:5;
 361       GLuint ia_src_blend_factor:5;
 362       GLuint ia_blend_function:3;
 363       GLuint statistics_enable:1;
 364       GLuint logicop_func:4;
 365       GLuint pad1:11;
 366       GLuint dither_enable:1;
 367    } cc5;
 368
 369    struct
 370    {
 371       GLuint clamp_post_alpha_blend:1;
 372       GLuint clamp_pre_alpha_blend:1;
 373       GLuint clamp_range:2;
 374       GLuint pad0:11;
 375       GLuint y_dither_offset:2;
 376       GLuint x_dither_offset:2;
 377       GLuint dest_blend_factor:5;
 378       GLuint src_blend_factor:5;
 379       GLuint blend_function:3;
 380    } cc6;
 381
 382    struct {
 383       union {
 384          GLfloat f;
 385          GLubyte ub[4];
 386       } alpha_ref;
 387    } cc7;
 388 };
 389
 390 struct brw_sf_unit_state
 391 {
 392    struct thread0 thread0;
 393    struct thread1 thread1;
 394    struct thread2 thread2;
 395    struct thread3 thread3;
 396
 397    struct
 398    {
 399       GLuint pad0:10;
 400       GLuint stats_enable:1;
 401       GLuint nr_urb_entries:7;
 402       GLuint pad1:1;
 403       GLuint urb_entry_allocation_size:5;
 404       GLuint pad2:1;
 405       GLuint max_threads:6;
 406       GLuint pad3:1;
 407    } thread4;
 408
 409    struct
 410    {
 411       GLuint front_winding:1;
 412       GLuint viewport_transform:1;
 413       GLuint pad0:3;
 414       GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
 415    } sf5;
 416
 417    struct
 418    {
 419       GLuint pad0:9;
 420       GLuint dest_org_vbias:4;
 421       GLuint dest_org_hbias:4;
 422       GLuint scissor:1;
 423       GLuint disable_2x2_trifilter:1;
 424       GLuint disable_zero_pix_trifilter:1;
 425       GLuint point_rast_rule:2;
 426       GLuint line_endcap_aa_region_width:2;
 427       GLuint line_width:4;
 428       GLuint fast_scissor_disable:1;
 429       GLuint cull_mode:2;
 430       GLuint aa_enable:1;
 431    } sf6;
 432
 433    struct
 434    {
 435       GLuint point_size:11;
 436       GLuint use_point_size_state:1;
 437       GLuint subpixel_precision:1;
 438       GLuint sprite_point:1;
 439       GLuint pad0:10;
 440       GLuint aa_line_distance_mode:1;
 441       GLuint trifan_pv:2;
 442       GLuint linestrip_pv:2;
 443       GLuint tristrip_pv:2;
 444       GLuint line_last_pixel_enable:1;
 445    } sf7;
 446
 447 };
 448
 449 struct gen6_scissor_rect
 450 {
 451    GLuint xmin:16;
 452    GLuint ymin:16;
 453    GLuint xmax:16;
 454    GLuint ymax:16;
 455 };
 456
 457 struct brw_gs_unit_state
 458 {
 459    struct thread0 thread0;
 460    struct thread1 thread1;
 461    struct thread2 thread2;
 462    struct thread3 thread3;
 463
 464    struct
 465    {
 466       GLuint pad0:8;
 467       GLuint rendering_enable:1; /* for Ironlake */
 468       GLuint pad4:1;
 469       GLuint stats_enable:1;
 470       GLuint nr_urb_entries:7;
 471       GLuint pad1:1;
 472       GLuint urb_entry_allocation_size:5;
 473       GLuint pad2:1;
 474       GLuint max_threads:5;
 475       GLuint pad3:2;
 476    } thread4;
 477
 478    struct
 479    {
 480       GLuint sampler_count:3;
 481       GLuint pad0:2;
 482       GLuint sampler_state_pointer:27;
 483    } gs5;
 484
 485
 486    struct
 487    {
 488       GLuint max_vp_index:4;
 489       GLuint pad0:12;
 490       GLuint svbi_post_inc_value:10;
 491       GLuint pad1:1;
 492       GLuint svbi_post_inc_enable:1;
 493       GLuint svbi_payload:1;
 494       GLuint discard_adjaceny:1;
 495       GLuint reorder_enable:1;
 496       GLuint pad2:1;
 497    } gs6;
 498 };
 499
 500
 501 struct brw_vs_unit_state
 502 {
 503    struct thread0 thread0;
 504    struct thread1 thread1;
 505    struct thread2 thread2;
 506    struct thread3 thread3;
 507
 508    struct
 509    {
 510       GLuint pad0:10;
 511       GLuint stats_enable:1;
 512       GLuint nr_urb_entries:7;
 513       GLuint pad1:1;
 514       GLuint urb_entry_allocation_size:5;
 515       GLuint pad2:1;
 516       GLuint max_threads:6;
 517       GLuint pad3:1;
 518    } thread4;
 519
 520    struct
 521    {
 522       GLuint sampler_count:3;
 523       GLuint pad0:2;
 524       GLuint sampler_state_pointer:27;
 525    } vs5;
 526
 527    struct
 528    {
 529       GLuint vs_enable:1;
 530       GLuint vert_cache_disable:1;
 531       GLuint pad0:30;
 532    } vs6;
 533 };
 534
 535
 536 struct brw_wm_unit_state
 537 {
 538    struct thread0 thread0;
 539    struct thread1 thread1;
 540    struct thread2 thread2;
 541    struct thread3 thread3;
 542
 543    struct {
 544       GLuint stats_enable:1;
 545       GLuint depth_buffer_clear:1;
 546       GLuint sampler_count:3;
 547       GLuint sampler_state_pointer:27;
 548    } wm4;
 549
 550    struct
 551    {
 552       GLuint enable_8_pix:1;
 553       GLuint enable_16_pix:1;
 554       GLuint enable_32_pix:1;
 555       GLuint enable_con_32_pix:1;
 556       GLuint enable_con_64_pix:1;
 557       GLuint pad0:1;
 558
 559       /* These next four bits are for Ironlake+ */
 560       GLuint fast_span_coverage_enable:1;
 561       GLuint depth_buffer_clear:1;
 562       GLuint depth_buffer_resolve_enable:1;
 563       GLuint hierarchical_depth_buffer_resolve_enable:1;
 564
 565       GLuint legacy_global_depth_bias:1;
 566       GLuint line_stipple:1;
 567       GLuint depth_offset:1;
 568       GLuint polygon_stipple:1;
 569       GLuint line_aa_region_width:2;
 570       GLuint line_endcap_aa_region_width:2;
 571       GLuint early_depth_test:1;
 572       GLuint thread_dispatch_enable:1;
 573       GLuint program_uses_depth:1;
 574       GLuint program_computes_depth:1;
 575       GLuint program_uses_killpixel:1;
 576       GLuint legacy_line_rast: 1;
 577       GLuint transposed_urb_read_enable:1;
 578       GLuint max_threads:7;
 579    } wm5;
 580
 581    GLfloat global_depth_offset_constant;
 582    GLfloat global_depth_offset_scale;
 583
 584    /* for Ironlake only */
 585    struct {
 586       GLuint pad0:1;
 587       GLuint grf_reg_count_1:3;
 588       GLuint pad1:2;
 589       GLuint kernel_start_pointer_1:26;
 590    } wm8;
 591
 592    struct {
 593       GLuint pad0:1;
 594       GLuint grf_reg_count_2:3;
 595       GLuint pad1:2;
 596       GLuint kernel_start_pointer_2:26;
 597    } wm9;
 598
 599    struct {
 600       GLuint pad0:1;
 601       GLuint grf_reg_count_3:3;
 602       GLuint pad1:2;
 603       GLuint kernel_start_pointer_3:26;
 604    } wm10;
 605 };
 606
 607 struct brw_sampler_default_color {
 608    GLfloat color[4];
 609 };
 610
 611 struct gen5_sampler_default_color {
 612    uint8_t ub[4];
 613    float f[4];
 614    uint16_t hf[4];
 615    uint16_t us[4];
 616    int16_t s[4];
 617    uint8_t b[4];
 618 };
 619
 620 struct brw_sampler_state
 621 {
 622
 623    struct
 624    {
 625       GLuint shadow_function:3;
 626       GLuint lod_bias:11;
 627       GLuint min_filter:3;
 628       GLuint mag_filter:3;
 629       GLuint mip_filter:2;
 630       GLuint base_level:5;
 631       GLuint min_mag_neq:1;
 632       GLuint lod_preclamp:1;
 633       GLuint default_color_mode:1;
 634       GLuint pad0:1;
 635       GLuint disable:1;
 636    } ss0;
 637
 638    struct
 639    {
 640       GLuint r_wrap_mode:3;
 641       GLuint t_wrap_mode:3;
 642       GLuint s_wrap_mode:3;
 643       GLuint cube_control_mode:1;
 644       GLuint pad:2;
 645       GLuint max_lod:10;
 646       GLuint min_lod:10;
 647    } ss1;
 648
 649
 650    struct
 651    {
 652       GLuint pad:5;
 653       GLuint default_color_pointer:27;
 654    } ss2;
 655
 656    struct
 657    {
 658       GLuint non_normalized_coord:1;
 659       GLuint pad:12;
 660       GLuint address_round:6;
 661       GLuint max_aniso:3;
 662       GLuint chroma_key_mode:1;
 663       GLuint chroma_key_index:2;
 664       GLuint chroma_key_enable:1;
 665       GLuint monochrome_filter_width:3;
 666       GLuint monochrome_filter_height:3;
 667    } ss3;
 668 };
 669
 670 struct gen7_sampler_state
 671 {
 672    struct
 673    {
 674       GLuint aniso_algorithm:1;
 675       GLuint lod_bias:13;
 676       GLuint min_filter:3;
 677       GLuint mag_filter:3;
 678       GLuint mip_filter:2;
 679       GLuint base_level:5;
 680       GLuint pad1:1;
 681       GLuint lod_preclamp:1;
 682       GLuint default_color_mode:1;
 683       GLuint pad0:1;
 684       GLuint disable:1;
 685    } ss0;
 686
 687    struct
 688    {
 689       GLuint cube_control_mode:1;
 690       GLuint shadow_function:3;
 691       GLuint pad:4;
 692       GLuint max_lod:12;
 693       GLuint min_lod:12;
 694    } ss1;
 695
 696    struct
 697    {
 698       GLuint pad:5;
 699       GLuint default_color_pointer:27;
 700    } ss2;
 701
 702    struct
 703    {
 704       GLuint r_wrap_mode:3;
 705       GLuint t_wrap_mode:3;
 706       GLuint s_wrap_mode:3;
 707       GLuint pad:1;
 708       GLuint non_normalized_coord:1;
 709       GLuint trilinear_quality:2;
 710       GLuint address_round:6;
 711       GLuint max_aniso:3;
 712       GLuint chroma_key_mode:1;
 713       GLuint chroma_key_index:2;
 714       GLuint chroma_key_enable:1;
 715       GLuint pad0:6;
 716    } ss3;
 717 };
 718
 719 struct brw_clipper_viewport
 720 {
 721    GLfloat xmin;
 722    GLfloat xmax;
 723    GLfloat ymin;
 724    GLfloat ymax;
 725 };
 726
 727 struct brw_cc_viewport
 728 {
 729    GLfloat min_depth;
 730    GLfloat max_depth;
 731 };
 732
 733 struct brw_sf_viewport
 734 {
 735    struct {
 736       GLfloat m00;
 737       GLfloat m11;
 738       GLfloat m22;
 739       GLfloat m30;
 740       GLfloat m31;
 741       GLfloat m32;
 742    } viewport;
 743
 744    /* scissor coordinates are inclusive */
 745    struct {
 746       GLshort xmin;
 747       GLshort ymin;
 748       GLshort xmax;
 749       GLshort ymax;
 750    } scissor;
 751 };
 752
 753 struct gen6_sf_viewport {
 754    GLfloat m00;
 755    GLfloat m11;
 756    GLfloat m22;
 757    GLfloat m30;
 758    GLfloat m31;
 759    GLfloat m32;
 760 };
 761
 762 struct gen7_sf_clip_viewport {
 763    struct {
 764       GLfloat m00;
 765       GLfloat m11;
 766       GLfloat m22;
 767       GLfloat m30;
 768       GLfloat m31;
 769       GLfloat m32;
 770    } viewport;
 771
 772    GLuint pad0[2];
 773
 774    struct {
 775       GLfloat xmin;
 776       GLfloat xmax;
 777       GLfloat ymin;
 778       GLfloat ymax;
 779    } guardband;
 780
 781    GLfloat pad1[4];
 782 };
 783
 784 /* volume 5c Shared Functions - 1.13.4.1.2 */
 785 struct gen7_surface_state
 786 {
 787    struct {
 788       GLuint cube_pos_z:1;
 789       GLuint cube_neg_z:1;
 790       GLuint cube_pos_y:1;
 791       GLuint cube_neg_y:1;
 792       GLuint cube_pos_x:1;
 793       GLuint cube_neg_x:1;
 794       GLuint pad2:2;
 795       GLuint render_cache_read_write:1;
 796       GLuint pad1:1;
 797       GLuint surface_array_spacing:1;
 798       GLuint vert_line_stride_ofs:1;
 799       GLuint vert_line_stride:1;
 800       GLuint tile_walk:1;
 801       GLuint tiled_surface:1;
 802       GLuint horizontal_alignment:1;
 803       GLuint vertical_alignment:2;
 804       GLuint surface_format:9;     /**< BRW_SURFACEFORMAT_x */
 805       GLuint pad0:1;
 806       GLuint is_array:1;
 807       GLuint surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
 808    } ss0;
 809
 810    struct {
 811       GLuint base_addr;
 812    } ss1;
 813
 814    struct {
 815       GLuint width:14;
 816       GLuint pad1:2;
 817       GLuint height:14;
 818       GLuint pad0:2;
 819    } ss2;
 820
 821    struct {
 822       GLuint pitch:18;
 823       GLuint pad:3;
 824       GLuint depth:11;
 825    } ss3;
 826
 827    struct {
 828       GLuint multisample_position_palette_index:3;
 829       GLuint num_multisamples:3;
 830       GLuint multisampled_surface_storage_format:1;
 831       GLuint render_target_view_extent:11;
 832       GLuint min_array_elt:11;
 833       GLuint rotation:2;
 834       GLuint pad0:1;
 835    } ss4;
 836
 837    struct {
 838       GLuint mip_count:4;
 839       GLuint min_lod:4;
 840       GLuint pad1:12;
 841       GLuint y_offset:4;
 842       GLuint pad0:1;
 843       GLuint x_offset:7;
 844    } ss5;
 845
 846    struct {
 847       GLuint pad; /* Multisample Control Surface stuff */
 848    } ss6;
 849
 850    struct {
 851       GLuint resource_min_lod:12;
 852       GLuint pad0:16;
 853       GLuint alpha_clear_color:1;
 854       GLuint blue_clear_color:1;
 855       GLuint green_clear_color:1;
 856       GLuint red_clear_color:1;
 857    } ss7;
 858 };
 859
 860
 861 struct brw_vertex_element_state
 862 {
 863    struct
 864    {
 865       GLuint src_offset:11;
 866       GLuint pad:5;
 867       GLuint src_format:9;
 868       GLuint pad0:1;
 869       GLuint valid:1;
 870       GLuint vertex_buffer_index:5;
 871    } ve0;
 872
 873    struct
 874    {
 875       GLuint dst_offset:8;
 876       GLuint pad:8;
 877       GLuint vfcomponent3:4;
 878       GLuint vfcomponent2:4;
 879       GLuint vfcomponent1:4;
 880       GLuint vfcomponent0:4;
 881    } ve1;
 882 };
 883
 884 #define BRW_VEP_MAX 18
 885
 886 struct brw_urb_immediate {
 887    GLuint opcode:4;
 888    GLuint offset:6;
 889    GLuint swizzle_control:2;
 890    GLuint pad:1;
 891    GLuint allocate:1;
 892    GLuint used:1;
 893    GLuint complete:1;
 894    GLuint response_length:4;
 895    GLuint msg_length:4;
 896    GLuint msg_target:4;
 897    GLuint pad1:3;
 898    GLuint end_of_thread:1;
 899 };
 900
 901 /* Instruction format for the execution units:
 902  */
 903
 904 struct brw_instruction
 905 {
 906    struct
 907    {
 908       GLuint opcode:7;
 909       GLuint pad:1;
 910       GLuint access_mode:1;
 911       GLuint mask_control:1;
 912       GLuint dependency_control:2;
 913       GLuint compression_control:2; /* gen6: quater control */
 914       GLuint thread_control:2;
 915       GLuint predicate_control:4;
 916       GLuint predicate_inverse:1;
 917       GLuint execution_size:3;
 918       GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
 919       GLuint acc_wr_control:1;
 920       GLuint cmpt_control:1;
 921       GLuint debug_control:1;
 922       GLuint saturate:1;
 923    } header;
 924
 925    union {
 926       struct
 927       {
 928          GLuint dest_reg_file:2;
 929          GLuint dest_reg_type:3;
 930          GLuint src0_reg_file:2;
 931          GLuint src0_reg_type:3;
 932          GLuint src1_reg_file:2;
 933          GLuint src1_reg_type:3;
 934          GLuint pad:1;
 935          GLuint dest_subreg_nr:5;
 936          GLuint dest_reg_nr:8;
 937          GLuint dest_horiz_stride:2;
 938          GLuint dest_address_mode:1;
 939       } da1;
 940
 941       struct
 942       {
 943          GLuint dest_reg_file:2;
 944          GLuint dest_reg_type:3;
 945          GLuint src0_reg_file:2;
 946          GLuint src0_reg_type:3;
 947          GLuint src1_reg_file:2;        /* 0x00000c00 */
 948          GLuint src1_reg_type:3;        /* 0x00007000 */
 949          GLuint pad:1;
 950          GLint dest_indirect_offset:10; /* offset against the deref'd address reg */
 951          GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
 952          GLuint dest_horiz_stride:2;
 953          GLuint dest_address_mode:1;
 954       } ia1;
 955
 956       struct
 957       {
 958          GLuint dest_reg_file:2;
 959          GLuint dest_reg_type:3;
 960          GLuint src0_reg_file:2;
 961          GLuint src0_reg_type:3;
 962          GLuint src1_reg_file:2;
 963          GLuint src1_reg_type:3;
 964          GLuint pad:1;
 965          GLuint dest_writemask:4;
 966          GLuint dest_subreg_nr:1;
 967          GLuint dest_reg_nr:8;
 968          GLuint dest_horiz_stride:2;
 969          GLuint dest_address_mode:1;
 970       } da16;
 971
 972       struct
 973       {
 974          GLuint dest_reg_file:2;
 975          GLuint dest_reg_type:3;
 976          GLuint src0_reg_file:2;
 977          GLuint src0_reg_type:3;
 978          GLuint pad0:6;
 979          GLuint dest_writemask:4;
 980          GLint dest_indirect_offset:6;
 981          GLuint dest_subreg_nr:3;
 982          GLuint dest_horiz_stride:2;
 983          GLuint dest_address_mode:1;
 984       } ia16;
 985
 986       struct {
 987          GLuint dest_reg_file:2;
 988          GLuint dest_reg_type:3;
 989          GLuint src0_reg_file:2;
 990          GLuint src0_reg_type:3;
 991          GLuint src1_reg_file:2;
 992          GLuint src1_reg_type:3;
 993          GLuint pad:1;
 994
 995          GLint jump_count:16;
 996       } branch_gen6;
 997    } bits1;
 998
 999
1000    union {
1001       struct
1002       {
1003          GLuint src0_subreg_nr:5;
1004          GLuint src0_reg_nr:8;
1005          GLuint src0_abs:1;
1006          GLuint src0_negate:1;
1007          GLuint src0_address_mode:1;
1008          GLuint src0_horiz_stride:2;
1009          GLuint src0_width:3;
1010          GLuint src0_vert_stride:4;
1011          GLuint flag_reg_nr:1;
1012          GLuint pad:6;
1013       } da1;
1014
1015       struct
1016       {
1017          GLint src0_indirect_offset:10;
1018          GLuint src0_subreg_nr:3;
1019          GLuint src0_abs:1;
1020          GLuint src0_negate:1;
1021          GLuint src0_address_mode:1;
1022          GLuint src0_horiz_stride:2;
1023          GLuint src0_width:3;
1024          GLuint src0_vert_stride:4;
1025          GLuint flag_reg_nr:1;
1026          GLuint pad:6;
1027       } ia1;
1028
1029       struct
1030       {
1031          GLuint src0_swz_x:2;
1032          GLuint src0_swz_y:2;
1033          GLuint src0_subreg_nr:1;
1034          GLuint src0_reg_nr:8;
1035          GLuint src0_abs:1;
1036          GLuint src0_negate:1;
1037          GLuint src0_address_mode:1;
1038          GLuint src0_swz_z:2;
1039          GLuint src0_swz_w:2;
1040          GLuint pad0:1;
1041          GLuint src0_vert_stride:4;
1042          GLuint flag_reg_nr:1;
1043          GLuint pad1:6;
1044       } da16;
1045
1046       struct
1047       {
1048          GLuint src0_swz_x:2;
1049          GLuint src0_swz_y:2;
1050          GLint src0_indirect_offset:6;
1051          GLuint src0_subreg_nr:3;
1052          GLuint src0_abs:1;
1053          GLuint src0_negate:1;
1054          GLuint src0_address_mode:1;
1055          GLuint src0_swz_z:2;
1056          GLuint src0_swz_w:2;
1057          GLuint pad0:1;
1058          GLuint src0_vert_stride:4;
1059          GLuint flag_reg_nr:1;
1060          GLuint pad1:6;
1061       } ia16;
1062
1063        struct
1064        {
1065            GLuint pad:26;
1066            GLuint end_of_thread:1;
1067            GLuint pad1:1;
1068            GLuint sfid:4;
1069        } send_gen5;  /* for Ironlake only */
1070
1071    } bits2;
1072
1073    union
1074    {
1075       struct
1076       {
1077          GLuint src1_subreg_nr:5;
1078          GLuint src1_reg_nr:8;
1079          GLuint src1_abs:1;
1080          GLuint src1_negate:1;
1081          GLuint src1_address_mode:1;
1082          GLuint src1_horiz_stride:2;
1083          GLuint src1_width:3;
1084          GLuint src1_vert_stride:4;
1085          GLuint pad0:7;
1086       } da1;
1087
1088       struct
1089       {
1090          GLuint src1_swz_x:2;
1091          GLuint src1_swz_y:2;
1092          GLuint src1_subreg_nr:1;
1093          GLuint src1_reg_nr:8;
1094          GLuint src1_abs:1;
1095          GLuint src1_negate:1;
1096          GLuint src1_address_mode:1;
1097          GLuint src1_swz_z:2;
1098          GLuint src1_swz_w:2;
1099          GLuint pad1:1;
1100          GLuint src1_vert_stride:4;
1101          GLuint pad2:7;
1102       } da16;
1103
1104       struct
1105       {
1106          GLint  src1_indirect_offset:10;
1107          GLuint src1_subreg_nr:3;
1108          GLuint src1_abs:1;
1109          GLuint src1_negate:1;
1110          GLuint src1_address_mode:1;
1111          GLuint src1_horiz_stride:2;
1112          GLuint src1_width:3;
1113          GLuint src1_vert_stride:4;
1114          GLuint flag_reg_nr:1;
1115          GLuint pad1:6;
1116       } ia1;
1117
1118       struct
1119       {
1120          GLuint src1_swz_x:2;
1121          GLuint src1_swz_y:2;
1122          GLint  src1_indirect_offset:6;
1123          GLuint src1_subreg_nr:3;
1124          GLuint src1_abs:1;
1125          GLuint src1_negate:1;
1126          GLuint pad0:1;
1127          GLuint src1_swz_z:2;
1128          GLuint src1_swz_w:2;
1129          GLuint pad1:1;
1130          GLuint src1_vert_stride:4;
1131          GLuint flag_reg_nr:1;
1132          GLuint pad2:6;
1133       } ia16;
1134
1135
1136       struct
1137       {
1138          GLint  jump_count:16;  /* note: signed */
1139          GLuint  pop_count:4;
1140          GLuint  pad0:12;
1141       } if_else;
1142
1143       /* This is also used for gen7 IF/ELSE instructions */
1144       struct
1145       {
1146          /* Signed jump distance to the ip to jump to if all channels
1147           * are disabled after the break or continue.  It should point
1148           * to the end of the innermost control flow block, as that's
1149           * where some channel could get re-enabled.
1150           */
1151          int jip:16;
1152
1153          /* Signed jump distance to the location to resume execution
1154           * of this channel if it's enabled for the break or continue.
1155           */
1156          int uip:16;
1157       } break_cont;
1158
1159       struct {
1160          GLuint function:4;
1161          GLuint int_type:1;
1162          GLuint precision:1;
1163          GLuint saturate:1;
1164          GLuint data_type:1;
1165          GLuint pad0:8;
1166          GLuint response_length:4;
1167          GLuint msg_length:4;
1168          GLuint msg_target:4;
1169          GLuint pad1:3;
1170          GLuint end_of_thread:1;
1171       } math;
1172
1173       struct {
1174          GLuint function:4;
1175          GLuint int_type:1;
1176          GLuint precision:1;
1177          GLuint saturate:1;
1178          GLuint data_type:1;
1179          GLuint snapshot:1;
1180          GLuint pad0:10;
1181          GLuint header_present:1;
1182          GLuint response_length:5;
1183          GLuint msg_length:4;
1184          GLuint pad1:2;
1185          GLuint end_of_thread:1;
1186       } math_gen5;
1187
1188       struct {
1189          GLuint binding_table_index:8;
1190          GLuint sampler:4;
1191          GLuint return_format:2;
1192          GLuint msg_type:2;
1193          GLuint response_length:4;
1194          GLuint msg_length:4;
1195          GLuint msg_target:4;
1196          GLuint pad1:3;
1197          GLuint end_of_thread:1;
1198       } sampler;
1199
1200       struct {
1201          GLuint binding_table_index:8;
1202          GLuint sampler:4;
1203          GLuint msg_type:4;
1204          GLuint response_length:4;
1205          GLuint msg_length:4;
1206          GLuint msg_target:4;
1207          GLuint pad1:3;
1208          GLuint end_of_thread:1;
1209       } sampler_g4x;
1210
1211       struct {
1212          GLuint binding_table_index:8;
1213          GLuint sampler:4;
1214          GLuint msg_type:4;
1215          GLuint simd_mode:2;
1216          GLuint pad0:1;
1217          GLuint header_present:1;
1218          GLuint response_length:5;
1219          GLuint msg_length:4;
1220          GLuint pad1:2;
1221          GLuint end_of_thread:1;
1222       } sampler_gen5;
1223
1224       struct {
1225          GLuint binding_table_index:8;
1226          GLuint sampler:4;
1227          GLuint msg_type:5;
1228          GLuint simd_mode:2;
1229          GLuint header_present:1;
1230          GLuint response_length:5;
1231          GLuint msg_length:4;
1232          GLuint pad1:2;
1233          GLuint end_of_thread:1;
1234       } sampler_gen7;
1235
1236       struct brw_urb_immediate urb;
1237
1238       struct {
1239          GLuint opcode:4;
1240          GLuint offset:6;
1241          GLuint swizzle_control:2;
1242          GLuint pad:1;
1243          GLuint allocate:1;
1244          GLuint used:1;
1245          GLuint complete:1;
1246          GLuint pad0:3;
1247          GLuint header_present:1;
1248          GLuint response_length:5;
1249          GLuint msg_length:4;
1250          GLuint pad1:2;
1251          GLuint end_of_thread:1;
1252       } urb_gen5;
1253
1254       struct {
1255          GLuint opcode:3;
1256          GLuint offset:11;
1257          GLuint swizzle_control:1;
1258          GLuint complete:1;
1259          GLuint per_slot_offset:1;
1260          GLuint pad0:2;
1261          GLuint header_present:1;
1262          GLuint response_length:5;
1263          GLuint msg_length:4;
1264          GLuint pad1:2;
1265          GLuint end_of_thread:1;
1266       } urb_gen7;
1267
1268       struct {
1269          GLuint binding_table_index:8;
1270          GLuint msg_control:4;
1271          GLuint msg_type:2;
1272          GLuint target_cache:2;
1273          GLuint response_length:4;
1274          GLuint msg_length:4;
1275          GLuint msg_target:4;
1276          GLuint pad1:3;
1277          GLuint end_of_thread:1;
1278       } dp_read;
1279
1280       struct {
1281          GLuint binding_table_index:8;
1282          GLuint msg_control:3;
1283          GLuint msg_type:3;
1284          GLuint target_cache:2;
1285          GLuint response_length:4;
1286          GLuint msg_length:4;
1287          GLuint msg_target:4;
1288          GLuint pad1:3;
1289          GLuint end_of_thread:1;
1290       } dp_read_g4x;
1291
1292       struct {
1293          GLuint binding_table_index:8;
1294          GLuint msg_control:3;
1295          GLuint msg_type:3;
1296          GLuint target_cache:2;
1297          GLuint pad0:3;
1298          GLuint header_present:1;
1299          GLuint response_length:5;
1300          GLuint msg_length:4;
1301          GLuint pad1:2;
1302          GLuint end_of_thread:1;
1303       } dp_read_gen5;
1304
1305       struct {
1306          GLuint binding_table_index:8;
1307          GLuint msg_control:3;
1308          GLuint pixel_scoreboard_clear:1;
1309          GLuint msg_type:3;
1310          GLuint send_commit_msg:1;
1311          GLuint response_length:4;
1312          GLuint msg_length:4;
1313          GLuint msg_target:4;
1314          GLuint pad1:3;
1315          GLuint end_of_thread:1;
1316       } dp_write;
1317
1318       struct {
1319          GLuint binding_table_index:8;
1320          GLuint msg_control:3;
1321          GLuint pixel_scoreboard_clear:1;
1322          GLuint msg_type:3;
1323          GLuint send_commit_msg:1;
1324          GLuint pad0:3;
1325          GLuint header_present:1;
1326          GLuint response_length:5;
1327          GLuint msg_length:4;
1328          GLuint pad1:2;
1329          GLuint end_of_thread:1;
1330       } dp_write_gen5;
1331
1332       /* Sandybridge DP for sample cache, constant cache, render cache */
1333       struct {
1334          GLuint binding_table_index:8;
1335          GLuint msg_control:5;
1336          GLuint msg_type:3;
1337          GLuint pad0:3;
1338          GLuint header_present:1;
1339          GLuint response_length:5;
1340          GLuint msg_length:4;
1341          GLuint pad1:2;
1342          GLuint end_of_thread:1;
1343       } dp_sampler_const_cache;
1344
1345       struct {
1346          GLuint binding_table_index:8;
1347          GLuint msg_control:3;
1348          GLuint slot_group_select:1;
1349          GLuint pixel_scoreboard_clear:1;
1350          GLuint msg_type:4;
1351          GLuint send_commit_msg:1;
1352          GLuint pad0:1;
1353          GLuint header_present:1;
1354          GLuint response_length:5;
1355          GLuint msg_length:4;
1356          GLuint pad1:2;
1357          GLuint end_of_thread:1;
1358       } gen6_dp;
1359
1360       /* See volume vol5c.2 sections 2.11.2.1.5 and 2.11.21.2.2. */
1361       struct {
1362          GLuint binding_table_index:8;
1363          GLuint msg_control:3;
1364          GLuint slot_group_select:1;
1365          GLuint pixel_scoreboard_clear:1;
1366          GLuint pad0:1;
1367          GLuint msg_type:4;
1368          GLuint pad1:1;
1369          GLuint header_present:1;
1370          GLuint response_length:5;
1371          GLuint msg_length:4;
1372          GLuint pad2:2;
1373          GLuint end_of_thread:1;
1374       } gen7_dp;
1375
1376       struct {
1377          GLuint function_control:16;
1378          GLuint response_length:4;
1379          GLuint msg_length:4;
1380          GLuint msg_target:4;
1381          GLuint pad1:3;
1382          GLuint end_of_thread:1;
1383       } generic;
1384
1385       /* Of this struct, only end_of_thread is not present for gen6. */
1386       struct {
1387          GLuint function_control:19;
1388          GLuint header_present:1;
1389          GLuint response_length:5;
1390          GLuint msg_length:4;
1391          GLuint pad1:2;
1392          GLuint end_of_thread:1;
1393       } generic_gen5;
1394
1395       GLint d;
1396       GLuint ud;
1397       float f;
1398    } bits3;
1399 };
1400
1401
1402 #endif