src/mesa/drivers/dri/i965/brw_surface_formats.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24
  25 #include "isl/isl.h"
  26
  27 #include "brw_context.h"
  28 #include "brw_state.h"
  29 #include "brw_defines.h"
  30
  31 uint32_t
  32 brw_isl_format_for_mesa_format(mesa_format mesa_format)
  33 {
  34    /* This table is ordered according to the enum ordering in formats.h.  We do
  35     * expect that enum to be extended without our explicit initialization
  36     * staying in sync, so we initialize to 0 even though
  37     * ISL_FORMAT_R32G32B32A32_FLOAT happens to also be 0.
  38     */
  39    static const uint32_t table[MESA_FORMAT_COUNT] =
  40    {
  41       [MESA_FORMAT_A8B8G8R8_UNORM] = 0,
  42       [MESA_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
  43       [MESA_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
  44       [MESA_FORMAT_A8R8G8B8_UNORM] = 0,
  45       [MESA_FORMAT_X8B8G8R8_UNORM] = 0,
  46       [MESA_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
  47       [MESA_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
  48       [MESA_FORMAT_X8R8G8B8_UNORM] = 0,
  49       [MESA_FORMAT_BGR_UNORM8] = 0,
  50       [MESA_FORMAT_RGB_UNORM8] = ISL_FORMAT_R8G8B8_UNORM,
  51       [MESA_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
  52       [MESA_FORMAT_R5G6B5_UNORM] = 0,
  53       [MESA_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
  54       [MESA_FORMAT_A4R4G4B4_UNORM] = 0,
  55       [MESA_FORMAT_A1B5G5R5_UNORM] = 0,
  56       [MESA_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
  57       [MESA_FORMAT_A1R5G5B5_UNORM] = 0,
  58       [MESA_FORMAT_L4A4_UNORM] = 0,
  59       [MESA_FORMAT_L8A8_UNORM] = ISL_FORMAT_L8A8_UNORM,
  60       [MESA_FORMAT_A8L8_UNORM] = 0,
  61       [MESA_FORMAT_L16A16_UNORM] = ISL_FORMAT_L16A16_UNORM,
  62       [MESA_FORMAT_A16L16_UNORM] = 0,
  63       [MESA_FORMAT_B2G3R3_UNORM] = 0,
  64       [MESA_FORMAT_A_UNORM8] = ISL_FORMAT_A8_UNORM,
  65       [MESA_FORMAT_A_UNORM16] = ISL_FORMAT_A16_UNORM,
  66       [MESA_FORMAT_L_UNORM8] = ISL_FORMAT_L8_UNORM,
  67       [MESA_FORMAT_L_UNORM16] = ISL_FORMAT_L16_UNORM,
  68       [MESA_FORMAT_I_UNORM8] = ISL_FORMAT_I8_UNORM,
  69       [MESA_FORMAT_I_UNORM16] = ISL_FORMAT_I16_UNORM,
  70       [MESA_FORMAT_YCBCR_REV] = ISL_FORMAT_YCRCB_NORMAL,
  71       [MESA_FORMAT_YCBCR] = ISL_FORMAT_YCRCB_SWAPUVY,
  72       [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM,
  73       [MESA_FORMAT_R8G8_UNORM] = ISL_FORMAT_R8G8_UNORM,
  74       [MESA_FORMAT_G8R8_UNORM] = 0,
  75       [MESA_FORMAT_R_UNORM16] = ISL_FORMAT_R16_UNORM,
  76       [MESA_FORMAT_R16G16_UNORM] = ISL_FORMAT_R16G16_UNORM,
  77       [MESA_FORMAT_G16R16_UNORM] = 0,
  78       [MESA_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
  79       [MESA_FORMAT_S8_UINT_Z24_UNORM] = 0,
  80       [MESA_FORMAT_Z24_UNORM_S8_UINT] = 0,
  81       [MESA_FORMAT_Z_UNORM16] = 0,
  82       [MESA_FORMAT_Z24_UNORM_X8_UINT] = 0,
  83       [MESA_FORMAT_X8_UINT_Z24_UNORM] = 0,
  84       [MESA_FORMAT_Z_UNORM32] = 0,
  85       [MESA_FORMAT_S_UINT8] = ISL_FORMAT_R8_UINT,
  86
  87       [MESA_FORMAT_BGR_SRGB8] = 0,
  88       [MESA_FORMAT_A8B8G8R8_SRGB] = 0,
  89       [MESA_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
  90       [MESA_FORMAT_A8R8G8B8_SRGB] = 0,
  91       [MESA_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
  92       [MESA_FORMAT_X8R8G8B8_SRGB] = 0,
  93       [MESA_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
  94       [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
  95       [MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
  96       [MESA_FORMAT_A8L8_SRGB] = 0,
  97       [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_DXT1_RGB_SRGB,
  98       [MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
  99       [MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
 100       [MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
 101
 102       [MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
 103       [MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
 104       [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_DXT1_RGB,
 105       [MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
 106       [MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
 107       [MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
 108
 109       [MESA_FORMAT_RGBA_FLOAT32] = ISL_FORMAT_R32G32B32A32_FLOAT,
 110       [MESA_FORMAT_RGBA_FLOAT16] = ISL_FORMAT_R16G16B16A16_FLOAT,
 111       [MESA_FORMAT_RGB_FLOAT32] = ISL_FORMAT_R32G32B32_FLOAT,
 112       [MESA_FORMAT_RGB_FLOAT16] = 0,
 113       [MESA_FORMAT_A_FLOAT32] = ISL_FORMAT_A32_FLOAT,
 114       [MESA_FORMAT_A_FLOAT16] = ISL_FORMAT_A16_FLOAT,
 115       [MESA_FORMAT_L_FLOAT32] = ISL_FORMAT_L32_FLOAT,
 116       [MESA_FORMAT_L_FLOAT16] = ISL_FORMAT_L16_FLOAT,
 117       [MESA_FORMAT_LA_FLOAT32] = ISL_FORMAT_L32A32_FLOAT,
 118       [MESA_FORMAT_LA_FLOAT16] = ISL_FORMAT_L16A16_FLOAT,
 119       [MESA_FORMAT_I_FLOAT32] = ISL_FORMAT_I32_FLOAT,
 120       [MESA_FORMAT_I_FLOAT16] = ISL_FORMAT_I16_FLOAT,
 121       [MESA_FORMAT_R_FLOAT32] = ISL_FORMAT_R32_FLOAT,
 122       [MESA_FORMAT_R_FLOAT16] = ISL_FORMAT_R16_FLOAT,
 123       [MESA_FORMAT_RG_FLOAT32] = ISL_FORMAT_R32G32_FLOAT,
 124       [MESA_FORMAT_RG_FLOAT16] = ISL_FORMAT_R16G16_FLOAT,
 125
 126       [MESA_FORMAT_A_UINT8] = 0,
 127       [MESA_FORMAT_A_UINT16] = 0,
 128       [MESA_FORMAT_A_UINT32] = 0,
 129       [MESA_FORMAT_A_SINT8] = 0,
 130       [MESA_FORMAT_A_SINT16] = 0,
 131       [MESA_FORMAT_A_SINT32] = 0,
 132
 133       [MESA_FORMAT_I_UINT8] = 0,
 134       [MESA_FORMAT_I_UINT16] = 0,
 135       [MESA_FORMAT_I_UINT32] = 0,
 136       [MESA_FORMAT_I_SINT8] = 0,
 137       [MESA_FORMAT_I_SINT16] = 0,
 138       [MESA_FORMAT_I_SINT32] = 0,
 139
 140       [MESA_FORMAT_L_UINT8] = 0,
 141       [MESA_FORMAT_L_UINT16] = 0,
 142       [MESA_FORMAT_L_UINT32] = 0,
 143       [MESA_FORMAT_L_SINT8] = 0,
 144       [MESA_FORMAT_L_SINT16] = 0,
 145       [MESA_FORMAT_L_SINT32] = 0,
 146
 147       [MESA_FORMAT_LA_UINT8] = 0,
 148       [MESA_FORMAT_LA_UINT16] = 0,
 149       [MESA_FORMAT_LA_UINT32] = 0,
 150       [MESA_FORMAT_LA_SINT8] = 0,
 151       [MESA_FORMAT_LA_SINT16] = 0,
 152       [MESA_FORMAT_LA_SINT32] = 0,
 153
 154       [MESA_FORMAT_R_SINT8] = ISL_FORMAT_R8_SINT,
 155       [MESA_FORMAT_RG_SINT8] = ISL_FORMAT_R8G8_SINT,
 156       [MESA_FORMAT_RGB_SINT8] = ISL_FORMAT_R8G8B8_SINT,
 157       [MESA_FORMAT_RGBA_SINT8] = ISL_FORMAT_R8G8B8A8_SINT,
 158       [MESA_FORMAT_R_SINT16] = ISL_FORMAT_R16_SINT,
 159       [MESA_FORMAT_RG_SINT16] = ISL_FORMAT_R16G16_SINT,
 160       [MESA_FORMAT_RGB_SINT16] = ISL_FORMAT_R16G16B16_SINT,
 161       [MESA_FORMAT_RGBA_SINT16] = ISL_FORMAT_R16G16B16A16_SINT,
 162       [MESA_FORMAT_R_SINT32] = ISL_FORMAT_R32_SINT,
 163       [MESA_FORMAT_RG_SINT32] = ISL_FORMAT_R32G32_SINT,
 164       [MESA_FORMAT_RGB_SINT32] = ISL_FORMAT_R32G32B32_SINT,
 165       [MESA_FORMAT_RGBA_SINT32] = ISL_FORMAT_R32G32B32A32_SINT,
 166
 167       [MESA_FORMAT_R_UINT8] = ISL_FORMAT_R8_UINT,
 168       [MESA_FORMAT_RG_UINT8] = ISL_FORMAT_R8G8_UINT,
 169       [MESA_FORMAT_RGB_UINT8] = ISL_FORMAT_R8G8B8_UINT,
 170       [MESA_FORMAT_RGBA_UINT8] = ISL_FORMAT_R8G8B8A8_UINT,
 171       [MESA_FORMAT_R_UINT16] = ISL_FORMAT_R16_UINT,
 172       [MESA_FORMAT_RG_UINT16] = ISL_FORMAT_R16G16_UINT,
 173       [MESA_FORMAT_RGB_UINT16] = ISL_FORMAT_R16G16B16_UINT,
 174       [MESA_FORMAT_RGBA_UINT16] = ISL_FORMAT_R16G16B16A16_UINT,
 175       [MESA_FORMAT_R_UINT32] = ISL_FORMAT_R32_UINT,
 176       [MESA_FORMAT_RG_UINT32] = ISL_FORMAT_R32G32_UINT,
 177       [MESA_FORMAT_RGB_UINT32] = ISL_FORMAT_R32G32B32_UINT,
 178       [MESA_FORMAT_RGBA_UINT32] = ISL_FORMAT_R32G32B32A32_UINT,
 179
 180       [MESA_FORMAT_R_SNORM8] = ISL_FORMAT_R8_SNORM,
 181       [MESA_FORMAT_R8G8_SNORM] = ISL_FORMAT_R8G8_SNORM,
 182       [MESA_FORMAT_X8B8G8R8_SNORM] = 0,
 183       [MESA_FORMAT_A8B8G8R8_SNORM] = 0,
 184       [MESA_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
 185       [MESA_FORMAT_R_SNORM16] = ISL_FORMAT_R16_SNORM,
 186       [MESA_FORMAT_R16G16_SNORM] = ISL_FORMAT_R16G16_SNORM,
 187       [MESA_FORMAT_RGB_SNORM16] = ISL_FORMAT_R16G16B16_SNORM,
 188       [MESA_FORMAT_RGBA_SNORM16] = ISL_FORMAT_R16G16B16A16_SNORM,
 189       [MESA_FORMAT_RGBA_UNORM16] = ISL_FORMAT_R16G16B16A16_UNORM,
 190
 191       [MESA_FORMAT_R_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
 192       [MESA_FORMAT_R_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
 193       [MESA_FORMAT_RG_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
 194       [MESA_FORMAT_RG_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
 195
 196       [MESA_FORMAT_L_LATC1_UNORM] = 0,
 197       [MESA_FORMAT_L_LATC1_SNORM] = 0,
 198       [MESA_FORMAT_LA_LATC2_UNORM] = 0,
 199       [MESA_FORMAT_LA_LATC2_SNORM] = 0,
 200
 201       [MESA_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
 202       [MESA_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
 203       [MESA_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
 204       [MESA_FORMAT_ETC2_RGBA8_EAC] = ISL_FORMAT_ETC2_EAC_RGBA8,
 205       [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
 206       [MESA_FORMAT_ETC2_R11_EAC] = ISL_FORMAT_EAC_R11,
 207       [MESA_FORMAT_ETC2_RG11_EAC] = ISL_FORMAT_EAC_RG11,
 208       [MESA_FORMAT_ETC2_SIGNED_R11_EAC] = ISL_FORMAT_EAC_SIGNED_R11,
 209       [MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = ISL_FORMAT_EAC_SIGNED_RG11,
 210       [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_RGB8_PTA,
 211       [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_SRGB8_PTA,
 212
 213       [MESA_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
 214       [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM] = ISL_FORMAT_BC7_UNORM_SRGB,
 215       [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT] = ISL_FORMAT_BC6H_SF16,
 216       [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT] = ISL_FORMAT_BC6H_UF16,
 217
 218       [MESA_FORMAT_RGBA_ASTC_4x4]           = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
 219       [MESA_FORMAT_RGBA_ASTC_5x4]           = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
 220       [MESA_FORMAT_RGBA_ASTC_5x5]           = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
 221       [MESA_FORMAT_RGBA_ASTC_6x5]           = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
 222       [MESA_FORMAT_RGBA_ASTC_6x6]           = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
 223       [MESA_FORMAT_RGBA_ASTC_8x5]           = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
 224       [MESA_FORMAT_RGBA_ASTC_8x6]           = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
 225       [MESA_FORMAT_RGBA_ASTC_8x8]           = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
 226       [MESA_FORMAT_RGBA_ASTC_10x5]          = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
 227       [MESA_FORMAT_RGBA_ASTC_10x6]          = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
 228       [MESA_FORMAT_RGBA_ASTC_10x8]          = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
 229       [MESA_FORMAT_RGBA_ASTC_10x10]         = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
 230       [MESA_FORMAT_RGBA_ASTC_12x10]         = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
 231       [MESA_FORMAT_RGBA_ASTC_12x12]         = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
 232       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4]   = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
 233       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4]   = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
 234       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5]   = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
 235       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5]   = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
 236       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6]   = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
 237       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5]   = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
 238       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6]   = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
 239       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8]   = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
 240       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5]  = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
 241       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6]  = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
 242       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8]  = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
 243       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
 244       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
 245       [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
 246
 247       [MESA_FORMAT_A_SNORM8] = 0,
 248       [MESA_FORMAT_L_SNORM8] = 0,
 249       [MESA_FORMAT_L8A8_SNORM] = 0,
 250       [MESA_FORMAT_A8L8_SNORM] = 0,
 251       [MESA_FORMAT_I_SNORM8] = 0,
 252       [MESA_FORMAT_A_SNORM16] = 0,
 253       [MESA_FORMAT_L_SNORM16] = 0,
 254       [MESA_FORMAT_LA_SNORM16] = 0,
 255       [MESA_FORMAT_I_SNORM16] = 0,
 256
 257       [MESA_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
 258       [MESA_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
 259
 260       [MESA_FORMAT_Z_FLOAT32] = 0,
 261       [MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = 0,
 262
 263       [MESA_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
 264       [MESA_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
 265       [MESA_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
 266
 267       [MESA_FORMAT_B4G4R4X4_UNORM] = 0,
 268       [MESA_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
 269       [MESA_FORMAT_R8G8B8X8_SNORM] = 0,
 270       [MESA_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
 271       [MESA_FORMAT_X8B8G8R8_SRGB] = 0,
 272       [MESA_FORMAT_RGBX_UINT8] = 0,
 273       [MESA_FORMAT_RGBX_SINT8] = 0,
 274       [MESA_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
 275       [MESA_FORMAT_RGBX_UNORM16] = ISL_FORMAT_R16G16B16X16_UNORM,
 276       [MESA_FORMAT_RGBX_SNORM16] = 0,
 277       [MESA_FORMAT_RGBX_FLOAT16] = ISL_FORMAT_R16G16B16X16_FLOAT,
 278       [MESA_FORMAT_RGBX_UINT16] = 0,
 279       [MESA_FORMAT_RGBX_SINT16] = 0,
 280       [MESA_FORMAT_RGBX_FLOAT32] = ISL_FORMAT_R32G32B32X32_FLOAT,
 281       [MESA_FORMAT_RGBX_UINT32] = 0,
 282       [MESA_FORMAT_RGBX_SINT32] = 0,
 283    };
 284    assert(mesa_format < MESA_FORMAT_COUNT);
 285    return table[mesa_format];
 286 }
 287
 288 void
 289 brw_init_surface_formats(struct brw_context *brw)
 290 {
 291    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 292    struct gl_context *ctx = &brw->ctx;
 293    int gen;
 294    mesa_format format;
 295
 296    memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported));
 297
 298    gen = brw->gen * 10;
 299    if (brw->is_g4x || brw->is_haswell)
 300       gen += 5;
 301
 302    for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
 303       uint32_t texture, render;
 304       bool is_integer = _mesa_is_format_integer_color(format);
 305
 306       render = texture = brw_isl_format_for_mesa_format(format);
 307
 308       /* The value of ISL_FORMAT_R32G32B32A32_FLOAT is 0, so don't skip
 309        * it.
 310        */
 311       if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32)
 312          continue;
 313
 314       /* Don't advertise 8 and 16-bit RGB formats to core mesa.  This ensures
 315        * that they are renderable from an API perspective since core mesa will
 316        * fall back to RGBA or RGBX (we can't render to non-power-of-two
 317        * formats).  For 8-bit, formats, this also keeps us from hitting some
 318        * nasty corners in intel_miptree_map_blit if you ever try to map one.
 319        */
 320       int format_size = _mesa_get_format_bytes(format);
 321       if (format_size == 3 || format_size == 6)
 322          continue;
 323
 324       if (isl_format_supports_sampling(devinfo, texture) &&
 325           (isl_format_supports_filtering(devinfo, texture) || is_integer))
 326          ctx->TextureFormatSupported[format] = true;
 327
 328       /* Re-map some render target formats to make them supported when they
 329        * wouldn't be using their format for texturing.
 330        */
 331       switch (render) {
 332          /* For these formats, we just need to read/write the first
 333           * channel into R, which is to say that we just treat them as
 334           * GL_RED.
 335           */
 336       case ISL_FORMAT_I32_FLOAT:
 337       case ISL_FORMAT_L32_FLOAT:
 338          render = ISL_FORMAT_R32_FLOAT;
 339          break;
 340       case ISL_FORMAT_I16_FLOAT:
 341       case ISL_FORMAT_L16_FLOAT:
 342          render = ISL_FORMAT_R16_FLOAT;
 343          break;
 344       case ISL_FORMAT_I8_UNORM:
 345       case ISL_FORMAT_L8_UNORM:
 346          render = ISL_FORMAT_R8_UNORM;
 347          break;
 348       case ISL_FORMAT_I16_UNORM:
 349       case ISL_FORMAT_L16_UNORM:
 350          render = ISL_FORMAT_R16_UNORM;
 351          break;
 352       case ISL_FORMAT_R16G16B16X16_UNORM:
 353          render = ISL_FORMAT_R16G16B16A16_UNORM;
 354          break;
 355       case ISL_FORMAT_R16G16B16X16_FLOAT:
 356          render = ISL_FORMAT_R16G16B16A16_FLOAT;
 357          break;
 358       case ISL_FORMAT_B8G8R8X8_UNORM:
 359          /* XRGB is handled as ARGB because the chips in this family
 360           * cannot render to XRGB targets.  This means that we have to
 361           * mask writes to alpha (ala glColorMask) and reconfigure the
 362           * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 363           * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 364           * used. On Gen8+ BGRX is actually allowed (but not RGBX).
 365           */
 366          if (!isl_format_supports_rendering(devinfo, texture))
 367             render = ISL_FORMAT_B8G8R8A8_UNORM;
 368          break;
 369       case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
 370          if (!isl_format_supports_rendering(devinfo, texture))
 371             render = ISL_FORMAT_B8G8R8A8_UNORM_SRGB;
 372          break;
 373       case ISL_FORMAT_R8G8B8X8_UNORM:
 374          render = ISL_FORMAT_R8G8B8A8_UNORM;
 375          break;
 376       case ISL_FORMAT_R8G8B8X8_UNORM_SRGB:
 377          render = ISL_FORMAT_R8G8B8A8_UNORM_SRGB;
 378          break;
 379       }
 380
 381       /* Note that GL_EXT_texture_integer says that blending doesn't occur for
 382        * integer, so we don't need hardware support for blending on it.  Other
 383        * than that, GL in general requires alpha blending for render targets,
 384        * even though we don't support it for some formats.
 385        */
 386       if (isl_format_supports_rendering(devinfo, render) &&
 387           (isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
 388          brw->render_target_format[format] = render;
 389          brw->format_supported_as_render_target[format] = true;
 390       }
 391    }
 392
 393    /* We will check this table for FBO completeness, but the surface format
 394     * table above only covered color rendering.
 395     */
 396    brw->format_supported_as_render_target[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
 397    brw->format_supported_as_render_target[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
 398    brw->format_supported_as_render_target[MESA_FORMAT_S_UINT8] = true;
 399    brw->format_supported_as_render_target[MESA_FORMAT_Z_FLOAT32] = true;
 400    brw->format_supported_as_render_target[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
 401    if (brw->gen >= 8)
 402       brw->format_supported_as_render_target[MESA_FORMAT_Z_UNORM16] = true;
 403
 404    /* We remap depth formats to a supported texturing format in
 405     * translate_tex_format().
 406     */
 407    ctx->TextureFormatSupported[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
 408    ctx->TextureFormatSupported[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
 409    ctx->TextureFormatSupported[MESA_FORMAT_Z_FLOAT32] = true;
 410    ctx->TextureFormatSupported[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
 411    ctx->TextureFormatSupported[MESA_FORMAT_S_UINT8] = true;
 412
 413    /* Benchmarking shows that Z16 is slower than Z24, so there's no reason to
 414     * use it unless you're under memory (not memory bandwidth) pressure.
 415     *
 416     * Apparently, the GPU's depth scoreboarding works on a 32-bit granularity,
 417     * which corresponds to one pixel in the depth buffer for Z24 or Z32 formats.
 418     * However, it corresponds to two pixels with Z16, which means both need to
 419     * hit the early depth case in order for it to happen.
 420     *
 421     * Other speculation is that we may be hitting increased fragment shader
 422     * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
 423     *
 424     * With the PMA stall workaround in place, Z16 is faster than Z24, as it
 425     * should be.
 426     */
 427    if (brw->gen >= 8)
 428       ctx->TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true;
 429
 430    /* The RGBX formats are not renderable. Normally these get mapped
 431     * internally to RGBA formats when rendering. However on Gen9+ when this
 432     * internal override is used fast clears don't work so they are disabled in
 433     * brw_meta_fast_clear. To avoid this problem we can just pretend not to
 434     * support RGBX formats at all. This will cause the upper layers of Mesa to
 435     * pick the RGBA formats instead. This works fine because when it is used
 436     * as a texture source the swizzle state is programmed to force the alpha
 437     * channel to 1.0 anyway. We could also do this for all gens except that
 438     * it's a bit more difficult when the hardware doesn't support texture
 439     * swizzling. Gens using the blorp have further problems because that
 440     * doesn't implement this swizzle override. We don't need to do this for
 441     * BGRX because that actually is supported natively on Gen8+.
 442     */
 443    if (brw->gen >= 9) {
 444       static const mesa_format rgbx_formats[] = {
 445          MESA_FORMAT_R8G8B8X8_UNORM,
 446          MESA_FORMAT_R8G8B8X8_SRGB,
 447          MESA_FORMAT_RGBX_UNORM16,
 448          MESA_FORMAT_RGBX_FLOAT16,
 449          MESA_FORMAT_RGBX_FLOAT32
 450       };
 451
 452       for (int i = 0; i < ARRAY_SIZE(rgbx_formats); i++) {
 453          ctx->TextureFormatSupported[rgbx_formats[i]] = false;
 454          brw->format_supported_as_render_target[rgbx_formats[i]] = false;
 455       }
 456    }
 457
 458    /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
 459     * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
 460     */
 461    ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
 462
 463    /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
 464     * MESA_FORMAT during glCompressedTexImage2D().
 465     * See intel_mipmap_tree::wraps_etc2.
 466     */
 467    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
 468    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8] = true;
 469    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
 470    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
 471    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_R11_EAC] = true;
 472    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RG11_EAC] = true;
 473    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
 474    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
 475    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
 476    ctx->TextureFormatSupported[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
 477 }
 478
 479 bool
 480 brw_render_target_supported(struct brw_context *brw,
 481                             struct gl_renderbuffer *rb)
 482 {
 483    mesa_format format = rb->Format;
 484
 485    /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
 486     * we would consider them renderable even though we don't have surface
 487     * support for their alpha behavior and don't have the blending unit
 488     * available to fake it like we do for XRGB8888.  Force them to being
 489     * unsupported.
 490     */
 491    if (_mesa_is_format_integer_color(format) &&
 492        rb->_BaseFormat != GL_RGBA &&
 493        rb->_BaseFormat != GL_RG &&
 494        rb->_BaseFormat != GL_RED)
 495       return false;
 496
 497    /* Under some conditions, MSAA is not supported for formats whose width is
 498     * more than 64 bits.
 499     */
 500    if (brw->gen < 8 &&
 501        rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
 502       /* Gen6: MSAA on >64 bit formats is unsupported. */
 503       if (brw->gen <= 6)
 504          return false;
 505
 506       /* Gen7: 8x MSAA on >64 bit formats is unsupported. */
 507       if (rb->NumSamples >= 8)
 508          return false;
 509    }
 510
 511    return brw->format_supported_as_render_target[format];
 512 }
 513
 514 GLuint
 515 translate_tex_format(struct brw_context *brw,
 516                      mesa_format mesa_format,
 517                      GLenum srgb_decode)
 518 {
 519    struct gl_context *ctx = &brw->ctx;
 520    if (srgb_decode == GL_SKIP_DECODE_EXT)
 521       mesa_format = _mesa_get_srgb_format_linear(mesa_format);
 522
 523    switch( mesa_format ) {
 524
 525    case MESA_FORMAT_Z_UNORM16:
 526       return ISL_FORMAT_R16_UNORM;
 527
 528    case MESA_FORMAT_Z24_UNORM_S8_UINT:
 529    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 530       return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
 531
 532    case MESA_FORMAT_Z_FLOAT32:
 533       return ISL_FORMAT_R32_FLOAT;
 534
 535    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
 536       return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
 537
 538    case MESA_FORMAT_RGBA_FLOAT32:
 539       /* The value of this ISL surface format is 0, which tricks the
 540        * assertion below.
 541        */
 542       return ISL_FORMAT_R32G32B32A32_FLOAT;
 543
 544    case MESA_FORMAT_SRGB_DXT1:
 545       if (brw->gen == 4 && !brw->is_g4x) {
 546          /* Work around missing SRGB DXT1 support on original gen4 by just
 547           * skipping SRGB decode.  It's not worth not supporting sRGB in
 548           * general to prevent this.
 549           */
 550          WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
 551          mesa_format = MESA_FORMAT_RGB_DXT1;
 552       }
 553       return brw_isl_format_for_mesa_format(mesa_format);
 554
 555    case MESA_FORMAT_RGBA_ASTC_4x4:
 556    case MESA_FORMAT_RGBA_ASTC_5x4:
 557    case MESA_FORMAT_RGBA_ASTC_5x5:
 558    case MESA_FORMAT_RGBA_ASTC_6x5:
 559    case MESA_FORMAT_RGBA_ASTC_6x6:
 560    case MESA_FORMAT_RGBA_ASTC_8x5:
 561    case MESA_FORMAT_RGBA_ASTC_8x6:
 562    case MESA_FORMAT_RGBA_ASTC_8x8:
 563    case MESA_FORMAT_RGBA_ASTC_10x5:
 564    case MESA_FORMAT_RGBA_ASTC_10x6:
 565    case MESA_FORMAT_RGBA_ASTC_10x8:
 566    case MESA_FORMAT_RGBA_ASTC_10x10:
 567    case MESA_FORMAT_RGBA_ASTC_12x10:
 568    case MESA_FORMAT_RGBA_ASTC_12x12: {
 569       GLuint brw_fmt = brw_isl_format_for_mesa_format(mesa_format);
 570
 571       /**
 572        * It is possible to process these formats using the LDR Profile
 573        * or the Full Profile mode of the hardware. Because, it isn't
 574        * possible to determine if an HDR or LDR texture is being rendered, we
 575        * can't determine which mode to enable in the hardware. Therefore, to
 576        * handle all cases, always default to Full profile unless we are
 577        * processing sRGBs, which are incompatible with this mode.
 578        */
 579       if (ctx->Extensions.KHR_texture_compression_astc_hdr)
 580          brw_fmt |= GEN9_SURFACE_ASTC_HDR_FORMAT_BIT;
 581
 582       return brw_fmt;
 583    }
 584
 585    default:
 586       assert(brw_isl_format_for_mesa_format(mesa_format) != 0);
 587       return brw_isl_format_for_mesa_format(mesa_format);
 588    }
 589 }
 590
 591 /**
 592  * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum.
 593  */
 594 uint32_t
 595 brw_depth_format(struct brw_context *brw, mesa_format format)
 596 {
 597    switch (format) {
 598    case MESA_FORMAT_Z_UNORM16:
 599       return BRW_DEPTHFORMAT_D16_UNORM;
 600    case MESA_FORMAT_Z_FLOAT32:
 601       return BRW_DEPTHFORMAT_D32_FLOAT;
 602    case MESA_FORMAT_Z24_UNORM_X8_UINT:
 603       if (brw->gen >= 6) {
 604          return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
 605       } else {
 606          /* Use D24_UNORM_S8, not D24_UNORM_X8.
 607           *
 608           * D24_UNORM_X8 was not introduced until Gen5. (See the Ironlake PRM,
 609           * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
 610           * 3DSTATE_DEPTH_BUFFER.Surface_Format).
 611           *
 612           * However, on Gen5, D24_UNORM_X8 may be used only if separate
 613           * stencil is enabled, and we never enable it. From the Ironlake PRM,
 614           * same section as above, 3DSTATE_DEPTH_BUFFER's
 615           * "Separate Stencil Buffer Enable" bit:
 616           *
 617           * "If this field is disabled, the Surface Format of the depth
 618           *  buffer cannot be D24_UNORM_X8_UINT."
 619           */
 620          return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 621       }
 622    case MESA_FORMAT_Z24_UNORM_S8_UINT:
 623       return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 624    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
 625       return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
 626    default:
 627       unreachable("Unexpected depth format.");
 628    }
 629 }