src/mesa/drivers/dri/i965/brw_tcs.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_tcs.c
  26  *
  27  * Tessellation control shader state upload code.
  28  */
  29
  30 #include "brw_context.h"
  31 #include "compiler/brw_nir.h"
  32 #include "brw_program.h"
  33 #include "brw_state.h"
  34 #include "program/prog_parameter.h"
  35 #include "nir_builder.h"
  36
  37 static nir_shader *
  38 create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
  39                        const nir_shader_compiler_options *options,
  40                        const struct brw_tcs_prog_key *key)
  41 {
  42    nir_builder b;
  43    nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_TESS_CTRL,
  44                                   options);
  45    nir_shader *nir = b.shader;
  46    nir_variable *var;
  47    nir_intrinsic_instr *load;
  48    nir_intrinsic_instr *store;
  49    nir_ssa_def *zero = nir_imm_int(&b, 0);
  50    nir_ssa_def *invoc_id =
  51       nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0);
  52
  53    nir->info.inputs_read = key->outputs_written &
  54       ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
  55    nir->info.outputs_written = key->outputs_written;
  56    nir->info.tess.tcs_vertices_out = key->input_vertices;
  57    nir->info.name = ralloc_strdup(nir, "passthrough");
  58    nir->num_uniforms = 8 * sizeof(uint32_t);
  59
  60    var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
  61    var->data.location = 0;
  62    var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1");
  63    var->data.location = 1;
  64
  65    /* Write the patch URB header. */
  66    for (int i = 0; i <= 1; i++) {
  67       load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform);
  68       load->num_components = 4;
  69       load->src[0] = nir_src_for_ssa(zero);
  70       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
  71       nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t));
  72       nir_builder_instr_insert(&b, &load->instr);
  73
  74       store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output);
  75       store->num_components = 4;
  76       store->src[0] = nir_src_for_ssa(&load->dest.ssa);
  77       store->src[1] = nir_src_for_ssa(zero);
  78       nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i);
  79       nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
  80       nir_builder_instr_insert(&b, &store->instr);
  81    }
  82
  83    /* Copy inputs to outputs. */
  84    uint64_t varyings = nir->info.inputs_read;
  85
  86    while (varyings != 0) {
  87       const int varying = ffsll(varyings) - 1;
  88
  89       load = nir_intrinsic_instr_create(nir,
  90                                         nir_intrinsic_load_per_vertex_input);
  91       load->num_components = 4;
  92       load->src[0] = nir_src_for_ssa(invoc_id);
  93       load->src[1] = nir_src_for_ssa(zero);
  94       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
  95       nir_intrinsic_set_base(load, varying);
  96       nir_builder_instr_insert(&b, &load->instr);
  97
  98       store = nir_intrinsic_instr_create(nir,
  99                                          nir_intrinsic_store_per_vertex_output);
 100       store->num_components = 4;
 101       store->src[0] = nir_src_for_ssa(&load->dest.ssa);
 102       store->src[1] = nir_src_for_ssa(invoc_id);
 103       store->src[2] = nir_src_for_ssa(zero);
 104       nir_intrinsic_set_base(store, varying);
 105       nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
 106       nir_builder_instr_insert(&b, &store->instr);
 107
 108       varyings &= ~BITFIELD64_BIT(varying);
 109    }
 110
 111    nir_validate_shader(nir);
 112
 113    nir = brw_preprocess_nir(compiler, nir);
 114
 115    return nir;
 116 }
 117
 118 static void
 119 brw_tcs_debug_recompile(struct brw_context *brw, struct gl_program *prog,
 120                        const struct brw_tcs_prog_key *key)
 121 {
 122    perf_debug("Recompiling tessellation control shader for program %d\n",
 123               prog->Id);
 124
 125    bool found = false;
 126    const struct brw_tcs_prog_key *old_key =
 127       brw_find_previous_compile(&brw->cache, BRW_CACHE_TCS_PROG,
 128                                 key->program_string_id);
 129
 130    if (!old_key) {
 131       perf_debug("  Didn't find previous compile in the shader cache for "
 132                  "debug\n");
 133       return;
 134    }
 135
 136    found |= key_debug(brw, "input vertices", old_key->input_vertices,
 137                       key->input_vertices);
 138    found |= key_debug(brw, "outputs written", old_key->outputs_written,
 139                       key->outputs_written);
 140    found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written,
 141                       key->patch_outputs_written);
 142    found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode,
 143                       key->tes_primitive_mode);
 144    found |= key_debug(brw, "quads and equal_spacing workaround",
 145                       old_key->quads_workaround, key->quads_workaround);
 146    found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
 147
 148    if (!found) {
 149       perf_debug("  Something else\n");
 150    }
 151 }
 152
 153 static bool
 154 brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
 155                      struct brw_program *tep, struct brw_tcs_prog_key *key)
 156 {
 157    struct gl_context *ctx = &brw->ctx;
 158    const struct brw_compiler *compiler = brw->screen->compiler;
 159    const struct gen_device_info *devinfo = compiler->devinfo;
 160    struct brw_stage_state *stage_state = &brw->tcs.base;
 161    nir_shader *nir;
 162    struct brw_tcs_prog_data prog_data;
 163    bool start_busy = false;
 164    double start_time = 0;
 165
 166    void *mem_ctx = ralloc_context(NULL);
 167    if (tcp) {
 168       nir = tcp->program.nir;
 169    } else {
 170       const nir_shader_compiler_options *options =
 171          ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
 172       nir = create_passthrough_tcs(mem_ctx, compiler, options, key);
 173    }
 174
 175    memset(&prog_data, 0, sizeof(prog_data));
 176
 177    if (tcp) {
 178       brw_assign_common_binding_table_offsets(devinfo, &tcp->program,
 179                                               &prog_data.base.base, 0);
 180
 181       brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tcp->program,
 182                                   &prog_data.base.base,
 183                                   compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 184       brw_nir_analyze_ubo_ranges(compiler, tcp->program.nir, NULL,
 185                                  prog_data.base.base.ubo_ranges);
 186    } else {
 187       /* Upload the Patch URB Header as the first two uniforms.
 188        * Do the annoying scrambling so the shader doesn't have to.
 189        */
 190       assert(nir->num_uniforms == 32);
 191       prog_data.base.base.param = rzalloc_array(mem_ctx, uint32_t, 8);
 192       prog_data.base.base.nr_params = 8;
 193
 194       uint32_t *param = prog_data.base.base.param;
 195       for (int i = 0; i < 8; i++)
 196          param[i] = BRW_PARAM_BUILTIN_ZERO;
 197
 198       if (key->tes_primitive_mode == GL_QUADS) {
 199          for (int i = 0; i < 4; i++)
 200             param[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
 201
 202          param[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
 203          param[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y;
 204       } else if (key->tes_primitive_mode == GL_TRIANGLES) {
 205          for (int i = 0; i < 3; i++)
 206             param[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
 207
 208          param[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
 209       } else {
 210          assert(key->tes_primitive_mode == GL_ISOLINES);
 211          param[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y;
 212          param[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X;
 213       }
 214    }
 215
 216    int st_index = -1;
 217    if (unlikely((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep))
 218       st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
 219
 220    if (unlikely(brw->perf_debug)) {
 221       start_busy = brw->batch.last_bo && brw_bo_busy(brw->batch.last_bo);
 222       start_time = get_time();
 223    }
 224
 225    char *error_str;
 226    const unsigned *program =
 227       brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index,
 228                       &error_str);
 229    if (program == NULL) {
 230       if (tep) {
 231          tep->program.sh.data->LinkStatus = LINKING_FAILURE;
 232          ralloc_strcat(&tep->program.sh.data->InfoLog, error_str);
 233       }
 234
 235       _mesa_problem(NULL, "Failed to compile tessellation control shader: "
 236                     "%s\n", error_str);
 237
 238       ralloc_free(mem_ctx);
 239       return false;
 240    }
 241
 242    if (unlikely(brw->perf_debug)) {
 243       if (tcp) {
 244          if (tcp->compiled_once) {
 245             brw_tcs_debug_recompile(brw, &tcp->program, key);
 246          }
 247          tcp->compiled_once = true;
 248       }
 249
 250       if (start_busy && !brw_bo_busy(brw->batch.last_bo)) {
 251          perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
 252                     (get_time() - start_time) * 1000);
 253       }
 254    }
 255
 256    /* Scratch space is used for register spilling */
 257    brw_alloc_stage_scratch(brw, stage_state,
 258                            prog_data.base.base.total_scratch);
 259
 260    /* The param and pull_param arrays will be freed by the shader cache. */
 261    ralloc_steal(NULL, prog_data.base.base.param);
 262    ralloc_steal(NULL, prog_data.base.base.pull_param);
 263    brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG,
 264                     key, sizeof(*key),
 265                     program, prog_data.base.base.program_size,
 266                     &prog_data, sizeof(prog_data),
 267                     &stage_state->prog_offset, &brw->tcs.base.prog_data);
 268    ralloc_free(mem_ctx);
 269
 270    return true;
 271 }
 272
 273 void
 274 brw_tcs_populate_key(struct brw_context *brw,
 275                      struct brw_tcs_prog_key *key)
 276 {
 277    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 278    struct brw_program *tcp =
 279       (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
 280    struct brw_program *tep =
 281       (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
 282    struct gl_program *tes_prog = &tep->program;
 283
 284    uint64_t per_vertex_slots = tes_prog->info.inputs_read;
 285    uint32_t per_patch_slots = tes_prog->info.patch_inputs_read;
 286
 287    memset(key, 0, sizeof(*key));
 288
 289    if (tcp) {
 290       struct gl_program *prog = &tcp->program;
 291       per_vertex_slots |= prog->info.outputs_written;
 292       per_patch_slots |= prog->info.patch_outputs_written;
 293    }
 294
 295    if (devinfo->gen < 8 || !tcp)
 296       key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices;
 297    key->outputs_written = per_vertex_slots;
 298    key->patch_outputs_written = per_patch_slots;
 299
 300    /* We need to specialize our code generation for tessellation levels
 301     * based on the domain the DS is expecting to tessellate.
 302     */
 303    key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
 304    key->quads_workaround = devinfo->gen < 9 &&
 305                            tep->program.info.tess.primitive_mode == GL_QUADS &&
 306                            tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
 307
 308    if (tcp) {
 309       key->program_string_id = tcp->id;
 310
 311       /* _NEW_TEXTURE */
 312       brw_populate_sampler_prog_key_data(&brw->ctx, &tcp->program, &key->tex);
 313    }
 314 }
 315
 316 void
 317 brw_upload_tcs_prog(struct brw_context *brw)
 318 {
 319    struct brw_stage_state *stage_state = &brw->tcs.base;
 320    struct brw_tcs_prog_key key;
 321    /* BRW_NEW_TESS_PROGRAMS */
 322    struct brw_program *tcp =
 323       (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
 324    MAYBE_UNUSED struct brw_program *tep =
 325       (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
 326    assert(tep);
 327
 328    if (!brw_state_dirty(brw,
 329                         _NEW_TEXTURE,
 330                         BRW_NEW_PATCH_PRIMITIVE |
 331                         BRW_NEW_TESS_PROGRAMS))
 332       return;
 333
 334    brw_tcs_populate_key(brw, &key);
 335
 336    if (brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG, &key, sizeof(key),
 337                         &stage_state->prog_offset, &brw->tcs.base.prog_data,
 338                         true))
 339       return;
 340
 341    if (brw_disk_cache_upload_program(brw, MESA_SHADER_TESS_CTRL))
 342       return;
 343
 344    tcp = (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
 345    if (tcp)
 346       tcp->id = key.program_string_id;
 347
 348    MAYBE_UNUSED bool success = brw_codegen_tcs_prog(brw, tcp, tep, &key);
 349    assert(success);
 350 }
 351
 352 void
 353 brw_tcs_populate_default_key(const struct gen_device_info *devinfo,
 354                              struct brw_tcs_prog_key *key,
 355                              struct gl_shader_program *sh_prog,
 356                              struct gl_program *prog)
 357 {
 358    struct brw_program *btcp = brw_program(prog);
 359    const struct gl_linked_shader *tes =
 360       sh_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
 361
 362    memset(key, 0, sizeof(*key));
 363
 364    key->program_string_id = btcp->id;
 365    brw_setup_tex_for_precompile(devinfo, &key->tex, prog);
 366
 367    /* Guess that the input and output patches have the same dimensionality. */
 368    if (devinfo->gen < 8)
 369       key->input_vertices = prog->info.tess.tcs_vertices_out;
 370
 371    if (tes) {
 372       key->tes_primitive_mode = tes->Program->info.tess.primitive_mode;
 373       key->quads_workaround = devinfo->gen < 9 &&
 374                               tes->Program->info.tess.primitive_mode == GL_QUADS &&
 375                               tes->Program->info.tess.spacing == TESS_SPACING_EQUAL;
 376    } else {
 377       key->tes_primitive_mode = GL_TRIANGLES;
 378    }
 379
 380    key->outputs_written = prog->nir->info.outputs_written;
 381    key->patch_outputs_written = prog->nir->info.patch_outputs_written;
 382 }
 383
 384 bool
 385 brw_tcs_precompile(struct gl_context *ctx,
 386                    struct gl_shader_program *shader_prog,
 387                    struct gl_program *prog)
 388 {
 389    struct brw_context *brw = brw_context(ctx);
 390    struct brw_tcs_prog_key key;
 391    uint32_t old_prog_offset = brw->tcs.base.prog_offset;
 392    struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
 393    bool success;
 394
 395    struct brw_program *btcp = brw_program(prog);
 396    const struct gl_linked_shader *tes =
 397       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
 398    struct brw_program *btep = tes ? brw_program(tes->Program) : NULL;
 399
 400    brw_tcs_populate_default_key(&brw->screen->devinfo, &key, shader_prog, prog);
 401
 402    success = brw_codegen_tcs_prog(brw, btcp, btep, &key);
 403
 404    brw->tcs.base.prog_offset = old_prog_offset;
 405    brw->tcs.base.prog_data = old_prog_data;
 406
 407    return success;
 408 }