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Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "brw_program.h"
27
28 using namespace brw;
29
30 static void
31 generate_math1_gen4(struct brw_codegen *p,
32 vec4_instruction *inst,
33 struct brw_reg dst,
34 struct brw_reg src)
35 {
36 gen4_math(p,
37 dst,
38 brw_math_function(inst->opcode),
39 inst->base_mrf,
40 src,
41 BRW_MATH_PRECISION_FULL);
42 }
43
44 static void
45 check_gen6_math_src_arg(struct brw_reg src)
46 {
47 /* Source swizzles are ignored. */
48 assert(!src.abs);
49 assert(!src.negate);
50 assert(src.swizzle == BRW_SWIZZLE_XYZW);
51 }
52
53 static void
54 generate_math_gen6(struct brw_codegen *p,
55 vec4_instruction *inst,
56 struct brw_reg dst,
57 struct brw_reg src0,
58 struct brw_reg src1)
59 {
60 /* Can't do writemask because math can't be align16. */
61 assert(dst.writemask == WRITEMASK_XYZW);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0);
64 if (src1.file == BRW_GENERAL_REGISTER_FILE)
65 check_gen6_math_src_arg(src1);
66
67 brw_set_default_access_mode(p, BRW_ALIGN_1);
68 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
69 brw_set_default_access_mode(p, BRW_ALIGN_16);
70 }
71
72 static void
73 generate_math2_gen4(struct brw_codegen *p,
74 vec4_instruction *inst,
75 struct brw_reg dst,
76 struct brw_reg src0,
77 struct brw_reg src1)
78 {
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
80 * "Message Payload":
81 *
82 * "Operand0[7]. For the INT DIV functions, this operand is the
83 * denominator."
84 * ...
85 * "Operand1[7]. For the INT DIV functions, this operand is the
86 * numerator."
87 */
88 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
89 struct brw_reg &op0 = is_int_div ? src1 : src0;
90 struct brw_reg &op1 = is_int_div ? src0 : src1;
91
92 brw_push_insn_state(p);
93 brw_set_default_saturate(p, false);
94 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
95 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
96 brw_pop_insn_state(p);
97
98 gen4_math(p,
99 dst,
100 brw_math_function(inst->opcode),
101 inst->base_mrf,
102 op0,
103 BRW_MATH_PRECISION_FULL);
104 }
105
106 static void
107 generate_tex(struct brw_codegen *p,
108 struct brw_vue_prog_data *prog_data,
109 vec4_instruction *inst,
110 struct brw_reg dst,
111 struct brw_reg src,
112 struct brw_reg surface_index,
113 struct brw_reg sampler_index)
114 {
115 const struct brw_device_info *devinfo = p->devinfo;
116 int msg_type = -1;
117
118 if (devinfo->gen >= 5) {
119 switch (inst->opcode) {
120 case SHADER_OPCODE_TEX:
121 case SHADER_OPCODE_TXL:
122 if (inst->shadow_compare) {
123 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
124 } else {
125 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
126 }
127 break;
128 case SHADER_OPCODE_TXD:
129 if (inst->shadow_compare) {
130 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
131 assert(devinfo->gen >= 8 || devinfo->is_haswell);
132 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
133 } else {
134 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
135 }
136 break;
137 case SHADER_OPCODE_TXF:
138 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
139 break;
140 case SHADER_OPCODE_TXF_CMS_W:
141 assert(devinfo->gen >= 9);
142 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
143 break;
144 case SHADER_OPCODE_TXF_CMS:
145 if (devinfo->gen >= 7)
146 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
147 else
148 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
149 break;
150 case SHADER_OPCODE_TXF_MCS:
151 assert(devinfo->gen >= 7);
152 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
153 break;
154 case SHADER_OPCODE_TXS:
155 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
156 break;
157 case SHADER_OPCODE_TG4:
158 if (inst->shadow_compare) {
159 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
160 } else {
161 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
162 }
163 break;
164 case SHADER_OPCODE_TG4_OFFSET:
165 if (inst->shadow_compare) {
166 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
167 } else {
168 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
169 }
170 break;
171 case SHADER_OPCODE_SAMPLEINFO:
172 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
173 break;
174 default:
175 unreachable("should not get here: invalid vec4 texture opcode");
176 }
177 } else {
178 switch (inst->opcode) {
179 case SHADER_OPCODE_TEX:
180 case SHADER_OPCODE_TXL:
181 if (inst->shadow_compare) {
182 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
183 assert(inst->mlen == 3);
184 } else {
185 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
186 assert(inst->mlen == 2);
187 }
188 break;
189 case SHADER_OPCODE_TXD:
190 /* There is no sample_d_c message; comparisons are done manually. */
191 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
192 assert(inst->mlen == 4);
193 break;
194 case SHADER_OPCODE_TXF:
195 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
196 assert(inst->mlen == 2);
197 break;
198 case SHADER_OPCODE_TXS:
199 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
200 assert(inst->mlen == 2);
201 break;
202 default:
203 unreachable("should not get here: invalid vec4 texture opcode");
204 }
205 }
206
207 assert(msg_type != -1);
208
209 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
210
211 /* Load the message header if present. If there's a texture offset, we need
212 * to set it up explicitly and load the offset bitfield. Otherwise, we can
213 * use an implied move from g0 to the first message register.
214 */
215 if (inst->header_size != 0) {
216 if (devinfo->gen < 6 && !inst->offset) {
217 /* Set up an implied move from g0 to the MRF. */
218 src = brw_vec8_grf(0, 0);
219 } else {
220 struct brw_reg header =
221 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
222 uint32_t dw2 = 0;
223
224 /* Explicitly set up the message header by copying g0 to the MRF. */
225 brw_push_insn_state(p);
226 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
227 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
228
229 brw_set_default_access_mode(p, BRW_ALIGN_1);
230
231 if (inst->offset)
232 /* Set the texel offset bits in DWord 2. */
233 dw2 = inst->offset;
234
235 if (devinfo->gen >= 9)
236 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
237 * based on bit 22 in the header.
238 */
239 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
240
241 if (dw2)
242 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
243
244 brw_adjust_sampler_state_pointer(p, header, sampler_index);
245 brw_pop_insn_state(p);
246 }
247 }
248
249 uint32_t return_format;
250
251 switch (dst.type) {
252 case BRW_REGISTER_TYPE_D:
253 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
254 break;
255 case BRW_REGISTER_TYPE_UD:
256 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
257 break;
258 default:
259 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
260 break;
261 }
262
263 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
264 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
265 ? prog_data->base.binding_table.gather_texture_start
266 : prog_data->base.binding_table.texture_start;
267
268 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
269 sampler_index.file == BRW_IMMEDIATE_VALUE) {
270 uint32_t surface = surface_index.ud;
271 uint32_t sampler = sampler_index.ud;
272
273 brw_SAMPLE(p,
274 dst,
275 inst->base_mrf,
276 src,
277 surface + base_binding_table_index,
278 sampler % 16,
279 msg_type,
280 1, /* response length */
281 inst->mlen,
282 inst->header_size != 0,
283 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
284 return_format);
285
286 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
287 } else {
288 /* Non-constant sampler index. */
289
290 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
291 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
292 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
293
294 brw_push_insn_state(p);
295 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
296 brw_set_default_access_mode(p, BRW_ALIGN_1);
297
298 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
299 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
300 } else {
301 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
302 brw_OR(p, addr, addr, surface_reg);
303 }
304 if (base_binding_table_index)
305 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
306 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
307
308 brw_pop_insn_state(p);
309
310 if (inst->base_mrf != -1)
311 gen6_resolve_implied_move(p, &src, inst->base_mrf);
312
313 /* dst = send(offset, a0.0 | <descriptor>) */
314 brw_inst *insn = brw_send_indirect_message(
315 p, BRW_SFID_SAMPLER, dst, src, addr);
316 brw_set_sampler_message(p, insn,
317 0 /* surface */,
318 0 /* sampler */,
319 msg_type,
320 1 /* rlen */,
321 inst->mlen /* mlen */,
322 inst->header_size != 0 /* header */,
323 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
324 return_format);
325
326 /* visitor knows more than we do about the surface limit required,
327 * so has already done marking.
328 */
329 }
330 }
331
332 static void
333 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
334 {
335 brw_urb_WRITE(p,
336 brw_null_reg(), /* dest */
337 inst->base_mrf, /* starting mrf reg nr */
338 brw_vec8_grf(0, 0), /* src */
339 inst->urb_write_flags,
340 inst->mlen,
341 0, /* response len */
342 inst->offset, /* urb destination offset */
343 BRW_URB_SWIZZLE_INTERLEAVE);
344 }
345
346 static void
347 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
348 {
349 struct brw_reg src = brw_message_reg(inst->base_mrf);
350 brw_urb_WRITE(p,
351 brw_null_reg(), /* dest */
352 inst->base_mrf, /* starting mrf reg nr */
353 src,
354 inst->urb_write_flags,
355 inst->mlen,
356 0, /* response len */
357 inst->offset, /* urb destination offset */
358 BRW_URB_SWIZZLE_INTERLEAVE);
359 }
360
361 static void
362 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
363 {
364 struct brw_reg src = brw_message_reg(inst->base_mrf);
365
366 /* We pass the temporary passed in src0 as the writeback register */
367 brw_urb_WRITE(p,
368 inst->src[0].as_brw_reg(), /* dest */
369 inst->base_mrf, /* starting mrf reg nr */
370 src,
371 BRW_URB_WRITE_ALLOCATE_COMPLETE,
372 inst->mlen,
373 1, /* response len */
374 inst->offset, /* urb destination offset */
375 BRW_URB_SWIZZLE_INTERLEAVE);
376
377 /* Now put allocated urb handle in dst.0 */
378 brw_push_insn_state(p);
379 brw_set_default_access_mode(p, BRW_ALIGN_1);
380 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
381 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
382 get_element_ud(inst->src[0].as_brw_reg(), 0));
383 brw_pop_insn_state(p);
384 }
385
386 static void
387 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
388 {
389 struct brw_reg src = brw_message_reg(inst->base_mrf);
390 brw_urb_WRITE(p,
391 brw_null_reg(), /* dest */
392 inst->base_mrf, /* starting mrf reg nr */
393 src,
394 BRW_URB_WRITE_EOT | inst->urb_write_flags,
395 inst->mlen,
396 0, /* response len */
397 0, /* urb destination offset */
398 BRW_URB_SWIZZLE_INTERLEAVE);
399 }
400
401 static void
402 generate_gs_set_write_offset(struct brw_codegen *p,
403 struct brw_reg dst,
404 struct brw_reg src0,
405 struct brw_reg src1)
406 {
407 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
408 * Header: M0.3):
409 *
410 * Slot 0 Offset. This field, after adding to the Global Offset field
411 * in the message descriptor, specifies the offset (in 256-bit units)
412 * from the start of the URB entry, as referenced by URB Handle 0, at
413 * which the data will be accessed.
414 *
415 * Similar text describes DWORD M0.4, which is slot 1 offset.
416 *
417 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
418 * of the register for geometry shader invocations 0 and 1) by the
419 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
420 *
421 * We can do this with the following EU instruction:
422 *
423 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
424 */
425 brw_push_insn_state(p);
426 brw_set_default_access_mode(p, BRW_ALIGN_1);
427 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
428 assert(p->devinfo->gen >= 7 &&
429 src1.file == BRW_IMMEDIATE_VALUE &&
430 src1.type == BRW_REGISTER_TYPE_UD &&
431 src1.ud <= USHRT_MAX);
432 if (src0.file == BRW_IMMEDIATE_VALUE) {
433 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
434 brw_imm_ud(src0.ud * src1.ud));
435 } else {
436 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
437 retype(src1, BRW_REGISTER_TYPE_UW));
438 }
439 brw_pop_insn_state(p);
440 }
441
442 static void
443 generate_gs_set_vertex_count(struct brw_codegen *p,
444 struct brw_reg dst,
445 struct brw_reg src)
446 {
447 brw_push_insn_state(p);
448 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
449
450 if (p->devinfo->gen >= 8) {
451 /* Move the vertex count into the second MRF for the EOT write. */
452 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
453 src);
454 } else {
455 /* If we think of the src and dst registers as composed of 8 DWORDs each,
456 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
457 * them to WORDs, and then pack them into DWORD 2 of dst.
458 *
459 * It's easier to get the EU to do this if we think of the src and dst
460 * registers as composed of 16 WORDS each; then, we want to pick up the
461 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
462 * of dst.
463 *
464 * We can do that by the following EU instruction:
465 *
466 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
467 */
468 brw_set_default_access_mode(p, BRW_ALIGN_1);
469 brw_MOV(p,
470 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
471 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
472 }
473 brw_pop_insn_state(p);
474 }
475
476 static void
477 generate_gs_svb_write(struct brw_codegen *p,
478 struct brw_vue_prog_data *prog_data,
479 vec4_instruction *inst,
480 struct brw_reg dst,
481 struct brw_reg src0,
482 struct brw_reg src1)
483 {
484 int binding = inst->sol_binding;
485 bool final_write = inst->sol_final_write;
486
487 brw_push_insn_state(p);
488 brw_set_default_exec_size(p, BRW_EXECUTE_4);
489 /* Copy Vertex data into M0.x */
490 brw_MOV(p, stride(dst, 4, 4, 1),
491 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
492 brw_pop_insn_state(p);
493
494 brw_push_insn_state(p);
495 /* Send SVB Write */
496 brw_svb_write(p,
497 final_write ? src1 : brw_null_reg(), /* dest == src1 */
498 1, /* msg_reg_nr */
499 dst, /* src0 == previous dst */
500 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
501 final_write); /* send_commit_msg */
502
503 /* Finally, wait for the write commit to occur so that we can proceed to
504 * other things safely.
505 *
506 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
507 *
508 * The write commit does not modify the destination register, but
509 * merely clears the dependency associated with the destination
510 * register. Thus, a simple “mov” instruction using the register as a
511 * source is sufficient to wait for the write commit to occur.
512 */
513 if (final_write) {
514 brw_MOV(p, src1, src1);
515 }
516 brw_pop_insn_state(p);
517 }
518
519 static void
520 generate_gs_svb_set_destination_index(struct brw_codegen *p,
521 vec4_instruction *inst,
522 struct brw_reg dst,
523 struct brw_reg src)
524 {
525 int vertex = inst->sol_vertex;
526 brw_push_insn_state(p);
527 brw_set_default_access_mode(p, BRW_ALIGN_1);
528 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
529 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
530 brw_pop_insn_state(p);
531 }
532
533 static void
534 generate_gs_set_dword_2(struct brw_codegen *p,
535 struct brw_reg dst,
536 struct brw_reg src)
537 {
538 brw_push_insn_state(p);
539 brw_set_default_access_mode(p, BRW_ALIGN_1);
540 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
541 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
542 brw_pop_insn_state(p);
543 }
544
545 static void
546 generate_gs_prepare_channel_masks(struct brw_codegen *p,
547 struct brw_reg dst)
548 {
549 /* We want to left shift just DWORD 4 (the x component belonging to the
550 * second geometry shader invocation) by 4 bits. So generate the
551 * instruction:
552 *
553 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
554 */
555 dst = suboffset(vec1(dst), 4);
556 brw_push_insn_state(p);
557 brw_set_default_access_mode(p, BRW_ALIGN_1);
558 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
559 brw_SHL(p, dst, dst, brw_imm_ud(4));
560 brw_pop_insn_state(p);
561 }
562
563 static void
564 generate_gs_set_channel_masks(struct brw_codegen *p,
565 struct brw_reg dst,
566 struct brw_reg src)
567 {
568 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
569 * Header: M0.5):
570 *
571 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
572 *
573 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
574 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
575 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
576 * channel enable to determine the final channel enable. For the
577 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
578 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
579 * in the writeback message. For the URB_WRITE_OWORD &
580 * URB_WRITE_HWORD messages, when final channel enable is 1 it
581 * indicates that Vertex 1 DATA [3] will be written to the surface.
582 *
583 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
584 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
585 *
586 * 14 Vertex 1 DATA [2] Channel Mask
587 * 13 Vertex 1 DATA [1] Channel Mask
588 * 12 Vertex 1 DATA [0] Channel Mask
589 * 11 Vertex 0 DATA [3] Channel Mask
590 * 10 Vertex 0 DATA [2] Channel Mask
591 * 9 Vertex 0 DATA [1] Channel Mask
592 * 8 Vertex 0 DATA [0] Channel Mask
593 *
594 * (This is from a section of the PRM that is agnostic to the particular
595 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
596 * geometry shader invocations 0 and 1, respectively). Since we have the
597 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
598 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
599 * DWORD 4, we just need to OR them together and store the result in bits
600 * 15:8 of DWORD 5.
601 *
602 * It's easier to get the EU to do this if we think of the src and dst
603 * registers as composed of 32 bytes each; then, we want to pick up the
604 * contents of bytes 0 and 16 from src, OR them together, and store them in
605 * byte 21.
606 *
607 * We can do that by the following EU instruction:
608 *
609 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
610 *
611 * Note: this relies on the source register having zeros in (a) bits 7:4 of
612 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
613 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
614 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
615 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
616 * contain valid channel mask values (which are in the range 0x0-0xf).
617 */
618 dst = retype(dst, BRW_REGISTER_TYPE_UB);
619 src = retype(src, BRW_REGISTER_TYPE_UB);
620 brw_push_insn_state(p);
621 brw_set_default_access_mode(p, BRW_ALIGN_1);
622 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
623 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
624 brw_pop_insn_state(p);
625 }
626
627 static void
628 generate_gs_get_instance_id(struct brw_codegen *p,
629 struct brw_reg dst)
630 {
631 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
632 * and store into dst.0 & dst.4. So generate the instruction:
633 *
634 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
635 */
636 brw_push_insn_state(p);
637 brw_set_default_access_mode(p, BRW_ALIGN_1);
638 dst = retype(dst, BRW_REGISTER_TYPE_UD);
639 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
640 brw_SHR(p, dst, stride(r0, 1, 4, 0),
641 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
642 brw_pop_insn_state(p);
643 }
644
645 static void
646 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
647 struct brw_reg dst,
648 struct brw_reg src0,
649 struct brw_reg src1,
650 struct brw_reg src2)
651 {
652 brw_push_insn_state(p);
653 brw_set_default_access_mode(p, BRW_ALIGN_1);
654 /* Save src0 data in 16:31 bits of dst.0 */
655 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
656 brw_imm_ud(0xffffu));
657 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
658 /* Save src1 data in 0:15 bits of dst.0 */
659 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
660 brw_imm_ud(0xffffu));
661 brw_OR(p, suboffset(vec1(dst), 0),
662 suboffset(vec1(dst), 0),
663 suboffset(vec1(src2), 0));
664 brw_pop_insn_state(p);
665 }
666
667 static void
668 generate_gs_ff_sync(struct brw_codegen *p,
669 vec4_instruction *inst,
670 struct brw_reg dst,
671 struct brw_reg src0,
672 struct brw_reg src1)
673 {
674 /* This opcode uses an implied MRF register for:
675 * - the header of the ff_sync message. And as such it is expected to be
676 * initialized to r0 before calling here.
677 * - the destination where we will write the allocated URB handle.
678 */
679 struct brw_reg header =
680 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
681
682 /* Overwrite dword 0 of the header (SO vertices to write) and
683 * dword 1 (number of primitives written).
684 */
685 brw_push_insn_state(p);
686 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
687 brw_set_default_access_mode(p, BRW_ALIGN_1);
688 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
689 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
690 brw_pop_insn_state(p);
691
692 /* Allocate URB handle in dst */
693 brw_ff_sync(p,
694 dst,
695 0,
696 header,
697 1, /* allocate */
698 1, /* response length */
699 0 /* eot */);
700
701 /* Now put allocated urb handle in header.0 */
702 brw_push_insn_state(p);
703 brw_set_default_access_mode(p, BRW_ALIGN_1);
704 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
705 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
706
707 /* src1 is not an immediate when we use transform feedback */
708 if (src1.file != BRW_IMMEDIATE_VALUE) {
709 brw_set_default_exec_size(p, BRW_EXECUTE_4);
710 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
711 }
712
713 brw_pop_insn_state(p);
714 }
715
716 static void
717 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
718 {
719 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
720 struct brw_reg src = brw_vec8_grf(0, 0);
721 brw_push_insn_state(p);
722 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
723 brw_set_default_access_mode(p, BRW_ALIGN_1);
724 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
725 brw_pop_insn_state(p);
726 }
727
728 static void
729 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
730 {
731 const struct brw_device_info *devinfo = p->devinfo;
732 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
733
734 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
735 *
736 * Since we operate in SIMD4x2 mode, we need run half as many threads
737 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
738 * shift right by one less to accomplish the multiplication by two.
739 */
740 dst = retype(dst, BRW_REGISTER_TYPE_UD);
741 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
742
743 brw_push_insn_state(p);
744 brw_set_default_access_mode(p, BRW_ALIGN_1);
745
746 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
747 const int shift = ivb ? 16 : 17;
748
749 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
750 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
751 brw_imm_ud(shift - 1));
752 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
753
754 brw_pop_insn_state(p);
755 }
756
757 static void
758 generate_tcs_urb_write(struct brw_codegen *p,
759 vec4_instruction *inst,
760 struct brw_reg urb_header)
761 {
762 const struct brw_device_info *devinfo = p->devinfo;
763
764 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
765 brw_set_dest(p, send, brw_null_reg());
766 brw_set_src0(p, send, urb_header);
767
768 brw_set_message_descriptor(p, send, BRW_SFID_URB,
769 inst->mlen /* mlen */, 0 /* rlen */,
770 true /* header */, false /* eot */);
771 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
772 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
773 if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
774 brw_inst_set_eot(devinfo, send, 1);
775 } else {
776 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
777 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
778 }
779
780 /* what happens to swizzles? */
781 }
782
783
784 static void
785 generate_tcs_input_urb_offsets(struct brw_codegen *p,
786 struct brw_reg dst,
787 struct brw_reg vertex,
788 struct brw_reg offset)
789 {
790 /* Generates an URB read/write message header for HS/DS operation.
791 * Inputs are a vertex index, and a byte offset from the beginning of
792 * the vertex. */
793
794 /* If `vertex` is not an immediate, we clobber a0.0 */
795
796 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
797 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
798
799 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
800
801 brw_push_insn_state(p);
802 brw_set_default_access_mode(p, BRW_ALIGN_1);
803 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
804 brw_MOV(p, dst, brw_imm_ud(0));
805
806 /* m0.5 bits 8-15 are channel enables */
807 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
808
809 /* m0.0-0.1: URB handles */
810 if (vertex.file == BRW_IMMEDIATE_VALUE) {
811 uint32_t vertex_index = vertex.ud;
812 struct brw_reg index_reg = brw_vec1_grf(
813 1 + (vertex_index >> 3), vertex_index & 7);
814
815 brw_MOV(p, vec2(get_element_ud(dst, 0)),
816 retype(index_reg, BRW_REGISTER_TYPE_UD));
817 } else {
818 /* Use indirect addressing. ICP Handles are DWords (single channels
819 * of a register) and start at g1.0.
820 *
821 * In order to start our region at g1.0, we add 8 to the vertex index,
822 * effectively skipping over the 8 channels in g0.0. This gives us a
823 * DWord offset to the ICP Handle.
824 *
825 * Indirect addressing works in terms of bytes, so we then multiply
826 * the DWord offset by 4 (by shifting left by 2).
827 */
828 struct brw_reg addr = brw_address_reg(0);
829
830 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
831 brw_ADD(p, addr, get_element_ud(vertex, 0), brw_imm_uw(0x8));
832 brw_SHL(p, addr, addr, brw_imm_ud(2));
833 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
834
835 /* top half: m0.1 = g[1.0 + vertex.4]UD */
836 brw_ADD(p, addr, get_element_ud(vertex, 4), brw_imm_uw(0x8));
837 brw_SHL(p, addr, addr, brw_imm_ud(2));
838 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
839 }
840
841 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
842 if (offset.file != ARF)
843 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
844
845 brw_pop_insn_state(p);
846 }
847
848
849 static void
850 generate_tcs_output_urb_offsets(struct brw_codegen *p,
851 struct brw_reg dst,
852 struct brw_reg write_mask,
853 struct brw_reg offset)
854 {
855 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
856 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
857
858 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
859 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
860
861 brw_push_insn_state(p);
862
863 brw_set_default_access_mode(p, BRW_ALIGN_1);
864 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
865 brw_MOV(p, dst, brw_imm_ud(0));
866
867 unsigned mask = write_mask.ud;
868
869 /* m0.5 bits 15:12 and 11:8 are channel enables */
870 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
871
872 /* HS patch URB handle is delivered in r0.0 */
873 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
874
875 /* m0.0-0.1: URB handles */
876 brw_MOV(p, vec2(get_element_ud(dst, 0)),
877 retype(urb_handle, BRW_REGISTER_TYPE_UD));
878
879 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
880 if (offset.file != ARF)
881 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
882
883 brw_pop_insn_state(p);
884 }
885
886 static void
887 generate_tes_create_input_read_header(struct brw_codegen *p,
888 struct brw_reg dst)
889 {
890 brw_push_insn_state(p);
891 brw_set_default_access_mode(p, BRW_ALIGN_1);
892 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
893
894 /* Initialize the register to 0 */
895 brw_MOV(p, dst, brw_imm_ud(0));
896
897 /* Enable all the channels in m0.5 bits 15:8 */
898 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
899
900 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
901 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
902 */
903 brw_AND(p, vec2(get_element_ud(dst, 0)),
904 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
905 brw_imm_ud(0x1fff));
906 brw_pop_insn_state(p);
907 }
908
909 static void
910 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
911 struct brw_reg dst,
912 struct brw_reg header,
913 struct brw_reg offset)
914 {
915 brw_push_insn_state(p);
916 brw_set_default_access_mode(p, BRW_ALIGN_1);
917 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
918
919 brw_MOV(p, dst, header);
920 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
921 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
922
923 brw_pop_insn_state(p);
924 }
925
926 static void
927 generate_vec4_urb_read(struct brw_codegen *p,
928 vec4_instruction *inst,
929 struct brw_reg dst,
930 struct brw_reg header)
931 {
932 const struct brw_device_info *devinfo = p->devinfo;
933
934 assert(header.file == BRW_GENERAL_REGISTER_FILE);
935 assert(header.type == BRW_REGISTER_TYPE_UD);
936
937 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
938 brw_set_dest(p, send, dst);
939 brw_set_src0(p, send, header);
940
941 brw_set_message_descriptor(p, send, BRW_SFID_URB,
942 1 /* mlen */, 1 /* rlen */,
943 true /* header */, false /* eot */);
944 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
945 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
946 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
947
948 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
949 }
950
951 static void
952 generate_tcs_release_input(struct brw_codegen *p,
953 struct brw_reg header,
954 struct brw_reg vertex,
955 struct brw_reg is_unpaired)
956 {
957 const struct brw_device_info *devinfo = p->devinfo;
958
959 assert(vertex.file == BRW_IMMEDIATE_VALUE);
960 assert(vertex.type == BRW_REGISTER_TYPE_UD);
961
962 /* m0.0-0.1: URB handles */
963 struct brw_reg urb_handles =
964 retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
965 BRW_REGISTER_TYPE_UD);
966
967 brw_push_insn_state(p);
968 brw_set_default_access_mode(p, BRW_ALIGN_1);
969 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
970 brw_MOV(p, header, brw_imm_ud(0));
971 brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
972 brw_pop_insn_state(p);
973
974 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
975 brw_set_dest(p, send, brw_null_reg());
976 brw_set_src0(p, send, header);
977 brw_set_message_descriptor(p, send, BRW_SFID_URB,
978 1 /* mlen */, 0 /* rlen */,
979 true /* header */, false /* eot */);
980 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
981 brw_inst_set_urb_complete(devinfo, send, 1);
982 brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
983 BRW_URB_SWIZZLE_NONE :
984 BRW_URB_SWIZZLE_INTERLEAVE);
985 }
986
987 static void
988 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
989 {
990 struct brw_reg header = brw_message_reg(inst->base_mrf);
991
992 brw_push_insn_state(p);
993 brw_set_default_access_mode(p, BRW_ALIGN_1);
994 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
995 brw_MOV(p, header, brw_imm_ud(0));
996 brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
997 brw_MOV(p, get_element_ud(header, 0),
998 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
999 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
1000 brw_pop_insn_state(p);
1001
1002 brw_urb_WRITE(p,
1003 brw_null_reg(), /* dest */
1004 inst->base_mrf, /* starting mrf reg nr */
1005 header,
1006 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
1007 BRW_URB_WRITE_USE_CHANNEL_MASKS,
1008 inst->mlen,
1009 0, /* response len */
1010 0, /* urb destination offset */
1011 0);
1012 }
1013
1014 static void
1015 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1016 {
1017 brw_push_insn_state(p);
1018 brw_set_default_access_mode(p, BRW_ALIGN_1);
1019 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
1020 brw_pop_insn_state(p);
1021 }
1022
1023 static void
1024 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1025 {
1026 brw_push_insn_state(p);
1027 brw_set_default_access_mode(p, BRW_ALIGN_1);
1028 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
1029 brw_pop_insn_state(p);
1030 }
1031
1032 static void
1033 generate_tcs_create_barrier_header(struct brw_codegen *p,
1034 struct brw_vue_prog_data *prog_data,
1035 struct brw_reg dst)
1036 {
1037 const struct brw_device_info *devinfo = p->devinfo;
1038 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
1039 struct brw_reg m0_2 = get_element_ud(dst, 2);
1040 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
1041
1042 brw_push_insn_state(p);
1043 brw_set_default_access_mode(p, BRW_ALIGN_1);
1044 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1045
1046 /* Zero the message header */
1047 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
1048
1049 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1050 brw_AND(p, m0_2,
1051 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
1052 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1053
1054 /* Shift it up to bits 27:24. */
1055 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
1056
1057 /* Set the Barrier Count and the enable bit */
1058 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
1059
1060 brw_pop_insn_state(p);
1061 }
1062
1063 static void
1064 generate_oword_dual_block_offsets(struct brw_codegen *p,
1065 struct brw_reg m1,
1066 struct brw_reg index)
1067 {
1068 int second_vertex_offset;
1069
1070 if (p->devinfo->gen >= 6)
1071 second_vertex_offset = 1;
1072 else
1073 second_vertex_offset = 16;
1074
1075 m1 = retype(m1, BRW_REGISTER_TYPE_D);
1076
1077 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1078 * M1.4 are used, and the rest are ignored.
1079 */
1080 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1081 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1082 struct brw_reg index_0 = suboffset(vec1(index), 0);
1083 struct brw_reg index_4 = suboffset(vec1(index), 4);
1084
1085 brw_push_insn_state(p);
1086 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1087 brw_set_default_access_mode(p, BRW_ALIGN_1);
1088
1089 brw_MOV(p, m1_0, index_0);
1090
1091 if (index.file == BRW_IMMEDIATE_VALUE) {
1092 index_4.ud += second_vertex_offset;
1093 brw_MOV(p, m1_4, index_4);
1094 } else {
1095 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1096 }
1097
1098 brw_pop_insn_state(p);
1099 }
1100
1101 static void
1102 generate_unpack_flags(struct brw_codegen *p,
1103 struct brw_reg dst)
1104 {
1105 brw_push_insn_state(p);
1106 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1107 brw_set_default_access_mode(p, BRW_ALIGN_1);
1108
1109 struct brw_reg flags = brw_flag_reg(0, 0);
1110 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1111 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1112
1113 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1114 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1115 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1116
1117 brw_pop_insn_state(p);
1118 }
1119
1120 static void
1121 generate_scratch_read(struct brw_codegen *p,
1122 vec4_instruction *inst,
1123 struct brw_reg dst,
1124 struct brw_reg index)
1125 {
1126 const struct brw_device_info *devinfo = p->devinfo;
1127 struct brw_reg header = brw_vec8_grf(0, 0);
1128
1129 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1130
1131 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1132 index);
1133
1134 uint32_t msg_type;
1135
1136 if (devinfo->gen >= 6)
1137 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1138 else if (devinfo->gen == 5 || devinfo->is_g4x)
1139 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1140 else
1141 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1142
1143 /* Each of the 8 channel enables is considered for whether each
1144 * dword is written.
1145 */
1146 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1147 brw_set_dest(p, send, dst);
1148 brw_set_src0(p, send, header);
1149 if (devinfo->gen < 6)
1150 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1151 brw_set_dp_read_message(p, send,
1152 brw_scratch_surface_idx(p),
1153 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1154 msg_type,
1155 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
1156 2, /* mlen */
1157 true, /* header_present */
1158 1 /* rlen */);
1159 }
1160
1161 static void
1162 generate_scratch_write(struct brw_codegen *p,
1163 vec4_instruction *inst,
1164 struct brw_reg dst,
1165 struct brw_reg src,
1166 struct brw_reg index)
1167 {
1168 const struct brw_device_info *devinfo = p->devinfo;
1169 struct brw_reg header = brw_vec8_grf(0, 0);
1170 bool write_commit;
1171
1172 /* If the instruction is predicated, we'll predicate the send, not
1173 * the header setup.
1174 */
1175 brw_set_default_predicate_control(p, false);
1176
1177 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1178
1179 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1180 index);
1181
1182 brw_MOV(p,
1183 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1184 retype(src, BRW_REGISTER_TYPE_D));
1185
1186 uint32_t msg_type;
1187
1188 if (devinfo->gen >= 7)
1189 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1190 else if (devinfo->gen == 6)
1191 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1192 else
1193 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1194
1195 brw_set_default_predicate_control(p, inst->predicate);
1196
1197 /* Pre-gen6, we have to specify write commits to ensure ordering
1198 * between reads and writes within a thread. Afterwards, that's
1199 * guaranteed and write commits only matter for inter-thread
1200 * synchronization.
1201 */
1202 if (devinfo->gen >= 6) {
1203 write_commit = false;
1204 } else {
1205 /* The visitor set up our destination register to be g0. This
1206 * means that when the next read comes along, we will end up
1207 * reading from g0 and causing a block on the write commit. For
1208 * write-after-read, we are relying on the value of the previous
1209 * read being used (and thus blocking on completion) before our
1210 * write is executed. This means we have to be careful in
1211 * instruction scheduling to not violate this assumption.
1212 */
1213 write_commit = true;
1214 }
1215
1216 /* Each of the 8 channel enables is considered for whether each
1217 * dword is written.
1218 */
1219 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1220 brw_set_dest(p, send, dst);
1221 brw_set_src0(p, send, header);
1222 if (devinfo->gen < 6)
1223 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1224 brw_set_dp_write_message(p, send,
1225 brw_scratch_surface_idx(p),
1226 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1227 msg_type,
1228 3, /* mlen */
1229 true, /* header present */
1230 false, /* not a render target write */
1231 write_commit, /* rlen */
1232 false, /* eot */
1233 write_commit);
1234 }
1235
1236 static void
1237 generate_pull_constant_load(struct brw_codegen *p,
1238 struct brw_vue_prog_data *prog_data,
1239 vec4_instruction *inst,
1240 struct brw_reg dst,
1241 struct brw_reg index,
1242 struct brw_reg offset)
1243 {
1244 const struct brw_device_info *devinfo = p->devinfo;
1245 assert(index.file == BRW_IMMEDIATE_VALUE &&
1246 index.type == BRW_REGISTER_TYPE_UD);
1247 uint32_t surf_index = index.ud;
1248
1249 struct brw_reg header = brw_vec8_grf(0, 0);
1250
1251 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1252
1253 if (devinfo->gen >= 6) {
1254 if (offset.file == BRW_IMMEDIATE_VALUE) {
1255 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1256 BRW_REGISTER_TYPE_D),
1257 brw_imm_d(offset.ud >> 4));
1258 } else {
1259 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1260 BRW_REGISTER_TYPE_D),
1261 offset, brw_imm_d(4));
1262 }
1263 } else {
1264 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1265 BRW_REGISTER_TYPE_D),
1266 offset);
1267 }
1268
1269 uint32_t msg_type;
1270
1271 if (devinfo->gen >= 6)
1272 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1273 else if (devinfo->gen == 5 || devinfo->is_g4x)
1274 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1275 else
1276 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1277
1278 /* Each of the 8 channel enables is considered for whether each
1279 * dword is written.
1280 */
1281 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1282 brw_set_dest(p, send, dst);
1283 brw_set_src0(p, send, header);
1284 if (devinfo->gen < 6)
1285 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1286 brw_set_dp_read_message(p, send,
1287 surf_index,
1288 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1289 msg_type,
1290 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1291 2, /* mlen */
1292 true, /* header_present */
1293 1 /* rlen */);
1294 }
1295
1296 static void
1297 generate_get_buffer_size(struct brw_codegen *p,
1298 struct brw_vue_prog_data *prog_data,
1299 vec4_instruction *inst,
1300 struct brw_reg dst,
1301 struct brw_reg src,
1302 struct brw_reg surf_index)
1303 {
1304 assert(p->devinfo->gen >= 7);
1305 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1306 surf_index.file == BRW_IMMEDIATE_VALUE);
1307
1308 brw_SAMPLE(p,
1309 dst,
1310 inst->base_mrf,
1311 src,
1312 surf_index.ud,
1313 0,
1314 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1315 1, /* response length */
1316 inst->mlen,
1317 inst->header_size > 0,
1318 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1319 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1320
1321 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1322 }
1323
1324 static void
1325 generate_pull_constant_load_gen7(struct brw_codegen *p,
1326 struct brw_vue_prog_data *prog_data,
1327 vec4_instruction *inst,
1328 struct brw_reg dst,
1329 struct brw_reg surf_index,
1330 struct brw_reg offset)
1331 {
1332 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1333
1334 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1335
1336 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1337 brw_set_dest(p, insn, dst);
1338 brw_set_src0(p, insn, offset);
1339 brw_set_sampler_message(p, insn,
1340 surf_index.ud,
1341 0, /* LD message ignores sampler unit */
1342 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1343 1, /* rlen */
1344 inst->mlen,
1345 inst->header_size != 0,
1346 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1347 0);
1348
1349 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1350
1351 } else {
1352
1353 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1354
1355 brw_push_insn_state(p);
1356 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1357 brw_set_default_access_mode(p, BRW_ALIGN_1);
1358
1359 /* a0.0 = surf_index & 0xff */
1360 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1361 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1362 brw_set_dest(p, insn_and, addr);
1363 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1364 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1365
1366 brw_pop_insn_state(p);
1367
1368 /* dst = send(offset, a0.0 | <descriptor>) */
1369 brw_inst *insn = brw_send_indirect_message(
1370 p, BRW_SFID_SAMPLER, dst, offset, addr);
1371 brw_set_sampler_message(p, insn,
1372 0 /* surface */,
1373 0 /* sampler */,
1374 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1375 1 /* rlen */,
1376 inst->mlen,
1377 inst->header_size != 0,
1378 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1379 0);
1380 }
1381 }
1382
1383 static void
1384 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1385 vec4_instruction *inst,
1386 struct brw_reg dst)
1387 {
1388 brw_push_insn_state(p);
1389 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1390
1391 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1392 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1393
1394 brw_set_default_access_mode(p, BRW_ALIGN_1);
1395 brw_MOV(p, get_element_ud(dst, 2),
1396 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1397
1398 brw_pop_insn_state(p);
1399 }
1400
1401 static void
1402 generate_mov_indirect(struct brw_codegen *p,
1403 vec4_instruction *inst,
1404 struct brw_reg dst, struct brw_reg reg,
1405 struct brw_reg indirect, struct brw_reg length)
1406 {
1407 assert(indirect.type == BRW_REGISTER_TYPE_UD);
1408
1409 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1410
1411 /* This instruction acts in align1 mode */
1412 assert(inst->force_writemask_all || reg.writemask == 0xf);
1413
1414 brw_push_insn_state(p);
1415 brw_set_default_access_mode(p, BRW_ALIGN_1);
1416 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1417
1418 struct brw_reg addr = vec2(brw_address_reg(0));
1419
1420 /* We need to move the indirect value into the address register. In order
1421 * to make things make some sense, we want to respect at least the X
1422 * component of the swizzle. In order to do that, we need to convert the
1423 * subnr (probably 0) to an align1 subnr and add in the swizzle. We then
1424 * use a region of <8,4,0>:uw to pick off the first 2 bytes of the indirect
1425 * and splat it out to all four channels of the given half of a0.
1426 */
1427 assert(brw_is_single_value_swizzle(indirect.swizzle));
1428 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0)) * 2;
1429 indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
1430
1431 brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
1432
1433 /* Use a <4,1> region Vx1 region*/
1434 struct brw_reg src = brw_VxH_indirect(0, 0);
1435 src.width = BRW_WIDTH_4;
1436 src.hstride = BRW_HORIZONTAL_STRIDE_1;
1437
1438 brw_MOV(p, dst, retype(src, reg.type));
1439
1440 brw_pop_insn_state(p);
1441 }
1442
1443 static void
1444 generate_code(struct brw_codegen *p,
1445 const struct brw_compiler *compiler,
1446 void *log_data,
1447 const nir_shader *nir,
1448 struct brw_vue_prog_data *prog_data,
1449 const struct cfg_t *cfg)
1450 {
1451 const struct brw_device_info *devinfo = p->devinfo;
1452 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
1453 bool debug_flag = INTEL_DEBUG &
1454 intel_debug_flag_for_shader_stage(nir->stage);
1455 struct annotation_info annotation;
1456 memset(&annotation, 0, sizeof(annotation));
1457 int loop_count = 0;
1458
1459 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1460 struct brw_reg src[3], dst;
1461
1462 if (unlikely(debug_flag))
1463 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1464
1465 for (unsigned int i = 0; i < 3; i++) {
1466 src[i] = inst->src[i].as_brw_reg();
1467 }
1468 dst = inst->dst.as_brw_reg();
1469
1470 brw_set_default_predicate_control(p, inst->predicate);
1471 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1472 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1473 brw_set_default_saturate(p, inst->saturate);
1474 brw_set_default_mask_control(p, inst->force_writemask_all);
1475 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1476
1477 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1478 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1479
1480 unsigned pre_emit_nr_insn = p->nr_insn;
1481 bool fix_exec_size = false;
1482
1483 if (dst.width == BRW_WIDTH_4) {
1484 /* This happens in attribute fixups for "dual instanced" geometry
1485 * shaders, since they use attributes that are vec4's. Since the exec
1486 * width is only 4, it's essential that the caller set
1487 * force_writemask_all in order to make sure the instruction is executed
1488 * regardless of which channels are enabled.
1489 */
1490 assert(inst->force_writemask_all);
1491
1492 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1493 * the following register region restrictions (from Graphics BSpec:
1494 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1495 * > Register Region Restrictions)
1496 *
1497 * 1. ExecSize must be greater than or equal to Width.
1498 *
1499 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1500 * to Width * HorzStride."
1501 */
1502 for (int i = 0; i < 3; i++) {
1503 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1504 src[i] = stride(src[i], 4, 4, 1);
1505 }
1506 brw_set_default_exec_size(p, BRW_EXECUTE_4);
1507 fix_exec_size = true;
1508 }
1509
1510 switch (inst->opcode) {
1511 case VEC4_OPCODE_UNPACK_UNIFORM:
1512 case BRW_OPCODE_MOV:
1513 brw_MOV(p, dst, src[0]);
1514 break;
1515 case BRW_OPCODE_ADD:
1516 brw_ADD(p, dst, src[0], src[1]);
1517 break;
1518 case BRW_OPCODE_MUL:
1519 brw_MUL(p, dst, src[0], src[1]);
1520 break;
1521 case BRW_OPCODE_MACH:
1522 brw_MACH(p, dst, src[0], src[1]);
1523 break;
1524
1525 case BRW_OPCODE_MAD:
1526 assert(devinfo->gen >= 6);
1527 brw_MAD(p, dst, src[0], src[1], src[2]);
1528 break;
1529
1530 case BRW_OPCODE_FRC:
1531 brw_FRC(p, dst, src[0]);
1532 break;
1533 case BRW_OPCODE_RNDD:
1534 brw_RNDD(p, dst, src[0]);
1535 break;
1536 case BRW_OPCODE_RNDE:
1537 brw_RNDE(p, dst, src[0]);
1538 break;
1539 case BRW_OPCODE_RNDZ:
1540 brw_RNDZ(p, dst, src[0]);
1541 break;
1542
1543 case BRW_OPCODE_AND:
1544 brw_AND(p, dst, src[0], src[1]);
1545 break;
1546 case BRW_OPCODE_OR:
1547 brw_OR(p, dst, src[0], src[1]);
1548 break;
1549 case BRW_OPCODE_XOR:
1550 brw_XOR(p, dst, src[0], src[1]);
1551 break;
1552 case BRW_OPCODE_NOT:
1553 brw_NOT(p, dst, src[0]);
1554 break;
1555 case BRW_OPCODE_ASR:
1556 brw_ASR(p, dst, src[0], src[1]);
1557 break;
1558 case BRW_OPCODE_SHR:
1559 brw_SHR(p, dst, src[0], src[1]);
1560 break;
1561 case BRW_OPCODE_SHL:
1562 brw_SHL(p, dst, src[0], src[1]);
1563 break;
1564
1565 case BRW_OPCODE_CMP:
1566 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1567 break;
1568 case BRW_OPCODE_SEL:
1569 brw_SEL(p, dst, src[0], src[1]);
1570 break;
1571
1572 case BRW_OPCODE_DPH:
1573 brw_DPH(p, dst, src[0], src[1]);
1574 break;
1575
1576 case BRW_OPCODE_DP4:
1577 brw_DP4(p, dst, src[0], src[1]);
1578 break;
1579
1580 case BRW_OPCODE_DP3:
1581 brw_DP3(p, dst, src[0], src[1]);
1582 break;
1583
1584 case BRW_OPCODE_DP2:
1585 brw_DP2(p, dst, src[0], src[1]);
1586 break;
1587
1588 case BRW_OPCODE_F32TO16:
1589 assert(devinfo->gen >= 7);
1590 brw_F32TO16(p, dst, src[0]);
1591 break;
1592
1593 case BRW_OPCODE_F16TO32:
1594 assert(devinfo->gen >= 7);
1595 brw_F16TO32(p, dst, src[0]);
1596 break;
1597
1598 case BRW_OPCODE_LRP:
1599 assert(devinfo->gen >= 6);
1600 brw_LRP(p, dst, src[0], src[1], src[2]);
1601 break;
1602
1603 case BRW_OPCODE_BFREV:
1604 assert(devinfo->gen >= 7);
1605 /* BFREV only supports UD type for src and dst. */
1606 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1607 retype(src[0], BRW_REGISTER_TYPE_UD));
1608 break;
1609 case BRW_OPCODE_FBH:
1610 assert(devinfo->gen >= 7);
1611 /* FBH only supports UD type for dst. */
1612 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1613 break;
1614 case BRW_OPCODE_FBL:
1615 assert(devinfo->gen >= 7);
1616 /* FBL only supports UD type for dst. */
1617 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1618 break;
1619 case BRW_OPCODE_CBIT:
1620 assert(devinfo->gen >= 7);
1621 /* CBIT only supports UD type for dst. */
1622 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1623 break;
1624 case BRW_OPCODE_ADDC:
1625 assert(devinfo->gen >= 7);
1626 brw_ADDC(p, dst, src[0], src[1]);
1627 break;
1628 case BRW_OPCODE_SUBB:
1629 assert(devinfo->gen >= 7);
1630 brw_SUBB(p, dst, src[0], src[1]);
1631 break;
1632 case BRW_OPCODE_MAC:
1633 brw_MAC(p, dst, src[0], src[1]);
1634 break;
1635
1636 case BRW_OPCODE_BFE:
1637 assert(devinfo->gen >= 7);
1638 brw_BFE(p, dst, src[0], src[1], src[2]);
1639 break;
1640
1641 case BRW_OPCODE_BFI1:
1642 assert(devinfo->gen >= 7);
1643 brw_BFI1(p, dst, src[0], src[1]);
1644 break;
1645 case BRW_OPCODE_BFI2:
1646 assert(devinfo->gen >= 7);
1647 brw_BFI2(p, dst, src[0], src[1], src[2]);
1648 break;
1649
1650 case BRW_OPCODE_IF:
1651 if (!inst->src[0].is_null()) {
1652 /* The instruction has an embedded compare (only allowed on gen6) */
1653 assert(devinfo->gen == 6);
1654 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1655 } else {
1656 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1657 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1658 }
1659 break;
1660
1661 case BRW_OPCODE_ELSE:
1662 brw_ELSE(p);
1663 break;
1664 case BRW_OPCODE_ENDIF:
1665 brw_ENDIF(p);
1666 break;
1667
1668 case BRW_OPCODE_DO:
1669 brw_DO(p, BRW_EXECUTE_8);
1670 break;
1671
1672 case BRW_OPCODE_BREAK:
1673 brw_BREAK(p);
1674 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1675 break;
1676 case BRW_OPCODE_CONTINUE:
1677 brw_CONT(p);
1678 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1679 break;
1680
1681 case BRW_OPCODE_WHILE:
1682 brw_WHILE(p);
1683 loop_count++;
1684 break;
1685
1686 case SHADER_OPCODE_RCP:
1687 case SHADER_OPCODE_RSQ:
1688 case SHADER_OPCODE_SQRT:
1689 case SHADER_OPCODE_EXP2:
1690 case SHADER_OPCODE_LOG2:
1691 case SHADER_OPCODE_SIN:
1692 case SHADER_OPCODE_COS:
1693 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1694 if (devinfo->gen >= 7) {
1695 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1696 brw_null_reg());
1697 } else if (devinfo->gen == 6) {
1698 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1699 } else {
1700 generate_math1_gen4(p, inst, dst, src[0]);
1701 }
1702 break;
1703
1704 case SHADER_OPCODE_POW:
1705 case SHADER_OPCODE_INT_QUOTIENT:
1706 case SHADER_OPCODE_INT_REMAINDER:
1707 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1708 if (devinfo->gen >= 7) {
1709 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1710 } else if (devinfo->gen == 6) {
1711 generate_math_gen6(p, inst, dst, src[0], src[1]);
1712 } else {
1713 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1714 }
1715 break;
1716
1717 case SHADER_OPCODE_TEX:
1718 case SHADER_OPCODE_TXD:
1719 case SHADER_OPCODE_TXF:
1720 case SHADER_OPCODE_TXF_CMS:
1721 case SHADER_OPCODE_TXF_CMS_W:
1722 case SHADER_OPCODE_TXF_MCS:
1723 case SHADER_OPCODE_TXL:
1724 case SHADER_OPCODE_TXS:
1725 case SHADER_OPCODE_TG4:
1726 case SHADER_OPCODE_TG4_OFFSET:
1727 case SHADER_OPCODE_SAMPLEINFO:
1728 generate_tex(p, prog_data, inst, dst, src[0], src[1], src[2]);
1729 break;
1730
1731 case VS_OPCODE_URB_WRITE:
1732 generate_vs_urb_write(p, inst);
1733 break;
1734
1735 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1736 generate_scratch_read(p, inst, dst, src[0]);
1737 break;
1738
1739 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1740 generate_scratch_write(p, inst, dst, src[0], src[1]);
1741 break;
1742
1743 case VS_OPCODE_PULL_CONSTANT_LOAD:
1744 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1745 break;
1746
1747 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1748 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1749 break;
1750
1751 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1752 generate_set_simd4x2_header_gen9(p, inst, dst);
1753 break;
1754
1755
1756 case VS_OPCODE_GET_BUFFER_SIZE:
1757 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1758 break;
1759
1760 case GS_OPCODE_URB_WRITE:
1761 generate_gs_urb_write(p, inst);
1762 break;
1763
1764 case GS_OPCODE_URB_WRITE_ALLOCATE:
1765 generate_gs_urb_write_allocate(p, inst);
1766 break;
1767
1768 case GS_OPCODE_SVB_WRITE:
1769 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1770 break;
1771
1772 case GS_OPCODE_SVB_SET_DST_INDEX:
1773 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1774 break;
1775
1776 case GS_OPCODE_THREAD_END:
1777 generate_gs_thread_end(p, inst);
1778 break;
1779
1780 case GS_OPCODE_SET_WRITE_OFFSET:
1781 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1782 break;
1783
1784 case GS_OPCODE_SET_VERTEX_COUNT:
1785 generate_gs_set_vertex_count(p, dst, src[0]);
1786 break;
1787
1788 case GS_OPCODE_FF_SYNC:
1789 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1790 break;
1791
1792 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1793 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1794 break;
1795
1796 case GS_OPCODE_SET_PRIMITIVE_ID:
1797 generate_gs_set_primitive_id(p, dst);
1798 break;
1799
1800 case GS_OPCODE_SET_DWORD_2:
1801 generate_gs_set_dword_2(p, dst, src[0]);
1802 break;
1803
1804 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1805 generate_gs_prepare_channel_masks(p, dst);
1806 break;
1807
1808 case GS_OPCODE_SET_CHANNEL_MASKS:
1809 generate_gs_set_channel_masks(p, dst, src[0]);
1810 break;
1811
1812 case GS_OPCODE_GET_INSTANCE_ID:
1813 generate_gs_get_instance_id(p, dst);
1814 break;
1815
1816 case SHADER_OPCODE_SHADER_TIME_ADD:
1817 brw_shader_time_add(p, src[0],
1818 prog_data->base.binding_table.shader_time_start);
1819 brw_mark_surface_used(&prog_data->base,
1820 prog_data->base.binding_table.shader_time_start);
1821 break;
1822
1823 case SHADER_OPCODE_UNTYPED_ATOMIC:
1824 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1825 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1826 !inst->dst.is_null());
1827 break;
1828
1829 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1830 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1831 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1832 src[2].ud);
1833 break;
1834
1835 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1836 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1837 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1838 src[2].ud);
1839 break;
1840
1841 case SHADER_OPCODE_TYPED_ATOMIC:
1842 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1843 brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1844 !inst->dst.is_null());
1845 break;
1846
1847 case SHADER_OPCODE_TYPED_SURFACE_READ:
1848 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1849 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1850 src[2].ud);
1851 break;
1852
1853 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1854 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1855 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1856 src[2].ud);
1857 break;
1858
1859 case SHADER_OPCODE_MEMORY_FENCE:
1860 brw_memory_fence(p, dst);
1861 break;
1862
1863 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1864 brw_find_live_channel(p, dst);
1865 break;
1866
1867 case SHADER_OPCODE_BROADCAST:
1868 brw_broadcast(p, dst, src[0], src[1]);
1869 break;
1870
1871 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1872 generate_unpack_flags(p, dst);
1873 break;
1874
1875 case VEC4_OPCODE_MOV_BYTES: {
1876 /* Moves the low byte from each channel, using an Align1 access mode
1877 * and a <4,1,0> source region.
1878 */
1879 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1880 src[0].type == BRW_REGISTER_TYPE_B);
1881
1882 brw_set_default_access_mode(p, BRW_ALIGN_1);
1883 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1884 src[0].width = BRW_WIDTH_1;
1885 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1886 brw_MOV(p, dst, src[0]);
1887 brw_set_default_access_mode(p, BRW_ALIGN_16);
1888 break;
1889 }
1890
1891 case VEC4_OPCODE_PACK_BYTES: {
1892 /* Is effectively:
1893 *
1894 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1895 *
1896 * but destinations' only regioning is horizontal stride, so instead we
1897 * have to use two instructions:
1898 *
1899 * mov(4) dst<1>:UB src<4,1,0>:UB
1900 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1901 *
1902 * where they pack the four bytes from the low and high four DW.
1903 */
1904 assert(_mesa_is_pow_two(dst.writemask) &&
1905 dst.writemask != 0);
1906 unsigned offset = __builtin_ctz(dst.writemask);
1907
1908 dst.type = BRW_REGISTER_TYPE_UB;
1909
1910 brw_set_default_access_mode(p, BRW_ALIGN_1);
1911
1912 src[0].type = BRW_REGISTER_TYPE_UB;
1913 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1914 src[0].width = BRW_WIDTH_1;
1915 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1916 dst.subnr = offset * 4;
1917 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1918 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1919 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
1920 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
1921
1922 src[0].subnr = 16;
1923 dst.subnr = 16 + offset * 4;
1924 insn = brw_MOV(p, dst, src[0]);
1925 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
1926 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
1927 brw_inst_set_no_dd_check(p->devinfo, insn, true);
1928
1929 brw_set_default_access_mode(p, BRW_ALIGN_16);
1930 break;
1931 }
1932
1933 case TCS_OPCODE_URB_WRITE:
1934 generate_tcs_urb_write(p, inst, src[0]);
1935 break;
1936
1937 case VEC4_OPCODE_URB_READ:
1938 generate_vec4_urb_read(p, inst, dst, src[0]);
1939 break;
1940
1941 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
1942 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
1943 break;
1944
1945 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
1946 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
1947 break;
1948
1949 case TCS_OPCODE_GET_INSTANCE_ID:
1950 generate_tcs_get_instance_id(p, dst);
1951 break;
1952
1953 case TCS_OPCODE_GET_PRIMITIVE_ID:
1954 generate_tcs_get_primitive_id(p, dst);
1955 break;
1956
1957 case TCS_OPCODE_CREATE_BARRIER_HEADER:
1958 generate_tcs_create_barrier_header(p, prog_data, dst);
1959 break;
1960
1961 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
1962 generate_tes_create_input_read_header(p, dst);
1963 break;
1964
1965 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
1966 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
1967 break;
1968
1969 case TES_OPCODE_GET_PRIMITIVE_ID:
1970 generate_tes_get_primitive_id(p, dst);
1971 break;
1972
1973 case TCS_OPCODE_SRC0_010_IS_ZERO:
1974 /* If src_reg had stride like fs_reg, we wouldn't need this. */
1975 brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
1976 break;
1977
1978 case TCS_OPCODE_RELEASE_INPUT:
1979 generate_tcs_release_input(p, dst, src[0], src[1]);
1980 break;
1981
1982 case TCS_OPCODE_THREAD_END:
1983 generate_tcs_thread_end(p, inst);
1984 break;
1985
1986 case SHADER_OPCODE_BARRIER:
1987 brw_barrier(p, src[0]);
1988 brw_WAIT(p);
1989 break;
1990
1991 case SHADER_OPCODE_MOV_INDIRECT:
1992 generate_mov_indirect(p, inst, dst, src[0], src[1], src[2]);
1993
1994 default:
1995 unreachable("Unsupported opcode");
1996 }
1997
1998 if (fix_exec_size)
1999 brw_set_default_exec_size(p, BRW_EXECUTE_8);
2000
2001 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
2002 /* Handled dependency hints in the generator. */
2003
2004 assert(!inst->conditional_mod);
2005 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2006 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
2007 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2008 "emitting more than 1 instruction");
2009
2010 brw_inst *last = &p->store[pre_emit_nr_insn];
2011
2012 if (inst->conditional_mod)
2013 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2014 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2015 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2016 }
2017 }
2018
2019 brw_set_uip_jip(p);
2020 annotation_finalize(&annotation, p->next_insn_offset);
2021
2022 #ifndef NDEBUG
2023 bool validated = brw_validate_instructions(p, 0, &annotation);
2024 #else
2025 if (unlikely(debug_flag))
2026 brw_validate_instructions(p, 0, &annotation);
2027 #endif
2028
2029 int before_size = p->next_insn_offset;
2030 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
2031 int after_size = p->next_insn_offset;
2032
2033 if (unlikely(debug_flag)) {
2034 fprintf(stderr, "Native code for %s %s shader %s:\n",
2035 nir->info.label ? nir->info.label : "unnamed",
2036 _mesa_shader_stage_to_string(nir->stage), nir->info.name);
2037
2038 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles."
2039 "Compacted %d to %d bytes (%.0f%%)\n",
2040 stage_abbrev,
2041 before_size / 16, loop_count, cfg->cycle_count, before_size, after_size,
2042 100.0f * (before_size - after_size) / before_size);
2043
2044 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2045 p->devinfo);
2046 ralloc_free(annotation.mem_ctx);
2047 }
2048 assert(validated);
2049
2050 compiler->shader_debug_log(log_data,
2051 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2052 "compacted %d to %d bytes.",
2053 stage_abbrev, before_size / 16,
2054 loop_count, cfg->cycle_count,
2055 before_size, after_size);
2056 }
2057
2058 extern "C" const unsigned *
2059 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
2060 void *log_data,
2061 void *mem_ctx,
2062 const nir_shader *nir,
2063 struct brw_vue_prog_data *prog_data,
2064 const struct cfg_t *cfg,
2065 unsigned *out_assembly_size)
2066 {
2067 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
2068 brw_init_codegen(compiler->devinfo, p, mem_ctx);
2069 brw_set_default_access_mode(p, BRW_ALIGN_16);
2070
2071 generate_code(p, compiler, log_data, nir, prog_data, cfg);
2072
2073 return brw_get_program(p, out_assembly_size);
2074 }