src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4_gs_visitor.h"
  25
  26 namespace brw {
  27
  28 void
  29 vec4_gs_visitor::nir_setup_inputs()
  30 {
  31 }
  32
  33 void
  34 vec4_gs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
  35 {
  36    dst_reg *reg;
  37
  38    switch (instr->intrinsic) {
  39    case nir_intrinsic_load_primitive_id:
  40       /* We'll just read g1 directly; don't create a temporary. */
  41       break;
  42
  43    case nir_intrinsic_load_invocation_id:
  44       reg = &this->nir_system_values[SYSTEM_VALUE_INVOCATION_ID];
  45       if (reg->file == BAD_FILE)
  46          *reg = *this->make_reg_for_system_value(SYSTEM_VALUE_INVOCATION_ID);
  47       break;
  48
  49    default:
  50       vec4_visitor::nir_setup_system_value_intrinsic(instr);
  51    }
  52
  53 }
  54
  55 void
  56 vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
  57 {
  58    dst_reg dest;
  59    src_reg src;
  60
  61    switch (instr->intrinsic) {
  62    case nir_intrinsic_load_per_vertex_input: {
  63       /* The EmitNoIndirectInput flag guarantees our vertex index will
  64        * be constant.  We should handle indirects someday.
  65        */
  66       nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
  67       nir_const_value *offset_reg = nir_src_as_const_value(instr->src[1]);
  68
  69       if (nir_dest_bit_size(instr->dest) == 64) {
  70          src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u32[0] +
  71                        instr->const_index[0] + offset_reg->u32[0],
  72                        glsl_type::dvec4_type);
  73
  74          dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
  75          shuffle_64bit_data(tmp, src, false);
  76
  77          src = src_reg(tmp);
  78          src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr) / 2);
  79
  80          /* Write to dst reg taking into account original writemask */
  81          dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF);
  82          dest.writemask = brw_writemask_for_size(instr->num_components);
  83          emit(MOV(dest, src));
  84       } else {
  85          /* Make up a type...we have no way of knowing... */
  86          const glsl_type *const type = glsl_type::ivec(instr->num_components);
  87
  88          src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u32[0] +
  89                        instr->const_index[0] + offset_reg->u32[0],
  90                        type);
  91          src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
  92
  93          /* gl_PointSize is passed in the .w component of the VUE header */
  94          if (instr->const_index[0] == VARYING_SLOT_PSIZ)
  95             src.swizzle = BRW_SWIZZLE_WWWW;
  96
  97          dest = get_nir_dest(instr->dest, src.type);
  98          dest.writemask = brw_writemask_for_size(instr->num_components);
  99          emit(MOV(dest, src));
 100       }
 101       break;
 102    }
 103
 104    case nir_intrinsic_load_input:
 105       unreachable("nir_lower_io should have produced per_vertex intrinsics");
 106
 107    case nir_intrinsic_emit_vertex_with_counter: {
 108       this->vertex_count =
 109          retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
 110       int stream_id = instr->const_index[0];
 111       gs_emit_vertex(stream_id);
 112       break;
 113    }
 114
 115    case nir_intrinsic_end_primitive_with_counter:
 116       this->vertex_count =
 117          retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
 118       gs_end_primitive();
 119       break;
 120
 121    case nir_intrinsic_set_vertex_count:
 122       this->vertex_count =
 123          retype(get_nir_src(instr->src[0], 1), BRW_REGISTER_TYPE_UD);
 124       break;
 125
 126    case nir_intrinsic_load_primitive_id:
 127       assert(gs_prog_data->include_primitive_id);
 128       dest = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);
 129       emit(MOV(dest, retype(brw_vec4_grf(1, 0), BRW_REGISTER_TYPE_D)));
 130       break;
 131
 132    case nir_intrinsic_load_invocation_id: {
 133       src_reg invocation_id =
 134          src_reg(nir_system_values[SYSTEM_VALUE_INVOCATION_ID]);
 135       assert(invocation_id.file != BAD_FILE);
 136       dest = get_nir_dest(instr->dest, invocation_id.type);
 137       emit(MOV(dest, invocation_id));
 138       break;
 139    }
 140
 141    default:
 142       vec4_visitor::nir_emit_intrinsic(instr);
 143    }
 144 }
 145 }