src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 struct brw_vs_unit_key {
  40    unsigned int total_grf;
  41    unsigned int urb_entry_read_length;
  42    unsigned int curb_entry_read_length;
  43
  44    unsigned int curbe_offset;
  45
  46    unsigned int nr_urb_entries, urb_size;
  47
  48    unsigned int nr_surfaces;
  49 };
  50
  51 static void
  52 vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key)
  53 {
  54    struct gl_context *ctx = &brw->intel.ctx;
  55
  56    memset(key, 0, sizeof(*key));
  57
  58    /* CACHE_NEW_VS_PROG */
  59    key->total_grf = brw->vs.prog_data->total_grf;
  60    key->urb_entry_read_length = brw->vs.prog_data->urb_read_length;
  61    key->curb_entry_read_length = brw->vs.prog_data->curb_read_length;
  62
  63    /* BRW_NEW_URB_FENCE */
  64    key->nr_urb_entries = brw->urb.nr_vs_entries;
  65    key->urb_size = brw->urb.vsize;
  66
  67    /* BRW_NEW_NR_VS_SURFACES */
  68    key->nr_surfaces = brw->vs.nr_surfaces;
  69
  70    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
  71    if (ctx->Transform.ClipPlanesEnabled) {
  72       /* Note that we read in the userclip planes as well, hence
  73        * clip_start:
  74        */
  75       key->curbe_offset = brw->curbe.clip_start;
  76    }
  77    else {
  78       key->curbe_offset = brw->curbe.vs_start;
  79    }
  80 }
  81
  82 static drm_intel_bo *
  83 vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86    struct brw_vs_unit_state vs;
  87    drm_intel_bo *bo;
  88
  89    memset(&vs, 0, sizeof(vs));
  90
  91    vs.thread0.kernel_start_pointer = brw->vs.prog_bo->offset >> 6; /* reloc */
  92    vs.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
  93    vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  94    /* Choosing multiple program flow means that we may get 2-vertex threads,
  95     * which will have the channel mask for dwords 4-7 enabled in the thread,
  96     * and those dwords will be written to the second URB handle when we
  97     * brw_urb_WRITE() results.
  98     */
  99    vs.thread1.single_program_flow = 0;
 100
 101    if (intel->gen == 5)
 102       vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
 103    else
 104       vs.thread1.binding_table_entry_count = key->nr_surfaces;
 105
 106    vs.thread3.urb_entry_read_length = key->urb_entry_read_length;
 107    vs.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
 108    vs.thread3.dispatch_grf_start_reg = 1;
 109    vs.thread3.urb_entry_read_offset = 0;
 110    vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 111
 112    if (intel->gen == 5) {
 113       switch (key->nr_urb_entries) {
 114       case 8:
 115       case 12:
 116       case 16:
 117       case 32:
 118       case 64:
 119       case 96:
 120       case 128:
 121       case 168:
 122       case 192:
 123       case 224:
 124       case 256:
 125          vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2;
 126          break;
 127       default:
 128          assert(0);
 129       }
 130    } else {
 131       switch (key->nr_urb_entries) {
 132       case 8:
 133       case 12:
 134       case 16:
 135       case 32:
 136          break;
 137       case 64:
 138          assert(intel->is_g4x);
 139          break;
 140       default:
 141          assert(0);
 142       }
 143       vs.thread4.nr_urb_entries = key->nr_urb_entries;
 144    }
 145
 146    vs.thread4.urb_entry_allocation_size = key->urb_size - 1;
 147
 148    vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2,
 149                                   1, brw->vs_max_threads) - 1;
 150
 151    /* No samplers for ARB_vp programs:
 152     */
 153    /* It has to be set to 0 for Ironlake
 154     */
 155    vs.vs5.sampler_count = 0;
 156
 157    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 158       vs.thread4.stats_enable = 1;
 159
 160    /* Vertex program always enabled:
 161     */
 162    vs.vs6.vs_enable = 1;
 163
 164    bo = brw_upload_cache(&brw->cache, BRW_VS_UNIT,
 165                          key, sizeof(*key),
 166                          &brw->vs.prog_bo, 1,
 167                          &vs, sizeof(vs));
 168
 169    /* Emit VS program relocation */
 170    drm_intel_bo_emit_reloc(bo, offsetof(struct brw_vs_unit_state, thread0),
 171                            brw->vs.prog_bo, vs.thread0.grf_reg_count << 1,
 172                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 173
 174    return bo;
 175 }
 176
 177 static void prepare_vs_unit(struct brw_context *brw)
 178 {
 179    struct brw_vs_unit_key key;
 180
 181    vs_unit_populate_key(brw, &key);
 182
 183    drm_intel_bo_unreference(brw->vs.state_bo);
 184    brw->vs.state_bo = brw_search_cache(&brw->cache, BRW_VS_UNIT,
 185                                        &key, sizeof(key),
 186                                        &brw->vs.prog_bo, 1,
 187                                        NULL);
 188    if (brw->vs.state_bo == NULL) {
 189       brw->vs.state_bo = vs_unit_create_from_key(brw, &key);
 190    }
 191 }
 192
 193 const struct brw_tracked_state brw_vs_unit = {
 194    .dirty = {
 195       .mesa  = _NEW_TRANSFORM,
 196       .brw   = (BRW_NEW_CURBE_OFFSETS |
 197                 BRW_NEW_NR_VS_SURFACES |
 198                 BRW_NEW_URB_FENCE),
 199       .cache = CACHE_NEW_VS_PROG
 200    },
 201    .prepare = prepare_vs_unit,
 202 };