src/mesa/drivers/dri/i965/brw_vs_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "main/macros.h"
  38
  39 static void
  40 brw_prepare_vs_unit(struct brw_context *brw)
  41 {
  42    struct intel_context *intel = &brw->intel;
  43    struct gl_context *ctx = &intel->ctx;
  44    struct brw_vs_unit_state *vs;
  45
  46    vs = brw_state_batch(brw, AUB_TRACE_VS_STATE,
  47                         sizeof(*vs), 32, &brw->vs.state_offset);
  48    memset(vs, 0, sizeof(*vs));
  49
  50    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */
  51    vs->thread0.grf_reg_count = ALIGN(brw->vs.prog_data->total_grf, 16) / 16 - 1;
  52    vs->thread0.kernel_start_pointer =
  53       brw_program_reloc(brw,
  54                         brw->vs.state_offset +
  55                         offsetof(struct brw_vs_unit_state, thread0),
  56                         brw->vs.prog_offset +
  57                         (vs->thread0.grf_reg_count << 1)) >> 6;
  58
  59    vs->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  60    /* Choosing multiple program flow means that we may get 2-vertex threads,
  61     * which will have the channel mask for dwords 4-7 enabled in the thread,
  62     * and those dwords will be written to the second URB handle when we
  63     * brw_urb_WRITE() results.
  64     */
  65    /* Disable single program flow on Ironlake.  We cannot reliably get
  66     * all applications working without it.  See:
  67     * https://bugs.freedesktop.org/show_bug.cgi?id=29172
  68     *
  69     * The most notable and reliably failing application is the Humus
  70     * demo "CelShading"
  71    */
  72    vs->thread1.single_program_flow = (intel->gen == 5);
  73
  74    /* BRW_NEW_NR_VS_SURFACES */
  75    if (intel->gen == 5)
  76       vs->thread1.binding_table_entry_count = 0; /* hardware requirement */
  77    else
  78       vs->thread1.binding_table_entry_count = brw->vs.nr_surfaces;
  79
  80    vs->thread3.urb_entry_read_length = brw->vs.prog_data->urb_read_length;
  81    vs->thread3.const_urb_entry_read_length = brw->vs.prog_data->curb_read_length;
  82    vs->thread3.dispatch_grf_start_reg = 1;
  83    vs->thread3.urb_entry_read_offset = 0;
  84
  85    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM */
  86    if (ctx->Transform.ClipPlanesEnabled) {
  87       /* Note that we read in the userclip planes as well, hence
  88        * clip_start:
  89        */
  90       vs->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  91    }
  92    else {
  93       vs->thread3.const_urb_entry_read_offset = brw->curbe.vs_start * 2;
  94    }
  95
  96
  97    /* BRW_NEW_URB_FENCE */
  98    if (intel->gen == 5) {
  99       switch (brw->urb.nr_vs_entries) {
 100       case 8:
 101       case 12:
 102       case 16:
 103       case 32:
 104       case 64:
 105       case 96:
 106       case 128:
 107       case 168:
 108       case 192:
 109       case 224:
 110       case 256:
 111          vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries >> 2;
 112          break;
 113       default:
 114          assert(0);
 115       }
 116    } else {
 117       switch (brw->urb.nr_vs_entries) {
 118       case 8:
 119       case 12:
 120       case 16:
 121       case 32:
 122          break;
 123       case 64:
 124          assert(intel->is_g4x);
 125          break;
 126       default:
 127          assert(0);
 128       }
 129       vs->thread4.nr_urb_entries = brw->urb.nr_vs_entries;
 130    }
 131
 132    vs->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
 133
 134    vs->thread4.max_threads = CLAMP(brw->urb.nr_vs_entries / 2,
 135                                    1, brw->vs_max_threads) - 1;
 136
 137    /* No samplers for ARB_vp programs:
 138     */
 139    /* It has to be set to 0 for Ironlake
 140     */
 141    vs->vs5.sampler_count = 0;
 142
 143    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 144       vs->thread4.stats_enable = 1;
 145
 146    /* Vertex program always enabled:
 147     */
 148    vs->vs6.vs_enable = 1;
 149
 150    brw->state.dirty.cache |= CACHE_NEW_VS_UNIT;
 151 }
 152
 153 const struct brw_tracked_state brw_vs_unit = {
 154    .dirty = {
 155       .mesa  = _NEW_TRANSFORM,
 156       .brw   = (BRW_NEW_BATCH |
 157                 BRW_NEW_PROGRAM_CACHE |
 158                 BRW_NEW_CURBE_OFFSETS |
 159                 BRW_NEW_NR_VS_SURFACES |
 160                 BRW_NEW_URB_FENCE),
 161       .cache = CACHE_NEW_VS_PROG
 162    },
 163    .prepare = brw_prepare_vs_unit,
 164 };