src/mesa/drivers/dri/i965/brw_wm.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_wm.h"
  34 #include "brw_state.h"
  35 #include "main/formats.h"
  36
  37 /** Return number of src args for given instruction */
  38 GLuint brw_wm_nr_args( GLuint opcode )
  39 {
  40    switch (opcode) {
  41    case WM_FRONTFACING:
  42    case WM_PIXELXY:
  43       return 0;
  44    case WM_CINTERP:
  45    case WM_WPOSXY:
  46    case WM_DELTAXY:
  47       return 1;
  48    case WM_LINTERP:
  49    case WM_PIXELW:
  50       return 2;
  51    case WM_FB_WRITE:
  52    case WM_PINTERP:
  53       return 3;
  54    default:
  55       assert(opcode < MAX_OPCODE);
  56       return _mesa_num_inst_src_regs(opcode);
  57    }
  58 }
  59
  60
  61 GLuint brw_wm_is_scalar_result( GLuint opcode )
  62 {
  63    switch (opcode) {
  64    case OPCODE_COS:
  65    case OPCODE_EX2:
  66    case OPCODE_LG2:
  67    case OPCODE_POW:
  68    case OPCODE_RCP:
  69    case OPCODE_RSQ:
  70    case OPCODE_SIN:
  71    case OPCODE_DP2:
  72    case OPCODE_DP3:
  73    case OPCODE_DP4:
  74    case OPCODE_DPH:
  75    case OPCODE_DST:
  76       return 1;
  77
  78    default:
  79       return 0;
  80    }
  81 }
  82
  83
  84 /**
  85  * Do GPU code generation for non-GLSL shader.  non-GLSL shaders have
  86  * no flow control instructions so we can more readily do SSA-style
  87  * optimizations.
  88  */
  89 static void
  90 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
  91 {
  92    /* Augment fragment program.  Add instructions for pre- and
  93     * post-fragment-program tasks such as interpolation and fogging.
  94     */
  95    brw_wm_pass_fp(c);
  96
  97    /* Translate to intermediate representation.  Build register usage
  98     * chains.
  99     */
 100    brw_wm_pass0(c);
 101
 102    /* Dead code removal.
 103     */
 104    brw_wm_pass1(c);
 105
 106    /* Register allocation.
 107     * Divide by two because we operate on 16 pixels at a time and require
 108     * two GRF entries for each logical shader register.
 109     */
 110    c->grf_limit = BRW_WM_MAX_GRF / 2;
 111
 112    brw_wm_pass2(c);
 113
 114    /* how many general-purpose registers are used */
 115    c->prog_data.total_grf = c->max_wm_grf;
 116
 117    /* Scratch space is used for register spilling */
 118    if (c->last_scratch) {
 119       c->prog_data.total_scratch = c->last_scratch + 0x40;
 120    }
 121    else {
 122       c->prog_data.total_scratch = 0;
 123    }
 124
 125    /* Emit GEN4 code.
 126     */
 127    brw_wm_emit(c);
 128 }
 129
 130
 131 /**
 132  * All Mesa program -> GPU code generation goes through this function.
 133  * Depending on the instructions used (i.e. flow control instructions)
 134  * we'll use one of two code generators.
 135  */
 136 static void do_wm_prog( struct brw_context *brw,
 137                         struct brw_fragment_program *fp,
 138                         struct brw_wm_prog_key *key)
 139 {
 140    struct brw_wm_compile *c;
 141    const GLuint *program;
 142    GLuint program_size;
 143
 144    c = brw->wm.compile_data;
 145    if (c == NULL) {
 146       brw->wm.compile_data = calloc(1, sizeof(*brw->wm.compile_data));
 147       c = brw->wm.compile_data;
 148       if (c == NULL) {
 149          /* Ouch - big out of memory problem.  Can't continue
 150           * without triggering a segfault, no way to signal,
 151           * so just return.
 152           */
 153          return;
 154       }
 155       c->instruction = calloc(1, BRW_WM_MAX_INSN * sizeof(*c->instruction));
 156       c->prog_instructions = calloc(1, BRW_WM_MAX_INSN *
 157                                           sizeof(*c->prog_instructions));
 158       c->vreg = calloc(1, BRW_WM_MAX_VREG * sizeof(*c->vreg));
 159       c->refs = calloc(1, BRW_WM_MAX_REF * sizeof(*c->refs));
 160    } else {
 161       void *instruction = c->instruction;
 162       void *prog_instructions = c->prog_instructions;
 163       void *vreg = c->vreg;
 164       void *refs = c->refs;
 165       memset(c, 0, sizeof(*brw->wm.compile_data));
 166       c->instruction = instruction;
 167       c->prog_instructions = prog_instructions;
 168       c->vreg = vreg;
 169       c->refs = refs;
 170    }
 171    memcpy(&c->key, key, sizeof(*key));
 172
 173    c->fp = fp;
 174    c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
 175
 176    brw_init_compile(brw, &c->func);
 177
 178    /* temporary sanity check assertion */
 179    ASSERT(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
 180
 181    if (!brw_wm_fs_emit(brw, c)) {
 182       /*
 183        * Shader which use GLSL features such as flow control are handled
 184        * differently from "simple" shaders.
 185        */
 186       if (fp->isGLSL) {
 187          c->dispatch_width = 8;
 188          brw_wm_glsl_emit(brw, c);
 189       }
 190       else {
 191          c->dispatch_width = 16;
 192          brw_wm_non_glsl_emit(brw, c);
 193       }
 194    }
 195
 196    if (INTEL_DEBUG & DEBUG_WM)
 197       fprintf(stderr, "\n");
 198
 199    /* get the program
 200     */
 201    program = brw_get_program(&c->func, &program_size);
 202
 203    drm_intel_bo_unreference(brw->wm.prog_bo);
 204    brw->wm.prog_bo = brw_upload_cache_with_auxdata(&brw->cache, BRW_WM_PROG,
 205                                                    &c->key, sizeof(c->key),
 206                                                    NULL, 0,
 207                                                    program, program_size,
 208                                                    &c->prog_data,
 209                                                    sizeof(c->prog_data),
 210                                                    &brw->wm.prog_data);
 211 }
 212
 213
 214
 215 static void brw_wm_populate_key( struct brw_context *brw,
 216                                  struct brw_wm_prog_key *key )
 217 {
 218    GLcontext *ctx = &brw->intel.ctx;
 219    /* BRW_NEW_FRAGMENT_PROGRAM */
 220    const struct brw_fragment_program *fp =
 221       (struct brw_fragment_program *)brw->fragment_program;
 222    GLboolean uses_depth = (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
 223    GLuint lookup = 0;
 224    GLuint line_aa;
 225    GLuint i;
 226
 227    memset(key, 0, sizeof(*key));
 228
 229    /* Build the index for table lookup
 230     */
 231    /* _NEW_COLOR */
 232    if (fp->program.UsesKill ||
 233        ctx->Color.AlphaEnabled)
 234       lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 235
 236    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 237       lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 238
 239    /* _NEW_DEPTH */
 240    if (ctx->Depth.Test)
 241       lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
 242
 243    if (ctx->Depth.Test &&
 244        ctx->Depth.Mask) /* ?? */
 245       lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
 246
 247    /* _NEW_STENCIL */
 248    if (ctx->Stencil._Enabled) {
 249       lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
 250
 251       if (ctx->Stencil.WriteMask[0] ||
 252           ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
 253          lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
 254    }
 255
 256    line_aa = AA_NEVER;
 257
 258    /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
 259    if (ctx->Line.SmoothFlag) {
 260       if (brw->intel.reduced_primitive == GL_LINES) {
 261          line_aa = AA_ALWAYS;
 262       }
 263       else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
 264          if (ctx->Polygon.FrontMode == GL_LINE) {
 265             line_aa = AA_SOMETIMES;
 266
 267             if (ctx->Polygon.BackMode == GL_LINE ||
 268                 (ctx->Polygon.CullFlag &&
 269                  ctx->Polygon.CullFaceMode == GL_BACK))
 270                line_aa = AA_ALWAYS;
 271          }
 272          else if (ctx->Polygon.BackMode == GL_LINE) {
 273             line_aa = AA_SOMETIMES;
 274
 275             if ((ctx->Polygon.CullFlag &&
 276                  ctx->Polygon.CullFaceMode == GL_FRONT))
 277                line_aa = AA_ALWAYS;
 278          }
 279       }
 280    }
 281
 282    brw_wm_lookup_iz(line_aa,
 283                     lookup,
 284                     uses_depth,
 285                     key);
 286
 287
 288    /* BRW_NEW_WM_INPUT_DIMENSIONS */
 289    key->proj_attrib_mask = brw->wm.input_size_masks[4-1];
 290
 291    /* _NEW_LIGHT */
 292    key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
 293
 294    /* _NEW_HINT */
 295    key->linear_color = (ctx->Hint.PerspectiveCorrection == GL_FASTEST);
 296
 297    /* _NEW_TEXTURE */
 298    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 299       const struct gl_texture_unit *unit = &ctx->Texture.Unit[i];
 300
 301       if (unit->_ReallyEnabled) {
 302          const struct gl_texture_object *t = unit->_Current;
 303          const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
 304          if (img->InternalFormat == GL_YCBCR_MESA) {
 305             key->yuvtex_mask |= 1 << i;
 306             if (img->TexFormat == MESA_FORMAT_YCBCR)
 307                 key->yuvtex_swap_mask |= 1 << i;
 308          }
 309
 310          key->tex_swizzles[i] = t->_Swizzle;
 311       }
 312       else {
 313          key->tex_swizzles[i] = SWIZZLE_NOOP;
 314       }
 315    }
 316
 317    /* Shadow */
 318    key->shadowtex_mask = fp->program.Base.ShadowSamplers;
 319
 320    /* _NEW_BUFFERS */
 321    /*
 322     * Include the draw buffer origin and height so that we can calculate
 323     * fragment position values relative to the bottom left of the drawable,
 324     * from the incoming screen origin relative position we get as part of our
 325     * payload.
 326     *
 327     * This is only needed for the WM_WPOSXY opcode when the fragment program
 328     * uses the gl_FragCoord input.
 329     *
 330     * We could avoid recompiling by including this as a constant referenced by
 331     * our program, but if we were to do that it would also be nice to handle
 332     * getting that constant updated at batchbuffer submit time (when we
 333     * hold the lock and know where the buffer really is) rather than at emit
 334     * time when we don't hold the lock and are just guessing.  We could also
 335     * just avoid using this as key data if the program doesn't use
 336     * fragment.position.
 337     *
 338     * For DRI2 the origin_x/y will always be (0,0) but we still need the
 339     * drawable height in order to invert the Y axis.
 340     */
 341    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
 342       key->drawable_height = ctx->DrawBuffer->Height;
 343    }
 344
 345    key->nr_color_regions = brw->state.nr_color_regions;
 346
 347    /* CACHE_NEW_VS_PROG */
 348    key->vp_outputs_written = brw->vs.prog_data->outputs_written;
 349
 350    /* The unique fragment program ID */
 351    key->program_string_id = fp->id;
 352 }
 353
 354
 355 static void brw_prepare_wm_prog(struct brw_context *brw)
 356 {
 357    struct brw_wm_prog_key key;
 358    struct brw_fragment_program *fp = (struct brw_fragment_program *)
 359       brw->fragment_program;
 360
 361    brw_wm_populate_key(brw, &key);
 362
 363    /* Make an early check for the key.
 364     */
 365    drm_intel_bo_unreference(brw->wm.prog_bo);
 366    brw->wm.prog_bo = brw_search_cache(&brw->cache, BRW_WM_PROG,
 367                                       &key, sizeof(key),
 368                                       NULL, 0,
 369                                       &brw->wm.prog_data);
 370    if (brw->wm.prog_bo == NULL)
 371       do_wm_prog(brw, fp, &key);
 372 }
 373
 374
 375 const struct brw_tracked_state brw_wm_prog = {
 376    .dirty = {
 377       .mesa  = (_NEW_COLOR |
 378                 _NEW_DEPTH |
 379                 _NEW_HINT |
 380                 _NEW_STENCIL |
 381                 _NEW_POLYGON |
 382                 _NEW_LINE |
 383                 _NEW_LIGHT |
 384                 _NEW_BUFFERS |
 385                 _NEW_TEXTURE),
 386       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 387                 BRW_NEW_WM_INPUT_DIMENSIONS |
 388                 BRW_NEW_REDUCED_PRIMITIVE),
 389       .cache = CACHE_NEW_VS_PROG,
 390    },
 391    .prepare = brw_prepare_wm_prog
 392 };
 393