src/mesa/drivers/dri/i965/brw_wm.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #ifndef BRW_WM_H
  34 #define BRW_WM_H
  35
  36
  37 #include "program/prog_instruction.h"
  38 #include "brw_context.h"
  39 #include "brw_eu.h"
  40
  41 #define SATURATE (1<<5)
  42
  43 /* A big lookup table is used to figure out which and how many
  44  * additional regs will inserted before the main payload in the WM
  45  * program execution.  These mainly relate to depth and stencil
  46  * processing and the early-depth-test optimization.
  47  */
  48 #define IZ_PS_KILL_ALPHATEST_BIT    0x1
  49 #define IZ_PS_COMPUTES_DEPTH_BIT    0x2
  50 #define IZ_DEPTH_WRITE_ENABLE_BIT   0x4
  51 #define IZ_DEPTH_TEST_ENABLE_BIT    0x8
  52 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10
  53 #define IZ_STENCIL_TEST_ENABLE_BIT  0x20
  54 #define IZ_BIT_MAX                  0x40
  55
  56 #define AA_NEVER     0
  57 #define AA_SOMETIMES 1
  58 #define AA_ALWAYS    2
  59
  60 struct brw_wm_prog_key {
  61    GLuint source_depth_reg:3;
  62    GLuint aa_dest_stencil_reg:3;
  63    GLuint dest_depth_reg:3;
  64    GLuint nr_depth_regs:3;
  65    GLuint computes_depth:1;     /* could be derived from program string */
  66    GLuint source_depth_to_render_target:1;
  67    GLuint flat_shade:1;
  68    GLuint linear_color:1;  /**< linear interpolation vs perspective interp */
  69    GLuint runtime_check_aads_emit:1;
  70    GLuint nr_color_regions:5;
  71
  72    GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
  73    GLuint shadowtex_mask:16;
  74    GLuint yuvtex_mask:16;
  75    GLuint yuvtex_swap_mask:16;  /* UV swaped */
  76
  77    GLushort tex_swizzles[BRW_MAX_TEX_UNIT];
  78
  79    GLushort drawable_height;
  80    GLbitfield64 vp_outputs_written;
  81    GLuint program_string_id:32;
  82 };
  83
  84
  85 /* A bit of a glossary:
  86  *
  87  * brw_wm_value: A computed value or program input.  Values are
  88  * constant, they are created once and are never modified.  When a
  89  * fragment program register is written or overwritten, new values are
  90  * created fresh, preserving the rule that values are constant.
  91  *
  92  * brw_wm_ref: A reference to a value.  Wherever a value used is by an
  93  * instruction or as a program output, that is tracked with an
  94  * instance of this struct.  All references to a value occur after it
  95  * is created.  After the last reference, a value is dead and can be
  96  * discarded.
  97  *
  98  * brw_wm_grf: Represents a physical hardware register.  May be either
  99  * empty or hold a value.  Register allocation is the process of
 100  * assigning values to grf registers.  This occurs in pass2 and the
 101  * brw_wm_grf struct is not used before that.
 102  *
 103  * Fragment program registers: These are time-varying constructs that
 104  * are hard to reason about and which we translate away in pass0.  A
 105  * single fragment program register element (eg. temp[0].x) will be
 106  * translated to one or more brw_wm_value structs, one for each time
 107  * that temp[0].x is written to during the program.
 108  */
 109
 110
 111
 112 /* Used in pass2 to track register allocation.
 113  */
 114 struct brw_wm_grf {
 115    struct brw_wm_value *value;
 116    GLuint nextuse;
 117 };
 118
 119 struct brw_wm_value {
 120    struct brw_reg hw_reg;       /* emitted to this reg, may not always be there */
 121    struct brw_wm_ref *lastuse;
 122    struct brw_wm_grf *resident;
 123    GLuint contributes_to_output:1;
 124    GLuint spill_slot:16;        /* if non-zero, spill immediately after calculation */
 125 };
 126
 127 struct brw_wm_ref {
 128    struct brw_reg hw_reg;       /* nr filled in in pass2, everything else, pass0 */
 129    struct brw_wm_value *value;
 130    struct brw_wm_ref *prevuse;
 131    GLuint unspill_reg:7;        /* unspill to reg */
 132    GLuint emitted:1;
 133    GLuint insn:24;
 134 };
 135
 136 struct brw_wm_constref {
 137    const struct brw_wm_ref *ref;
 138    GLfloat constval;
 139 };
 140
 141
 142 struct brw_wm_instruction {
 143    struct brw_wm_value *dst[4];
 144    struct brw_wm_ref *src[3][4];
 145    GLuint opcode:8;
 146    GLuint saturate:1;
 147    GLuint writemask:4;
 148    GLuint tex_unit:4;   /* texture unit for TEX, TXD, TXP instructions */
 149    GLuint tex_idx:3;    /* TEXTURE_1D,2D,3D,CUBE,RECT_INDEX source target */
 150    GLuint tex_shadow:1; /* do shadow comparison? */
 151    GLuint eot:1;        /* End of thread indicator for FB_WRITE*/
 152    GLuint target:10;    /* target binding table index for FB_WRITE*/
 153 };
 154
 155
 156 #define BRW_WM_MAX_INSN  (MAX_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3)
 157 #define BRW_WM_MAX_GRF   128            /* hardware limit */
 158 #define BRW_WM_MAX_VREG  (BRW_WM_MAX_INSN * 4)
 159 #define BRW_WM_MAX_REF   (BRW_WM_MAX_INSN * 12)
 160 #define BRW_WM_MAX_PARAM 256
 161 #define BRW_WM_MAX_CONST 256
 162 #define BRW_WM_MAX_SUBROUTINE 16
 163
 164 /* used in masks next to WRITEMASK_*. */
 165 #define SATURATE (1<<5)
 166
 167
 168 /* New opcodes to track internal operations required for WM unit.
 169  * These are added early so that the registers used can be tracked,
 170  * freed and reused like those of other instructions.
 171  */
 172 #define WM_PIXELXY        (MAX_OPCODE)
 173 #define WM_DELTAXY        (MAX_OPCODE + 1)
 174 #define WM_PIXELW         (MAX_OPCODE + 2)
 175 #define WM_LINTERP        (MAX_OPCODE + 3)
 176 #define WM_PINTERP        (MAX_OPCODE + 4)
 177 #define WM_CINTERP        (MAX_OPCODE + 5)
 178 #define WM_WPOSXY         (MAX_OPCODE + 6)
 179 #define WM_FB_WRITE       (MAX_OPCODE + 7)
 180 #define WM_FRONTFACING    (MAX_OPCODE + 8)
 181 #define MAX_WM_OPCODE     (MAX_OPCODE + 9)
 182
 183 #define PROGRAM_PAYLOAD   (PROGRAM_FILE_MAX)
 184 #define PAYLOAD_DEPTH     (FRAG_ATTRIB_MAX)
 185
 186 struct brw_wm_compile {
 187    struct brw_compile func;
 188    struct brw_wm_prog_key key;
 189    struct brw_wm_prog_data prog_data;
 190
 191    struct brw_fragment_program *fp;
 192
 193    GLfloat (*env_param)[4];
 194
 195    enum {
 196       START,
 197       PASS2_DONE
 198    } state;
 199
 200    /* Initial pass - translate fp instructions to fp instructions,
 201     * simplifying and adding instructions for interpolation and
 202     * framebuffer writes.
 203     */
 204    struct prog_instruction *prog_instructions;
 205    GLuint nr_fp_insns;
 206    GLuint fp_temp;
 207    GLuint fp_interp_emitted;
 208    GLuint fp_fragcolor_emitted;
 209
 210    struct prog_src_register pixel_xy;
 211    struct prog_src_register delta_xy;
 212    struct prog_src_register pixel_w;
 213
 214
 215    struct brw_wm_value *vreg;
 216    GLuint nr_vreg;
 217
 218    struct brw_wm_value creg[BRW_WM_MAX_PARAM];
 219    GLuint nr_creg;
 220
 221    struct {
 222       struct brw_wm_value depth[4]; /* includes r0/r1 */
 223       struct brw_wm_value input_interp[FRAG_ATTRIB_MAX];
 224    } payload;
 225
 226
 227    const struct brw_wm_ref *pass0_fp_reg[PROGRAM_PAYLOAD+1][256][4];
 228
 229    struct brw_wm_ref undef_ref;
 230    struct brw_wm_value undef_value;
 231
 232    struct brw_wm_ref *refs;
 233    GLuint nr_refs;
 234
 235    struct brw_wm_instruction *instruction;
 236    GLuint nr_insns;
 237
 238    struct brw_wm_constref constref[BRW_WM_MAX_CONST];
 239    GLuint nr_constrefs;
 240
 241    struct brw_wm_grf pass2_grf[BRW_WM_MAX_GRF/2];
 242
 243    GLuint grf_limit;
 244    GLuint max_wm_grf;
 245    GLuint last_scratch;
 246
 247    GLuint cur_inst;  /**< index of current instruction */
 248
 249    GLboolean out_of_regs;  /**< ran out of GRF registers? */
 250
 251    /** Mapping from Mesa registers to hardware registers */
 252    struct {
 253       GLboolean inited;
 254       struct brw_reg reg;
 255    } wm_regs[PROGRAM_PAYLOAD+1][256][4];
 256
 257    GLboolean used_grf[BRW_WM_MAX_GRF];
 258    GLuint first_free_grf;
 259    struct brw_reg stack;
 260    struct brw_reg emit_mask_reg;
 261    GLuint tmp_regs[BRW_WM_MAX_GRF];
 262    GLuint tmp_index;
 263    GLuint tmp_max;
 264    GLuint subroutines[BRW_WM_MAX_SUBROUTINE];
 265    GLuint dispatch_width;
 266
 267    /** we may need up to 3 constants per instruction (if use_const_buffer) */
 268    struct {
 269       GLint index;
 270       struct brw_reg reg;
 271    } current_const[3];
 272 };
 273
 274
 275 /** Bits for prog_instruction::Aux field */
 276 #define INST_AUX_EOT      0x1
 277 #define INST_AUX_TARGET(T)  (T << 1)
 278 #define INST_AUX_GET_TARGET(AUX) ((AUX) >> 1)
 279
 280
 281 GLuint brw_wm_nr_args( GLuint opcode );
 282 GLuint brw_wm_is_scalar_result( GLuint opcode );
 283
 284 void brw_wm_pass_fp( struct brw_wm_compile *c );
 285 void brw_wm_pass0( struct brw_wm_compile *c );
 286 void brw_wm_pass1( struct brw_wm_compile *c );
 287 void brw_wm_pass2( struct brw_wm_compile *c );
 288 void brw_wm_emit( struct brw_wm_compile *c );
 289 GLboolean brw_wm_arg_can_be_immediate(enum prog_opcode, int arg);
 290 void brw_wm_print_value( struct brw_wm_compile *c,
 291                          struct brw_wm_value *value );
 292
 293 void brw_wm_print_ref( struct brw_wm_compile *c,
 294                        struct brw_wm_ref *ref );
 295
 296 void brw_wm_print_insn( struct brw_wm_compile *c,
 297                         struct brw_wm_instruction *inst );
 298
 299 void brw_wm_print_program( struct brw_wm_compile *c,
 300                            const char *stage );
 301
 302 void brw_wm_lookup_iz( GLuint line_aa,
 303                        GLuint lookup,
 304                        GLboolean ps_uses_depth,
 305                        struct brw_wm_prog_key *key );
 306
 307 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
 308 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
 309
 310 /* brw_wm_emit.c */
 311 void emit_alu1(struct brw_compile *p,
 312                struct brw_instruction *(*func)(struct brw_compile *,
 313                                                struct brw_reg,
 314                                                struct brw_reg),
 315                const struct brw_reg *dst,
 316                GLuint mask,
 317                const struct brw_reg *arg0);
 318 void emit_alu2(struct brw_compile *p,
 319                struct brw_instruction *(*func)(struct brw_compile *,
 320                                                struct brw_reg,
 321                                                struct brw_reg,
 322                                                struct brw_reg),
 323                const struct brw_reg *dst,
 324                GLuint mask,
 325                const struct brw_reg *arg0,
 326                const struct brw_reg *arg1);
 327 void emit_cinterp(struct brw_compile *p,
 328                   const struct brw_reg *dst,
 329                   GLuint mask,
 330                   const struct brw_reg *arg0);
 331 void emit_cmp(struct brw_compile *p,
 332               const struct brw_reg *dst,
 333               GLuint mask,
 334               const struct brw_reg *arg0,
 335               const struct brw_reg *arg1,
 336               const struct brw_reg *arg2);
 337 void emit_ddxy(struct brw_compile *p,
 338                const struct brw_reg *dst,
 339                GLuint mask,
 340                GLboolean is_ddx,
 341                const struct brw_reg *arg0);
 342 void emit_delta_xy(struct brw_compile *p,
 343                    const struct brw_reg *dst,
 344                    GLuint mask,
 345                    const struct brw_reg *arg0);
 346 void emit_dp2(struct brw_compile *p,
 347               const struct brw_reg *dst,
 348               GLuint mask,
 349               const struct brw_reg *arg0,
 350               const struct brw_reg *arg1);
 351 void emit_dp3(struct brw_compile *p,
 352               const struct brw_reg *dst,
 353               GLuint mask,
 354               const struct brw_reg *arg0,
 355               const struct brw_reg *arg1);
 356 void emit_dp4(struct brw_compile *p,
 357               const struct brw_reg *dst,
 358               GLuint mask,
 359               const struct brw_reg *arg0,
 360               const struct brw_reg *arg1);
 361 void emit_dph(struct brw_compile *p,
 362               const struct brw_reg *dst,
 363               GLuint mask,
 364               const struct brw_reg *arg0,
 365               const struct brw_reg *arg1);
 366 void emit_fb_write(struct brw_wm_compile *c,
 367                    struct brw_reg *arg0,
 368                    struct brw_reg *arg1,
 369                    struct brw_reg *arg2,
 370                    GLuint target,
 371                    GLuint eot);
 372 void emit_frontfacing(struct brw_compile *p,
 373                       const struct brw_reg *dst,
 374                       GLuint mask);
 375 void emit_linterp(struct brw_compile *p,
 376                   const struct brw_reg *dst,
 377                   GLuint mask,
 378                   const struct brw_reg *arg0,
 379                   const struct brw_reg *deltas);
 380 void emit_lrp(struct brw_compile *p,
 381               const struct brw_reg *dst,
 382               GLuint mask,
 383               const struct brw_reg *arg0,
 384               const struct brw_reg *arg1,
 385               const struct brw_reg *arg2);
 386 void emit_mad(struct brw_compile *p,
 387               const struct brw_reg *dst,
 388               GLuint mask,
 389               const struct brw_reg *arg0,
 390               const struct brw_reg *arg1,
 391               const struct brw_reg *arg2);
 392 void emit_math1(struct brw_wm_compile *c,
 393                 GLuint function,
 394                 const struct brw_reg *dst,
 395                 GLuint mask,
 396                 const struct brw_reg *arg0);
 397 void emit_math2(struct brw_wm_compile *c,
 398                 GLuint function,
 399                 const struct brw_reg *dst,
 400                 GLuint mask,
 401                 const struct brw_reg *arg0,
 402                 const struct brw_reg *arg1);
 403 void emit_min(struct brw_compile *p,
 404               const struct brw_reg *dst,
 405               GLuint mask,
 406               const struct brw_reg *arg0,
 407               const struct brw_reg *arg1);
 408 void emit_max(struct brw_compile *p,
 409               const struct brw_reg *dst,
 410               GLuint mask,
 411               const struct brw_reg *arg0,
 412               const struct brw_reg *arg1);
 413 void emit_pinterp(struct brw_compile *p,
 414                   const struct brw_reg *dst,
 415                   GLuint mask,
 416                   const struct brw_reg *arg0,
 417                   const struct brw_reg *deltas,
 418                   const struct brw_reg *w);
 419 void emit_pixel_xy(struct brw_wm_compile *c,
 420                    const struct brw_reg *dst,
 421                    GLuint mask);
 422 void emit_pixel_w(struct brw_wm_compile *c,
 423                   const struct brw_reg *dst,
 424                   GLuint mask,
 425                   const struct brw_reg *arg0,
 426                   const struct brw_reg *deltas);
 427 void emit_sop(struct brw_compile *p,
 428               const struct brw_reg *dst,
 429               GLuint mask,
 430               GLuint cond,
 431               const struct brw_reg *arg0,
 432               const struct brw_reg *arg1);
 433 void emit_sign(struct brw_compile *p,
 434                const struct brw_reg *dst,
 435                GLuint mask,
 436                const struct brw_reg *arg0);
 437 void emit_tex(struct brw_wm_compile *c,
 438               struct brw_reg *dst,
 439               GLuint dst_flags,
 440               struct brw_reg *arg,
 441               struct brw_reg depth_payload,
 442               GLuint tex_idx,
 443               GLuint sampler,
 444               GLboolean shadow);
 445 void emit_txb(struct brw_wm_compile *c,
 446               struct brw_reg *dst,
 447               GLuint dst_flags,
 448               struct brw_reg *arg,
 449               struct brw_reg depth_payload,
 450               GLuint tex_idx,
 451               GLuint sampler);
 452 void emit_wpos_xy(struct brw_wm_compile *c,
 453                   const struct brw_reg *dst,
 454                   GLuint mask,
 455                   const struct brw_reg *arg0);
 456 void emit_xpd(struct brw_compile *p,
 457               const struct brw_reg *dst,
 458               GLuint mask,
 459               const struct brw_reg *arg0,
 460               const struct brw_reg *arg1);
 461
 462 #endif