src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "intel_fbo.h"
  35 #include "brw_context.h"
  36 #include "brw_state.h"
  37 #include "brw_defines.h"
  38 #include "brw_wm.h"
  39
  40 /***********************************************************************
  41  * WM unit - fragment programs and rasterization
  42  */
  43
  44 bool
  45 brw_color_buffer_write_enabled(struct brw_context *brw)
  46 {
  47    struct gl_context *ctx = &brw->ctx;
  48    /* BRW_NEW_FRAGMENT_PROGRAM */
  49    const struct gl_fragment_program *fp = brw->fragment_program;
  50    int i;
  51
  52    /* _NEW_BUFFERS */
  53    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
  54       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
  55
  56       /* _NEW_COLOR */
  57       if (rb &&
  58           (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
  59            fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
  60           (ctx->Color.ColorMask[i][0] ||
  61            ctx->Color.ColorMask[i][1] ||
  62            ctx->Color.ColorMask[i][2] ||
  63            ctx->Color.ColorMask[i][3])) {
  64          return true;
  65       }
  66    }
  67
  68    return false;
  69 }
  70
  71 /**
  72  * Setup wm hardware state.  See page 225 of Volume 2
  73  */
  74 static void
  75 brw_upload_wm_unit(struct brw_context *brw)
  76 {
  77    struct gl_context *ctx = &brw->ctx;
  78    /* BRW_NEW_FRAGMENT_PROGRAM */
  79    const struct gl_fragment_program *fp = brw->fragment_program;
  80    /* BRW_NEW_FS_PROG_DATA */
  81    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  82    struct brw_wm_unit_state *wm;
  83
  84    wm = brw_state_batch(brw, AUB_TRACE_WM_STATE,
  85                         sizeof(*wm), 32, &brw->wm.base.state_offset);
  86    memset(wm, 0, sizeof(*wm));
  87
  88    if (prog_data->prog_offset_16) {
  89       /* These two fields should be the same pre-gen6, which is why we
  90        * only have one hardware field to program for both dispatch
  91        * widths.
  92        */
  93       assert(prog_data->base.dispatch_grf_start_reg ==
  94              prog_data->dispatch_grf_start_reg_16);
  95    }
  96
  97    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_FS_PROG_DATA */
  98    if (prog_data->no_8) {
  99       wm->wm5.enable_16_pix = 1;
 100       wm->thread0.grf_reg_count = prog_data->reg_blocks_16;
 101       wm->thread0.kernel_start_pointer =
 102          brw_program_reloc(brw,
 103                            brw->wm.base.state_offset +
 104                            offsetof(struct brw_wm_unit_state, thread0),
 105                            brw->wm.base.prog_offset +
 106                            prog_data->prog_offset_16 +
 107                            (prog_data->reg_blocks_16 << 1)) >> 6;
 108
 109    } else {
 110       wm->thread0.grf_reg_count = prog_data->reg_blocks;
 111       wm->wm9.grf_reg_count_2 = prog_data->reg_blocks_16;
 112
 113       wm->wm5.enable_8_pix = 1;
 114       if (prog_data->prog_offset_16)
 115          wm->wm5.enable_16_pix = 1;
 116
 117       wm->thread0.kernel_start_pointer =
 118          brw_program_reloc(brw,
 119                            brw->wm.base.state_offset +
 120                            offsetof(struct brw_wm_unit_state, thread0),
 121                            brw->wm.base.prog_offset +
 122                            (wm->thread0.grf_reg_count << 1)) >> 6;
 123
 124       wm->wm9.kernel_start_pointer_2 =
 125          brw_program_reloc(brw,
 126                            brw->wm.base.state_offset +
 127                            offsetof(struct brw_wm_unit_state, wm9),
 128                            brw->wm.base.prog_offset +
 129                            prog_data->prog_offset_16 +
 130                            (wm->wm9.grf_reg_count_2 << 1)) >> 6;
 131    }
 132
 133    wm->thread1.depth_coef_urb_read_offset = 1;
 134    if (prog_data->base.use_alt_mode)
 135       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 136    else
 137       wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
 138
 139    wm->thread1.binding_table_entry_count =
 140       prog_data->base.binding_table.size_bytes / 4;
 141
 142    if (prog_data->base.total_scratch != 0) {
 143       wm->thread2.scratch_space_base_pointer =
 144          brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
 145       wm->thread2.per_thread_scratch_space =
 146          ffs(prog_data->base.total_scratch) - 11;
 147    } else {
 148       wm->thread2.scratch_space_base_pointer = 0;
 149       wm->thread2.per_thread_scratch_space = 0;
 150    }
 151
 152    wm->thread3.dispatch_grf_start_reg =
 153       prog_data->base.dispatch_grf_start_reg;
 154    wm->thread3.urb_entry_read_length =
 155       prog_data->num_varying_inputs * 2;
 156    wm->thread3.urb_entry_read_offset = 0;
 157    wm->thread3.const_urb_entry_read_length =
 158       prog_data->base.curb_read_length;
 159    /* BRW_NEW_CURBE_OFFSETS */
 160    wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2;
 161
 162    if (brw->gen == 5)
 163       wm->wm4.sampler_count = 0; /* hardware requirement */
 164    else {
 165       wm->wm4.sampler_count = (brw->wm.base.sampler_count + 1) / 4;
 166    }
 167
 168    if (brw->wm.base.sampler_count) {
 169       /* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
 170       wm->wm4.sampler_state_pointer = (brw->batch.bo->offset64 +
 171                                        brw->wm.base.sampler_offset) >> 5;
 172    } else {
 173       wm->wm4.sampler_state_pointer = 0;
 174    }
 175
 176    /* BRW_NEW_FRAGMENT_PROGRAM */
 177    wm->wm5.program_uses_depth = (fp->Base.InputsRead &
 178                                  (1 << VARYING_SLOT_POS)) != 0;
 179    wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
 180                                      BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
 181    /* _NEW_BUFFERS
 182     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 183     * Depth field.
 184     */
 185    if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH))
 186       wm->wm5.program_computes_depth = 0;
 187
 188    /* _NEW_COLOR */
 189    wm->wm5.program_uses_killpixel =
 190       prog_data->uses_kill || ctx->Color.AlphaEnabled;
 191
 192    wm->wm5.max_threads = brw->max_wm_threads - 1;
 193
 194    /* _NEW_BUFFERS | _NEW_COLOR */
 195    if (brw_color_buffer_write_enabled(brw) ||
 196        wm->wm5.program_uses_killpixel ||
 197        wm->wm5.program_computes_depth) {
 198       wm->wm5.thread_dispatch_enable = 1;
 199    }
 200
 201    wm->wm5.legacy_line_rast = 0;
 202    wm->wm5.legacy_global_depth_bias = 0;
 203    wm->wm5.early_depth_test = 1;                /* never need to disable */
 204    wm->wm5.line_aa_region_width = 0;
 205    wm->wm5.line_endcap_aa_region_width = 1;
 206
 207    /* _NEW_POLYGONSTIPPLE */
 208    wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag;
 209
 210    /* _NEW_POLYGON */
 211    if (ctx->Polygon.OffsetFill) {
 212       wm->wm5.depth_offset = 1;
 213       /* Something wierd going on with legacy_global_depth_bias,
 214        * offset_constant, scaling and MRD.  This value passes glean
 215        * but gives some odd results elsewere (eg. the
 216        * quad-offset-units test).
 217        */
 218       wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2;
 219
 220       /* This is the only value that passes glean:
 221        */
 222       wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor;
 223    }
 224
 225    /* _NEW_LINE */
 226    wm->wm5.line_stipple = ctx->Line.StippleFlag;
 227
 228    /* BRW_NEW_STATS_WM */
 229    if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm)
 230       wm->wm4.stats_enable = 1;
 231
 232    /* Emit scratch space relocation */
 233    if (prog_data->base.total_scratch != 0) {
 234       drm_intel_bo_emit_reloc(brw->batch.bo,
 235                               brw->wm.base.state_offset +
 236                               offsetof(struct brw_wm_unit_state, thread2),
 237                               brw->wm.base.scratch_bo,
 238                               wm->thread2.per_thread_scratch_space,
 239                               I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
 240    }
 241
 242    /* Emit sampler state relocation */
 243    if (brw->wm.base.sampler_count != 0) {
 244       drm_intel_bo_emit_reloc(brw->batch.bo,
 245                               brw->wm.base.state_offset +
 246                               offsetof(struct brw_wm_unit_state, wm4),
 247                               brw->batch.bo, (brw->wm.base.sampler_offset |
 248                                               wm->wm4.stats_enable |
 249                                               (wm->wm4.sampler_count << 2)),
 250                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 251    }
 252
 253    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 254 }
 255
 256 const struct brw_tracked_state brw_wm_unit = {
 257    .dirty = {
 258       .mesa = _NEW_BUFFERS |
 259               _NEW_COLOR |
 260               _NEW_LINE |
 261               _NEW_POLYGON |
 262               _NEW_POLYGONSTIPPLE,
 263       .brw = BRW_NEW_BATCH |
 264              BRW_NEW_CURBE_OFFSETS |
 265              BRW_NEW_FRAGMENT_PROGRAM |
 266              BRW_NEW_FS_PROG_DATA |
 267              BRW_NEW_PROGRAM_CACHE |
 268              BRW_NEW_SAMPLER_STATE_TABLE |
 269              BRW_NEW_STATS_WM,
 270    },
 271    .emit = brw_upload_wm_unit,
 272 };
 273