src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texstore.h"
  35 #include "shader/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( gl_format mesa_format,
  73                                     GLenum internal_format,
  74                                     GLenum depth_mode )
  75 {
  76    switch( mesa_format ) {
  77    case MESA_FORMAT_L8:
  78       return BRW_SURFACEFORMAT_L8_UNORM;
  79
  80    case MESA_FORMAT_I8:
  81       return BRW_SURFACEFORMAT_I8_UNORM;
  82
  83    case MESA_FORMAT_A8:
  84       return BRW_SURFACEFORMAT_A8_UNORM;
  85
  86    case MESA_FORMAT_AL88:
  87       return BRW_SURFACEFORMAT_L8A8_UNORM;
  88
  89    case MESA_FORMAT_AL1616:
  90       return BRW_SURFACEFORMAT_L16A16_UNORM;
  91
  92    case MESA_FORMAT_RGB888:
  93       assert(0);                /* not supported for sampling */
  94       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
  95
  96    case MESA_FORMAT_ARGB8888:
  97       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
  98
  99    case MESA_FORMAT_XRGB8888:
 100       return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 101
 102    case MESA_FORMAT_RGBA8888_REV:
 103       _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
 104       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 105
 106    case MESA_FORMAT_RGB565:
 107       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
 108
 109    case MESA_FORMAT_ARGB1555:
 110       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 111
 112    case MESA_FORMAT_ARGB4444:
 113       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 114
 115    case MESA_FORMAT_YCBCR_REV:
 116       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 117
 118    case MESA_FORMAT_YCBCR:
 119       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 120
 121    case MESA_FORMAT_RGB_FXT1:
 122    case MESA_FORMAT_RGBA_FXT1:
 123       return BRW_SURFACEFORMAT_FXT1;
 124
 125    case MESA_FORMAT_Z16:
 126       if (depth_mode == GL_INTENSITY)
 127           return BRW_SURFACEFORMAT_I16_UNORM;
 128       else if (depth_mode == GL_ALPHA)
 129           return BRW_SURFACEFORMAT_A16_UNORM;
 130       else
 131           return BRW_SURFACEFORMAT_L16_UNORM;
 132
 133    case MESA_FORMAT_RGB_DXT1:
 134        return BRW_SURFACEFORMAT_DXT1_RGB;
 135
 136    case MESA_FORMAT_RGBA_DXT1:
 137        return BRW_SURFACEFORMAT_BC1_UNORM;
 138
 139    case MESA_FORMAT_RGBA_DXT3:
 140        return BRW_SURFACEFORMAT_BC2_UNORM;
 141
 142    case MESA_FORMAT_RGBA_DXT5:
 143        return BRW_SURFACEFORMAT_BC3_UNORM;
 144
 145    case MESA_FORMAT_SARGB8:
 146       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 147
 148    case MESA_FORMAT_SLA8:
 149       return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
 150
 151    case MESA_FORMAT_SL8:
 152       return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
 153
 154    case MESA_FORMAT_SRGB_DXT1:
 155       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 156
 157    case MESA_FORMAT_S8_Z24:
 158       /* XXX: these different surface formats don't seem to
 159        * make any difference for shadow sampler/compares.
 160        */
 161       if (depth_mode == GL_INTENSITY)
 162          return BRW_SURFACEFORMAT_I24X8_UNORM;
 163       else if (depth_mode == GL_ALPHA)
 164          return BRW_SURFACEFORMAT_A24X8_UNORM;
 165       else
 166          return BRW_SURFACEFORMAT_L24X8_UNORM;
 167
 168    case MESA_FORMAT_DUDV8:
 169       return BRW_SURFACEFORMAT_R8G8_SNORM;
 170
 171    case MESA_FORMAT_SIGNED_RGBA8888_REV:
 172       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 173
 174    default:
 175       assert(0);
 176       return 0;
 177    }
 178 }
 179
 180 static void
 181 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 182 {
 183    switch (tiling) {
 184    case I915_TILING_NONE:
 185       surf->ss3.tiled_surface = 0;
 186       surf->ss3.tile_walk = 0;
 187       break;
 188    case I915_TILING_X:
 189       surf->ss3.tiled_surface = 1;
 190       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 191       break;
 192    case I915_TILING_Y:
 193       surf->ss3.tiled_surface = 1;
 194       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 195       break;
 196    }
 197 }
 198
 199 static dri_bo *
 200 brw_create_texture_surface( struct brw_context *brw,
 201                             struct brw_surface_key *key )
 202 {
 203    struct brw_surface_state surf;
 204    dri_bo *bo;
 205
 206    memset(&surf, 0, sizeof(surf));
 207
 208    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 209    surf.ss0.surface_type = translate_tex_target(key->target);
 210    if (key->bo) {
 211       surf.ss0.surface_format = translate_tex_format(key->format,
 212                                                      key->internal_format,
 213                                                      key->depthmode);
 214    }
 215    else {
 216       switch (key->depth) {
 217       case 32:
 218          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 219          break;
 220       default:
 221       case 24:
 222          surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 223          break;
 224       case 16:
 225          surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 226          break;
 227       }
 228    }
 229
 230    /* This is ok for all textures with channel width 8bit or less:
 231     */
 232 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 233    if (key->bo)
 234       surf.ss1.base_addr = key->bo->offset; /* reloc */
 235    else
 236       surf.ss1.base_addr = key->offset;
 237
 238    surf.ss2.mip_count = key->last_level - key->first_level;
 239    surf.ss2.width = key->width - 1;
 240    surf.ss2.height = key->height - 1;
 241    brw_set_surface_tiling(&surf, key->tiling);
 242    surf.ss3.pitch = (key->pitch * key->cpp) - 1;
 243    surf.ss3.depth = key->depth - 1;
 244
 245    surf.ss4.min_lod = 0;
 246
 247    if (key->target == GL_TEXTURE_CUBE_MAP) {
 248       surf.ss0.cube_pos_x = 1;
 249       surf.ss0.cube_pos_y = 1;
 250       surf.ss0.cube_pos_z = 1;
 251       surf.ss0.cube_neg_x = 1;
 252       surf.ss0.cube_neg_y = 1;
 253       surf.ss0.cube_neg_z = 1;
 254    }
 255
 256    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 257                          key, sizeof(*key),
 258                          &key->bo, key->bo ? 1 : 0,
 259                          &surf, sizeof(surf));
 260
 261    if (key->bo) {
 262       /* Emit relocation to surface contents */
 263       dri_bo_emit_reloc(bo,
 264                         I915_GEM_DOMAIN_SAMPLER, 0,
 265                         0,
 266                         offsetof(struct brw_surface_state, ss1),
 267                         key->bo);
 268    }
 269    return bo;
 270 }
 271
 272 static void
 273 brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 274 {
 275    struct brw_context *brw = brw_context(ctx);
 276    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 277    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 278    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 279    struct brw_surface_key key;
 280    const GLuint surf = SURF_INDEX_TEXTURE(unit);
 281
 282    memset(&key, 0, sizeof(key));
 283
 284    if (intelObj->imageOverride) {
 285       key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
 286       key.depth = intelObj->depthOverride;
 287       key.bo = NULL;
 288       key.offset = intelObj->textureOffset;
 289    } else {
 290       key.format = firstImage->TexFormat;
 291       key.internal_format = firstImage->InternalFormat;
 292       key.pitch = intelObj->mt->pitch;
 293       key.depth = firstImage->Depth;
 294       key.bo = intelObj->mt->region->buffer;
 295       key.offset = 0;
 296    }
 297
 298    key.target = tObj->Target;
 299    key.depthmode = tObj->DepthMode;
 300    key.first_level = intelObj->firstLevel;
 301    key.last_level = intelObj->lastLevel;
 302    key.width = firstImage->Width;
 303    key.height = firstImage->Height;
 304    key.cpp = intelObj->mt->cpp;
 305    key.tiling = intelObj->mt->region->tiling;
 306
 307    dri_bo_unreference(brw->wm.surf_bo[surf]);
 308    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 309                                             BRW_SS_SURFACE,
 310                                             &key, sizeof(key),
 311                                             &key.bo, key.bo ? 1 : 0,
 312                                             NULL);
 313    if (brw->wm.surf_bo[surf] == NULL) {
 314       brw->wm.surf_bo[surf] = brw_create_texture_surface(brw, &key);
 315    }
 316 }
 317
 318
 319
 320 /**
 321  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 322  * read from this buffer with Data Port Read instructions/messages.
 323  */
 324 dri_bo *
 325 brw_create_constant_surface( struct brw_context *brw,
 326                              struct brw_surface_key *key )
 327 {
 328    const GLint w = key->width - 1;
 329    struct brw_surface_state surf;
 330    dri_bo *bo;
 331
 332    memset(&surf, 0, sizeof(surf));
 333
 334    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 335    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 336    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 337
 338    assert(key->bo);
 339    if (key->bo)
 340       surf.ss1.base_addr = key->bo->offset; /* reloc */
 341    else
 342       surf.ss1.base_addr = key->offset;
 343
 344    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 345    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 346    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 347    surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */
 348    brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
 349
 350    bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
 351                          key, sizeof(*key),
 352                          &key->bo, key->bo ? 1 : 0,
 353                          &surf, sizeof(surf));
 354
 355    if (key->bo) {
 356       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 357        * bspec ("Data Cache") says that the data cache does not exist as
 358        * a separate cache and is just the sampler cache.
 359        */
 360       dri_bo_emit_reloc(bo,
 361                         I915_GEM_DOMAIN_SAMPLER, 0,
 362                         0,
 363                         offsetof(struct brw_surface_state, ss1),
 364                         key->bo);
 365    }
 366
 367    return bo;
 368 }
 369
 370 /* Creates a new WM constant buffer reflecting the current fragment program's
 371  * constants, if needed by the fragment program.
 372  *
 373  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 374  * state atom.
 375  */
 376 static drm_intel_bo *
 377 brw_wm_update_constant_buffer(struct brw_context *brw)
 378 {
 379    struct intel_context *intel = &brw->intel;
 380    struct brw_fragment_program *fp =
 381       (struct brw_fragment_program *) brw->fragment_program;
 382    const struct gl_program_parameter_list *params = fp->program.Base.Parameters;
 383    const int size = params->NumParameters * 4 * sizeof(GLfloat);
 384    drm_intel_bo *const_buffer;
 385
 386    /* BRW_NEW_FRAGMENT_PROGRAM */
 387    if (!fp->use_const_buffer)
 388       return NULL;
 389
 390    const_buffer = drm_intel_bo_alloc(intel->bufmgr, "fp_const_buffer",
 391                                      size, 64);
 392
 393    /* _NEW_PROGRAM_CONSTANTS */
 394    dri_bo_subdata(const_buffer, 0, size, params->ParameterValues);
 395
 396    return const_buffer;
 397 }
 398
 399 /**
 400  * Update the surface state for a WM constant buffer.
 401  * The constant buffer will be (re)allocated here if needed.
 402  */
 403 static void
 404 brw_update_wm_constant_surface( GLcontext *ctx,
 405                                 GLuint surf)
 406 {
 407    struct brw_context *brw = brw_context(ctx);
 408    struct brw_surface_key key;
 409    struct brw_fragment_program *fp =
 410       (struct brw_fragment_program *) brw->fragment_program;
 411    const struct gl_program_parameter_list *params =
 412       fp->program.Base.Parameters;
 413
 414    /* If we're in this state update atom, we need to update WM constants, so
 415     * free the old buffer and create a new one for the new contents.
 416     */
 417    dri_bo_unreference(fp->const_buffer);
 418    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 419
 420    /* If there's no constant buffer, then no surface BO is needed to point at
 421     * it.
 422     */
 423    if (fp->const_buffer == 0) {
 424       drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 425       brw->wm.surf_bo[surf] = NULL;
 426       return;
 427    }
 428
 429    memset(&key, 0, sizeof(key));
 430
 431    key.format = MESA_FORMAT_RGBA_FLOAT32;
 432    key.internal_format = GL_RGBA;
 433    key.bo = fp->const_buffer;
 434    key.depthmode = GL_NONE;
 435    key.pitch = params->NumParameters;
 436    key.width = params->NumParameters;
 437    key.height = 1;
 438    key.depth = 1;
 439    key.cpp = 16;
 440
 441    /*
 442    printf("%s:\n", __FUNCTION__);
 443    printf("  width %d  height %d  depth %d  cpp %d  pitch %d\n",
 444           key.width, key.height, key.depth, key.cpp, key.pitch);
 445    */
 446
 447    dri_bo_unreference(brw->wm.surf_bo[surf]);
 448    brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
 449                                             BRW_SS_SURFACE,
 450                                             &key, sizeof(key),
 451                                             &key.bo, key.bo ? 1 : 0,
 452                                             NULL);
 453    if (brw->wm.surf_bo[surf] == NULL) {
 454       brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
 455    }
 456    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 457 }
 458
 459 /**
 460  * Updates surface / buffer for fragment shader constant buffer, if
 461  * one is required.
 462  *
 463  * This consumes the state updates for the constant buffer, and produces
 464  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 465  * inclusion in the binding table.
 466  */
 467 static void prepare_wm_constant_surface(struct brw_context *brw )
 468 {
 469    GLcontext *ctx = &brw->intel.ctx;
 470    struct brw_fragment_program *fp =
 471       (struct brw_fragment_program *) brw->fragment_program;
 472    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 473
 474    drm_intel_bo_unreference(fp->const_buffer);
 475    fp->const_buffer = brw_wm_update_constant_buffer(brw);
 476
 477    /* If there's no constant buffer, then no surface BO is needed to point at
 478     * it.
 479     */
 480    if (fp->const_buffer == 0) {
 481       if (brw->wm.surf_bo[surf] != NULL) {
 482          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 483          brw->wm.surf_bo[surf] = NULL;
 484          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 485       }
 486       return;
 487    }
 488
 489    brw_update_wm_constant_surface(ctx, surf);
 490 }
 491
 492 const struct brw_tracked_state brw_wm_constant_surface = {
 493    .dirty = {
 494       .mesa = (_NEW_PROGRAM_CONSTANTS),
 495       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 496       .cache = 0
 497    },
 498    .prepare = prepare_wm_constant_surface,
 499 };
 500
 501
 502 /**
 503  * Sets up a surface state structure to point at the given region.
 504  * While it is only used for the front/back buffer currently, it should be
 505  * usable for further buffers when doing ARB_draw_buffer support.
 506  */
 507 static void
 508 brw_update_renderbuffer_surface(struct brw_context *brw,
 509                                 struct gl_renderbuffer *rb,
 510                                 unsigned int unit)
 511 {
 512    struct intel_context *intel = &brw->intel;;
 513    GLcontext *ctx = &intel->ctx;
 514    dri_bo *region_bo = NULL;
 515    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 516    struct intel_region *region = irb ? irb->region : NULL;
 517    struct {
 518       unsigned int surface_type;
 519       unsigned int surface_format;
 520       unsigned int width, height, pitch, cpp;
 521       GLubyte color_mask[4];
 522       GLboolean color_blend;
 523       uint32_t tiling;
 524       uint32_t draw_x;
 525       uint32_t draw_y;
 526    } key;
 527
 528    memset(&key, 0, sizeof(key));
 529
 530    if (region != NULL) {
 531       region_bo = region->buffer;
 532
 533       key.surface_type = BRW_SURFACE_2D;
 534       switch (irb->Base.Format) {
 535       /* XRGB and ARGB are treated the same here because the chips in this
 536        * family cannot render to XRGB targets.  This means that we have to
 537        * mask writes to alpha (ala glColorMask) and reconfigure the alpha
 538        * blending hardware to use GL_ONE (or GL_ZERO) for cases where
 539        * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
 540        */
 541       case MESA_FORMAT_ARGB8888:
 542       case MESA_FORMAT_XRGB8888:
 543          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 544          break;
 545       case MESA_FORMAT_RGB565:
 546          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 547          break;
 548       case MESA_FORMAT_ARGB1555:
 549          key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 550          break;
 551       case MESA_FORMAT_ARGB4444:
 552          key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 553          break;
 554       default:
 555          _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format);
 556       }
 557       key.tiling = region->tiling;
 558       if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) {
 559          key.width = rb->Width;
 560          key.height = rb->Height;
 561       } else {
 562          key.width = region->width;
 563          key.height = region->height;
 564       }
 565       key.pitch = region->pitch;
 566       key.cpp = region->cpp;
 567       key.draw_x = region->draw_x;
 568       key.draw_y = region->draw_y;
 569    } else {
 570       key.surface_type = BRW_SURFACE_NULL;
 571       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 572       key.tiling = I915_TILING_X;
 573       key.width = 1;
 574       key.height = 1;
 575       key.cpp = 4;
 576       key.draw_x = 0;
 577       key.draw_y = 0;
 578    }
 579    /* _NEW_COLOR */
 580    memcpy(key.color_mask, ctx->Color.ColorMask[0],
 581           sizeof(key.color_mask));
 582
 583    /* As mentioned above, disable writes to the alpha component when the
 584     * renderbuffer is XRGB.
 585     */
 586    if (ctx->DrawBuffer->Visual.alphaBits == 0)
 587      key.color_mask[3] = GL_FALSE;
 588
 589    key.color_blend = (!ctx->Color._LogicOpEnabled &&
 590                       ctx->Color.BlendEnabled);
 591
 592    dri_bo_unreference(brw->wm.surf_bo[unit]);
 593    brw->wm.surf_bo[unit] = brw_search_cache(&brw->surface_cache,
 594                                             BRW_SS_SURFACE,
 595                                             &key, sizeof(key),
 596                                             &region_bo, 1,
 597                                             NULL);
 598
 599    if (brw->wm.surf_bo[unit] == NULL) {
 600       struct brw_surface_state surf;
 601
 602       memset(&surf, 0, sizeof(surf));
 603
 604       surf.ss0.surface_format = key.surface_format;
 605       surf.ss0.surface_type = key.surface_type;
 606       if (key.tiling == I915_TILING_NONE) {
 607          surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp;
 608       } else {
 609          uint32_t tile_base, tile_x, tile_y;
 610          uint32_t pitch = key.pitch * key.cpp;
 611
 612          if (key.tiling == I915_TILING_X) {
 613             tile_x = key.draw_x % (512 / key.cpp);
 614             tile_y = key.draw_y % 8;
 615             tile_base = ((key.draw_y / 8) * (8 * pitch));
 616             tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096;
 617          } else {
 618             /* Y */
 619             tile_x = key.draw_x % (128 / key.cpp);
 620             tile_y = key.draw_y % 32;
 621             tile_base = ((key.draw_y / 32) * (32 * pitch));
 622             tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
 623          }
 624          assert(intel->is_g4x || (tile_x == 0 && tile_y == 0));
 625          assert(tile_x % 4 == 0);
 626          assert(tile_y % 2 == 0);
 627          /* Note that the low bits of these fields are missing, so
 628           * there's the possibility of getting in trouble.
 629           */
 630          surf.ss1.base_addr = tile_base;
 631          surf.ss5.x_offset = tile_x / 4;
 632          surf.ss5.y_offset = tile_y / 2;
 633       }
 634       if (region_bo != NULL)
 635          surf.ss1.base_addr += region_bo->offset; /* reloc */
 636
 637       surf.ss2.width = key.width - 1;
 638       surf.ss2.height = key.height - 1;
 639       brw_set_surface_tiling(&surf, key.tiling);
 640       surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 641
 642       /* _NEW_COLOR */
 643       surf.ss0.color_blend = key.color_blend;
 644       surf.ss0.writedisable_red =   !key.color_mask[0];
 645       surf.ss0.writedisable_green = !key.color_mask[1];
 646       surf.ss0.writedisable_blue =  !key.color_mask[2];
 647       surf.ss0.writedisable_alpha = !key.color_mask[3];
 648
 649       /* Key size will never match key size for textures, so we're safe. */
 650       brw->wm.surf_bo[unit] = brw_upload_cache(&brw->surface_cache,
 651                                                BRW_SS_SURFACE,
 652                                                &key, sizeof(key),
 653                                                &region_bo, 1,
 654                                                &surf, sizeof(surf));
 655       if (region_bo != NULL) {
 656          /* We might sample from it, and we might render to it, so flag
 657           * them both.  We might be able to figure out from other state
 658           * a more restrictive relocation to emit.
 659           */
 660          drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 661                                  offsetof(struct brw_surface_state, ss1),
 662                                  region_bo,
 663                                  surf.ss1.base_addr - region_bo->offset,
 664                                  I915_GEM_DOMAIN_RENDER,
 665                                  I915_GEM_DOMAIN_RENDER);
 666       }
 667    }
 668 }
 669
 670
 671 /**
 672  * Constructs the binding table for the WM surface state, which maps unit
 673  * numbers to surface state objects.
 674  */
 675 static dri_bo *
 676 brw_wm_get_binding_table(struct brw_context *brw)
 677 {
 678    dri_bo *bind_bo;
 679
 680    assert(brw->wm.nr_surfaces <= BRW_WM_MAX_SURF);
 681
 682    bind_bo = brw_search_cache(&brw->surface_cache, BRW_SS_SURF_BIND,
 683                               NULL, 0,
 684                               brw->wm.surf_bo, brw->wm.nr_surfaces,
 685                               NULL);
 686
 687    if (bind_bo == NULL) {
 688       GLuint data_size = brw->wm.nr_surfaces * sizeof(GLuint);
 689       uint32_t data[BRW_WM_MAX_SURF];
 690       int i;
 691
 692       for (i = 0; i < brw->wm.nr_surfaces; i++)
 693          if (brw->wm.surf_bo[i])
 694             data[i] = brw->wm.surf_bo[i]->offset;
 695          else
 696             data[i] = 0;
 697
 698       bind_bo = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
 699                                   NULL, 0,
 700                                   brw->wm.surf_bo, brw->wm.nr_surfaces,
 701                                   data, data_size);
 702
 703       /* Emit binding table relocations to surface state */
 704       for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 705          if (brw->wm.surf_bo[i] != NULL) {
 706             dri_bo_emit_reloc(bind_bo,
 707                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 708                               0,
 709                               i * sizeof(GLuint),
 710                               brw->wm.surf_bo[i]);
 711          }
 712       }
 713    }
 714
 715    return bind_bo;
 716 }
 717
 718 static void prepare_wm_surfaces(struct brw_context *brw )
 719 {
 720    GLcontext *ctx = &brw->intel.ctx;
 721    GLuint i;
 722    int old_nr_surfaces;
 723
 724    /* _NEW_BUFFERS | _NEW_COLOR */
 725    /* Update surfaces for drawing buffers */
 726    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 727       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 728          brw_update_renderbuffer_surface(brw,
 729                                          ctx->DrawBuffer->_ColorDrawBuffers[i],
 730                                          i);
 731       }
 732    } else {
 733       brw_update_renderbuffer_surface(brw, NULL, 0);
 734    }
 735
 736    old_nr_surfaces = brw->wm.nr_surfaces;
 737    brw->wm.nr_surfaces = BRW_MAX_DRAW_BUFFERS;
 738
 739    if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL)
 740        brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 741
 742    /* Update surfaces for textures */
 743    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 744       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 745       const GLuint surf = SURF_INDEX_TEXTURE(i);
 746
 747       /* _NEW_TEXTURE, BRW_NEW_TEXDATA */
 748       if (texUnit->_ReallyEnabled) {
 749          brw_update_texture_surface(ctx, i);
 750          brw->wm.nr_surfaces = surf + 1;
 751       } else {
 752          dri_bo_unreference(brw->wm.surf_bo[surf]);
 753          brw->wm.surf_bo[surf] = NULL;
 754       }
 755    }
 756
 757    dri_bo_unreference(brw->wm.bind_bo);
 758    brw->wm.bind_bo = brw_wm_get_binding_table(brw);
 759
 760    if (brw->wm.nr_surfaces != old_nr_surfaces)
 761       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 762 }
 763
 764 const struct brw_tracked_state brw_wm_surfaces = {
 765    .dirty = {
 766       .mesa = (_NEW_COLOR |
 767                _NEW_TEXTURE |
 768                _NEW_BUFFERS),
 769       .brw = (BRW_NEW_CONTEXT |
 770               BRW_NEW_WM_SURFACES),
 771       .cache = 0
 772    },
 773    .prepare = prepare_wm_surfaces,
 774 };
 775
 776
 777