src/mesa/drivers/dri/i965/gen6_urb.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "main/macros.h"
  29 #include "intel_batchbuffer.h"
  30 #include "brw_context.h"
  31 #include "brw_state.h"
  32 #include "brw_defines.h"
  33
  34 static void
  35 prepare_urb( struct brw_context *brw )
  36 {
  37    brw->urb.nr_vs_entries = 24;
  38    if (brw->gs.prog_bo)
  39       brw->urb.nr_gs_entries = 4;
  40    else
  41       brw->urb.nr_gs_entries = 0;
  42    /* CACHE_NEW_VS_PROG */
  43    brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1);
  44
  45    /* Check that the number of URB rows (8 floats each) allocated is less
  46     * than the URB space.
  47     */
  48    assert((brw->urb.nr_vs_entries +
  49            brw->urb.nr_gs_entries) * brw->urb.vs_size * 8 < 64 * 1024);
  50 }
  51
  52 static void
  53 upload_urb(struct brw_context *brw)
  54 {
  55    struct intel_context *intel = &brw->intel;
  56
  57    assert(brw->urb.nr_vs_entries % 4 == 0);
  58    assert(brw->urb.nr_gs_entries % 4 == 0);
  59    /* GS requirement */
  60    assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
  61
  62    BEGIN_BATCH(3);
  63    OUT_BATCH(CMD_URB << 16 | (3 - 2));
  64    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
  65              ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
  66    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |
  67              ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT));
  68    ADVANCE_BATCH();
  69 }
  70
  71 const struct brw_tracked_state gen6_urb = {
  72    .dirty = {
  73       .mesa = 0,
  74       .brw = BRW_NEW_CONTEXT,
  75       .cache = CACHE_NEW_VS_PROG,
  76    },
  77    .prepare = prepare_urb,
  78    .emit = upload_urb,
  79 };