src/mesa/drivers/dri/i965/gen7_blorp.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_state.h"
  31
  32 #include "brw_blorp.h"
  33
  34 /* Once vertex fetcher has written full VUE entries with complete
  35  * header the space requirement is as follows per vertex (in bytes):
  36  *
  37  *     Header    Position    Program constants
  38  *   +--------+------------+-------------------+
  39  *   |   16   |     16     |      n x 16       |
  40  *   +--------+------------+-------------------+
  41  *
  42  * where 'n' stands for number of varying inputs expressed as vec4s.
  43  *
  44  * The URB size is in turn expressed in 64 bytes (512 bits).
  45  */
  46 static unsigned
  47 gen7_blorp_get_vs_entry_size(const struct brw_blorp_params *params)
  48 {
  49     const unsigned num_varyings =
  50        params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
  51     const unsigned total_needed = 16 + 16 + num_varyings * 16;
  52
  53    return DIV_ROUND_UP(total_needed, 64);
  54 }
  55
  56 /* 3DSTATE_URB_VS
  57  * 3DSTATE_URB_HS
  58  * 3DSTATE_URB_DS
  59  * 3DSTATE_URB_GS
  60  *
  61  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  62  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  63  *
  64  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  65  *     programmed in order for the programming of this state to be
  66  *     valid.
  67  */
  68 void
  69 gen7_blorp_emit_urb_config(struct brw_context *brw,
  70                            const struct brw_blorp_params *params)
  71 {
  72    const unsigned vs_entry_size = gen7_blorp_get_vs_entry_size(params);
  73
  74    if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
  75        brw->urb.vsize >= vs_entry_size)
  76       return;
  77
  78    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
  79
  80    gen7_upload_urb(brw, vs_entry_size, false, false);
  81 }
  82
  83
  84 /* 3DSTATE_BLEND_STATE_POINTERS */
  85 void
  86 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  87                                     uint32_t cc_blend_state_offset)
  88 {
  89    BEGIN_BATCH(2);
  90    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  91    OUT_BATCH(cc_blend_state_offset | 1);
  92    ADVANCE_BATCH();
  93 }
  94
  95
  96 /* 3DSTATE_CC_STATE_POINTERS */
  97 void
  98 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  99                                  uint32_t cc_state_offset)
 100 {
 101    BEGIN_BATCH(2);
 102    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 103    OUT_BATCH(cc_state_offset | 1);
 104    ADVANCE_BATCH();
 105 }
 106
 107 void
 108 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
 109 {
 110    struct brw_cc_viewport *ccv;
 111    uint32_t cc_vp_offset;
 112
 113    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 114                                                    sizeof(*ccv), 32,
 115                                                    &cc_vp_offset);
 116    ccv->min_depth = 0.0;
 117    ccv->max_depth = 1.0;
 118
 119    BEGIN_BATCH(2);
 120    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 121    OUT_BATCH(cc_vp_offset);
 122    ADVANCE_BATCH();
 123 }
 124
 125
 126 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 127  *
 128  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 129  */
 130 static void
 131 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 132                                              uint32_t depthstencil_offset)
 133 {
 134    BEGIN_BATCH(2);
 135    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 136    OUT_BATCH(depthstencil_offset | 1);
 137    ADVANCE_BATCH();
 138 }
 139
 140
 141 /* SURFACE_STATE for renderbuffer or texture surface (see
 142  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 143  */
 144 static uint32_t
 145 gen7_blorp_emit_surface_state(struct brw_context *brw,
 146                               const struct brw_blorp_surface_info *surface,
 147                               uint32_t read_domains, uint32_t write_domain,
 148                               bool is_render_target)
 149 {
 150    uint32_t wm_surf_offset;
 151    uint32_t width = surface->width;
 152    uint32_t height = surface->height;
 153    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 154     * color surfaces, width and height are measured in pixels; we don't need
 155     * to divide them by 2 as we do for Gen6 (see
 156     * gen6_blorp_emit_surface_state).
 157     */
 158    struct intel_mipmap_tree *mt = surface->mt;
 159    uint32_t tile_x, tile_y;
 160    const uint8_t mocs = GEN7_MOCS_L3;
 161
 162    uint32_t tiling = surface->map_stencil_as_y_tiled
 163       ? I915_TILING_Y : mt->tiling;
 164
 165    uint32_t *surf = (uint32_t *)
 166       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 167    memset(surf, 0, 8 * 4);
 168
 169    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 170              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 171              gen7_surface_tiling_mode(tiling);
 172
 173    if (surface->mt->valign == 4)
 174       surf[0] |= GEN7_SURFACE_VALIGN_4;
 175    if (surface->mt->halign == 8)
 176       surf[0] |= GEN7_SURFACE_HALIGN_8;
 177
 178    if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
 179       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 180    else
 181       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 182
 183    /* reloc */
 184    surf[1] = brw_blorp_compute_tile_offsets(surface, &tile_x, &tile_y) +
 185              mt->bo->offset64;
 186
 187    /* Note that the low bits of these fields are missing, so
 188     * there's the possibility of getting in trouble.
 189     */
 190    assert(tile_x % 4 == 0);
 191    assert(tile_y % 2 == 0);
 192    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 193              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 194              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 195
 196    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 197              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 198
 199    uint32_t pitch_bytes = mt->pitch;
 200    if (surface->map_stencil_as_y_tiled)
 201       pitch_bytes *= 2;
 202    surf[3] = pitch_bytes - 1;
 203
 204    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 205    if (surface->mt->mcs_mt) {
 206       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 207                                 is_render_target);
 208    }
 209
 210    surf[7] = surface->mt->fast_clear_color_value;
 211
 212    if (brw->is_haswell) {
 213       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 214                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 215                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 216                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 217    }
 218
 219    /* Emit relocation to surface contents */
 220    drm_intel_bo_emit_reloc(brw->batch.bo,
 221                            wm_surf_offset + 4,
 222                            mt->bo,
 223                            surf[1] - mt->bo->offset64,
 224                            read_domains, write_domain);
 225
 226    gen7_check_surface_setup(surf, is_render_target);
 227
 228    return wm_surf_offset;
 229 }
 230
 231
 232 /* 3DSTATE_VS
 233  *
 234  * Disable vertex shader.
 235  */
 236 static void
 237 gen7_blorp_emit_vs_disable(struct brw_context *brw)
 238 {
 239    BEGIN_BATCH(6);
 240    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 241    OUT_BATCH(0);
 242    OUT_BATCH(0);
 243    OUT_BATCH(0);
 244    OUT_BATCH(0);
 245    OUT_BATCH(0);
 246    ADVANCE_BATCH();
 247 }
 248
 249
 250 /* 3DSTATE_HS
 251  *
 252  * Disable the hull shader.
 253  */
 254 static void
 255 gen7_blorp_emit_hs_disable(struct brw_context *brw)
 256 {
 257    BEGIN_BATCH(7);
 258    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 259    OUT_BATCH(0);
 260    OUT_BATCH(0);
 261    OUT_BATCH(0);
 262    OUT_BATCH(0);
 263    OUT_BATCH(0);
 264    OUT_BATCH(0);
 265    ADVANCE_BATCH();
 266 }
 267
 268
 269 /* 3DSTATE_TE
 270  *
 271  * Disable the tesselation engine.
 272  */
 273 void
 274 gen7_blorp_emit_te_disable(struct brw_context *brw)
 275 {
 276    BEGIN_BATCH(4);
 277    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 278    OUT_BATCH(0);
 279    OUT_BATCH(0);
 280    OUT_BATCH(0);
 281    ADVANCE_BATCH();
 282 }
 283
 284
 285 /* 3DSTATE_DS
 286  *
 287  * Disable the domain shader.
 288  */
 289 static void
 290 gen7_blorp_emit_ds_disable(struct brw_context *brw)
 291 {
 292    BEGIN_BATCH(6);
 293    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 294    OUT_BATCH(0);
 295    OUT_BATCH(0);
 296    OUT_BATCH(0);
 297    OUT_BATCH(0);
 298    OUT_BATCH(0);
 299    ADVANCE_BATCH();
 300 }
 301
 302 /* 3DSTATE_GS
 303  *
 304  * Disable the geometry shader.
 305  */
 306 static void
 307 gen7_blorp_emit_gs_disable(struct brw_context *brw)
 308 {
 309    /**
 310     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 311     * Geometry > Geometry Shader > State:
 312     *
 313     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 314     *     whole fixed function pipeline when the GS enable changes value in
 315     *     the 3DSTATE_GS."
 316     *
 317     * The hardware architects have clarified that in this context "flush the
 318     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 319     * Stall" bit set.
 320     */
 321    if (brw->gen < 8 && !brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 322       gen7_emit_cs_stall_flush(brw);
 323
 324    BEGIN_BATCH(7);
 325    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 326    OUT_BATCH(0);
 327    OUT_BATCH(0);
 328    OUT_BATCH(0);
 329    OUT_BATCH(0);
 330    OUT_BATCH(0);
 331    OUT_BATCH(0);
 332    ADVANCE_BATCH();
 333    brw->gs.enabled = false;
 334 }
 335
 336 /* 3DSTATE_STREAMOUT
 337  *
 338  * Disable streamout.
 339  */
 340 static void
 341 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 342 {
 343    BEGIN_BATCH(3);
 344    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 345    OUT_BATCH(0);
 346    OUT_BATCH(0);
 347    ADVANCE_BATCH();
 348 }
 349
 350
 351 static void
 352 gen7_blorp_emit_sf_config(struct brw_context *brw,
 353                           const struct brw_blorp_params *params)
 354 {
 355    /* 3DSTATE_SF
 356     *
 357     * Disable ViewportTransformEnable (dw1.1)
 358     *
 359     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 360     * Primitives Overview":
 361     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 362     *     use of screen- space coordinates).
 363     *
 364     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 365     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 366     *
 367     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 368     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 369     *     SOLID: Any triangle or rectangle object found to be front-facing
 370     *     is rendered as a solid object. This setting is required when
 371     *     (rendering rectangle (RECTLIST) objects.
 372     */
 373    {
 374       BEGIN_BATCH(7);
 375       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 376       OUT_BATCH(params->depth_format <<
 377                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 378       OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 379       OUT_BATCH(0);
 380       OUT_BATCH(0);
 381       OUT_BATCH(0);
 382       OUT_BATCH(0);
 383       ADVANCE_BATCH();
 384    }
 385
 386    /* 3DSTATE_SBE */
 387    {
 388       const unsigned num_varyings =
 389          params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
 390       const unsigned urb_read_length =
 391          brw_blorp_get_urb_length(params->wm_prog_data);
 392
 393       BEGIN_BATCH(14);
 394       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 395
 396       /* There is no need for swizzling (GEN7_SBE_SWIZZLE_ENABLE). All the
 397        * vertex data coming from vertex fetcher is taken as unmodified
 398        * (i.e., passed through). Vertex shader state is disabled and vertex
 399        * fetcher builds complete vertex entries including VUE header.
 400        * This is for unknown reason really needed to be disabled when more
 401        * than one vec4 worth of vertex attributes are needed.
 402        */
 403       OUT_BATCH(num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 404                 urb_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 405                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 406                    GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 407       for (int i = 0; i < 9; ++i)
 408          OUT_BATCH(0);
 409       OUT_BATCH(params->wm_prog_data ? params->wm_prog_data->flat_inputs : 0);
 410       OUT_BATCH(0);
 411       OUT_BATCH(0);
 412       ADVANCE_BATCH();
 413    }
 414 }
 415
 416
 417 /**
 418  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 419  */
 420 static void
 421 gen7_blorp_emit_wm_config(struct brw_context *brw,
 422                           const struct brw_blorp_params *params)
 423 {
 424    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 425    uint32_t dw1 = 0, dw2 = 0;
 426
 427    switch (params->hiz_op) {
 428    case GEN6_HIZ_OP_DEPTH_CLEAR:
 429       dw1 |= GEN7_WM_DEPTH_CLEAR;
 430       break;
 431    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 432       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 433       break;
 434    case GEN6_HIZ_OP_HIZ_RESOLVE:
 435       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 436       break;
 437    case GEN6_HIZ_OP_NONE:
 438       break;
 439    default:
 440       unreachable("not reached");
 441    }
 442    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 443    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 444    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 445
 446    if (params->wm_prog_data)
 447       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 448
 449    if (params->src.mt)
 450       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 451
 452    if (params->dst.num_samples > 1) {
 453       dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 454       if (prog_data && prog_data->persample_msaa_dispatch)
 455          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 456       else
 457          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 458    } else {
 459       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 460       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 461    }
 462
 463    BEGIN_BATCH(3);
 464    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 465    OUT_BATCH(dw1);
 466    OUT_BATCH(dw2);
 467    ADVANCE_BATCH();
 468 }
 469
 470
 471 /**
 472  * 3DSTATE_PS
 473  *
 474  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 475  * that, thread dispatch info must still be specified.
 476  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 477  *       valid range for this field is [0x3, 0x2f].
 478  *     - A dispatch mode must be given; that is, at least one of the
 479  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 480  *       discovered through simulator error messages.
 481  */
 482 static void
 483 gen7_blorp_emit_ps_config(struct brw_context *brw,
 484                           const struct brw_blorp_params *params)
 485 {
 486    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 487    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 488    const int max_threads_shift = brw->is_haswell ?
 489       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 490
 491    dw2 = dw4 = dw5 = ksp0 = ksp2 = 0;
 492    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 493
 494    if (brw->is_haswell)
 495       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 496    if (params->wm_prog_data) {
 497       dw5 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 498       dw5 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 499
 500       ksp0 = params->wm_prog_kernel;
 501       ksp2 = params->wm_prog_kernel + params->wm_prog_data->ksp_offset_2;
 502
 503       if (params->wm_prog_data->dispatch_8)
 504          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 505       if (params->wm_prog_data->dispatch_16)
 506          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 507       if (params->wm_prog_data->num_varying_inputs)
 508          dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 509    } else {
 510       /* The hardware gets angry if we don't enable at least one dispatch
 511        * mode, so just enable 16-pixel dispatch if we don't have a program.
 512        */
 513       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 514    }
 515
 516    if (params->src.mt)
 517       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 518
 519    dw4 |= params->fast_clear_op;
 520
 521    BEGIN_BATCH(8);
 522    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 523    OUT_BATCH(ksp0);
 524    OUT_BATCH(dw2);
 525    OUT_BATCH(0);
 526    OUT_BATCH(dw4);
 527    OUT_BATCH(dw5);
 528    OUT_BATCH(0); /* kernel 1 pointer */
 529    OUT_BATCH(ksp2);
 530    ADVANCE_BATCH();
 531 }
 532
 533
 534 void
 535 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 536                                           uint32_t wm_bind_bo_offset)
 537 {
 538    BEGIN_BATCH(2);
 539    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 540    OUT_BATCH(wm_bind_bo_offset);
 541    ADVANCE_BATCH();
 542 }
 543
 544
 545 void
 546 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 547                                           uint32_t sampler_offset)
 548 {
 549    BEGIN_BATCH(2);
 550    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 551    OUT_BATCH(sampler_offset);
 552    ADVANCE_BATCH();
 553 }
 554
 555 void
 556 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
 557 {
 558    BEGIN_BATCH(7);
 559    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 560    OUT_BATCH(0);
 561    OUT_BATCH(0);
 562    OUT_BATCH(0);
 563    OUT_BATCH(0);
 564    OUT_BATCH(0);
 565    OUT_BATCH(0);
 566    ADVANCE_BATCH();
 567 }
 568
 569 static void
 570 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 571                                      const struct brw_blorp_params *params)
 572 {
 573    const uint8_t mocs = GEN7_MOCS_L3;
 574    uint32_t surfwidth, surfheight;
 575    uint32_t surftype;
 576    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 577    unsigned int min_array_element;
 578    GLenum gl_target = params->depth.mt->target;
 579    unsigned int lod;
 580
 581    switch (gl_target) {
 582    case GL_TEXTURE_CUBE_MAP_ARRAY:
 583    case GL_TEXTURE_CUBE_MAP:
 584       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 585        * situation, but experiments show that gl_Layer doesn't work when we do
 586        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 587        * equivalent.
 588        */
 589       surftype = BRW_SURFACE_2D;
 590       depth *= 6;
 591       break;
 592    default:
 593       surftype = translate_tex_target(gl_target);
 594       break;
 595    }
 596
 597    min_array_element = params->depth.layer;
 598    if (params->depth.mt->num_samples > 1) {
 599       /* Convert physical layer to logical layer. */
 600       min_array_element /= params->depth.mt->num_samples;
 601    }
 602
 603    lod = params->depth.level - params->depth.mt->first_level;
 604
 605    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 606       /* HIZ ops for lod 0 may set the width & height a little
 607        * larger to allow the fast depth clear to fit the hardware
 608        * alignment requirements. (8x4)
 609        */
 610       surfwidth = params->depth.width;
 611       surfheight = params->depth.height;
 612    } else {
 613       surfwidth = params->depth.mt->logical_width0;
 614       surfheight = params->depth.mt->logical_height0;
 615    }
 616
 617    /* 3DSTATE_DEPTH_BUFFER */
 618    {
 619       brw_emit_depth_stall_flushes(brw);
 620
 621       BEGIN_BATCH(7);
 622       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 623       OUT_BATCH((params->depth.mt->pitch - 1) |
 624                 params->depth_format << 18 |
 625                 1 << 22 | /* hiz enable */
 626                 1 << 28 | /* depth write */
 627                 surftype << 29);
 628       OUT_RELOC(params->depth.mt->bo,
 629                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 630                 0);
 631       OUT_BATCH((surfwidth - 1) << 4 |
 632                 (surfheight - 1) << 18 |
 633                 lod);
 634       OUT_BATCH(((depth - 1) << 21) |
 635                 (min_array_element << 10) |
 636                 mocs);
 637       OUT_BATCH(0);
 638       OUT_BATCH((depth - 1) << 21);
 639       ADVANCE_BATCH();
 640    }
 641
 642    /* 3DSTATE_HIER_DEPTH_BUFFER */
 643    {
 644       struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
 645
 646       BEGIN_BATCH(3);
 647       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 648       OUT_BATCH((mocs << 25) |
 649                 (hiz_buf->pitch - 1));
 650       OUT_RELOC(hiz_buf->bo,
 651                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 652                 0);
 653       ADVANCE_BATCH();
 654    }
 655
 656    /* 3DSTATE_STENCIL_BUFFER */
 657    {
 658       BEGIN_BATCH(3);
 659       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 660       OUT_BATCH(0);
 661       OUT_BATCH(0);
 662       ADVANCE_BATCH();
 663    }
 664 }
 665
 666
 667 static void
 668 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 669 {
 670    brw_emit_depth_stall_flushes(brw);
 671
 672    BEGIN_BATCH(7);
 673    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 674    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 675    OUT_BATCH(0);
 676    OUT_BATCH(0);
 677    OUT_BATCH(0);
 678    OUT_BATCH(0);
 679    OUT_BATCH(0);
 680    ADVANCE_BATCH();
 681
 682    BEGIN_BATCH(3);
 683    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 684    OUT_BATCH(0);
 685    OUT_BATCH(0);
 686    ADVANCE_BATCH();
 687
 688    BEGIN_BATCH(3);
 689    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 690    OUT_BATCH(0);
 691    OUT_BATCH(0);
 692    ADVANCE_BATCH();
 693 }
 694
 695
 696 /* 3DSTATE_CLEAR_PARAMS
 697  *
 698  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 699  * 3DSTATE_CLEAR_PARAMS:
 700  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 701  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 702  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 703  */
 704 void
 705 gen7_blorp_emit_clear_params(struct brw_context *brw,
 706                              const struct brw_blorp_params *params)
 707 {
 708    BEGIN_BATCH(3);
 709    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 710    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 711    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 712    ADVANCE_BATCH();
 713 }
 714
 715
 716 /* 3DPRIMITIVE */
 717 void
 718 gen7_blorp_emit_primitive(struct brw_context *brw,
 719                           const struct brw_blorp_params *params)
 720 {
 721    BEGIN_BATCH(7);
 722    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 723    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 724              _3DPRIM_RECTLIST);
 725    OUT_BATCH(3); /* vertex count per instance */
 726    OUT_BATCH(0);
 727    OUT_BATCH(params->num_layers); /* instance count */
 728    OUT_BATCH(0);
 729    OUT_BATCH(0);
 730    ADVANCE_BATCH();
 731 }
 732
 733
 734 /**
 735  * \copydoc gen6_blorp_exec()
 736  */
 737 void
 738 gen7_blorp_exec(struct brw_context *brw,
 739                 const struct brw_blorp_params *params)
 740 {
 741    if (brw->gen >= 8)
 742       return;
 743
 744    uint32_t cc_blend_state_offset = 0;
 745    uint32_t cc_state_offset = 0;
 746    uint32_t depthstencil_offset;
 747    uint32_t wm_bind_bo_offset = 0;
 748
 749    brw_upload_state_base_address(brw);
 750
 751    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
 752    gen6_emit_3dstate_sample_mask(brw,
 753                                  params->dst.num_samples > 1 ?
 754                                  (1 << params->dst.num_samples) - 1 : 1);
 755    gen6_blorp_emit_vertices(brw, params);
 756    gen7_blorp_emit_urb_config(brw, params);
 757    if (params->wm_prog_data) {
 758       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 759       cc_state_offset = gen6_blorp_emit_cc_state(brw);
 760       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 761       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 762    }
 763    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 764    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
 765    if (brw->use_resource_streamer)
 766       gen7_disable_hw_binding_tables(brw);
 767    if (params->wm_prog_data) {
 768       uint32_t wm_surf_offset_renderbuffer;
 769       uint32_t wm_surf_offset_texture = 0;
 770
 771       intel_miptree_used_for_rendering(params->dst.mt);
 772       wm_surf_offset_renderbuffer =
 773          gen7_blorp_emit_surface_state(brw, &params->dst,
 774                                        I915_GEM_DOMAIN_RENDER,
 775                                        I915_GEM_DOMAIN_RENDER,
 776                                        true /* is_render_target */);
 777       if (params->src.mt) {
 778          wm_surf_offset_texture =
 779             gen7_blorp_emit_surface_state(brw, &params->src,
 780                                           I915_GEM_DOMAIN_SAMPLER, 0,
 781                                           false /* is_render_target */);
 782       }
 783       wm_bind_bo_offset =
 784          gen6_blorp_emit_binding_table(brw,
 785                                        wm_surf_offset_renderbuffer,
 786                                        wm_surf_offset_texture);
 787    }
 788    gen7_blorp_emit_vs_disable(brw);
 789    gen7_blorp_emit_hs_disable(brw);
 790    gen7_blorp_emit_te_disable(brw);
 791    gen7_blorp_emit_ds_disable(brw);
 792    gen7_blorp_emit_gs_disable(brw);
 793    gen7_blorp_emit_streamout_disable(brw);
 794    gen6_blorp_emit_clip_disable(brw);
 795    gen7_blorp_emit_sf_config(brw, params);
 796    gen7_blorp_emit_wm_config(brw, params);
 797    if (params->wm_prog_data)
 798       gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 799
 800    gen7_blorp_emit_constant_ps_disable(brw);
 801
 802    if (params->src.mt) {
 803       const uint32_t sampler_offset =
 804          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 805       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 806    }
 807
 808    gen7_blorp_emit_ps_config(brw, params);
 809    gen7_blorp_emit_cc_viewport(brw);
 810
 811    if (params->depth.mt)
 812       gen7_blorp_emit_depth_stencil_config(brw, params);
 813    else
 814       gen7_blorp_emit_depth_disable(brw);
 815    gen7_blorp_emit_clear_params(brw, params);
 816    gen6_blorp_emit_drawing_rectangle(brw, params);
 817    gen7_blorp_emit_primitive(brw, params);
 818 }