src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "compiler/brw_eu_defines.h"
  29 #include "brw_util.h"
  30 #include "brw_wm.h"
  31 #include "program/program.h"
  32 #include "program/prog_parameter.h"
  33 #include "program/prog_statevars.h"
  34 #include "main/framebuffer.h"
  35 #include "intel_batchbuffer.h"
  36
  37 static void
  38 upload_wm_state(struct brw_context *brw)
  39 {
  40    struct gl_context *ctx = &brw->ctx;
  41    /* BRW_NEW_FS_PROG_DATA */
  42    const struct brw_wm_prog_data *prog_data =
  43       brw_wm_prog_data(brw->wm.base.prog_data);
  44    bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
  45    uint32_t dw1, dw2;
  46
  47    /* _NEW_BUFFERS */
  48    const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
  49
  50    dw1 = dw2 = 0;
  51    dw1 |= GEN7_WM_STATISTICS_ENABLE;
  52    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
  53    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
  54
  55    /* _NEW_LINE */
  56    if (ctx->Line.StippleFlag)
  57       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
  58
  59    /* _NEW_POLYGON */
  60    if (ctx->Polygon.StippleFlag)
  61       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
  62
  63    if (prog_data->uses_src_depth)
  64       dw1 |= GEN7_WM_USES_SOURCE_DEPTH;
  65
  66    if (prog_data->uses_src_w)
  67       dw1 |= GEN7_WM_USES_SOURCE_W;
  68
  69    dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
  70    dw1 |= prog_data->barycentric_interp_modes <<
  71       GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
  72
  73    /* _NEW_COLOR, _NEW_MULTISAMPLE _NEW_BUFFERS */
  74    /* Enable if the pixel shader kernel generates and outputs oMask.
  75     */
  76    if (prog_data->uses_kill ||
  77        _mesa_is_alpha_test_enabled(ctx) ||
  78        _mesa_is_alpha_to_coverage_enabled(ctx) ||
  79        prog_data->uses_omask) {
  80       dw1 |= GEN7_WM_KILL_ENABLE;
  81    }
  82
  83    /* _NEW_BUFFERS | _NEW_COLOR */
  84    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
  85        prog_data->has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) {
  86       dw1 |= GEN7_WM_DISPATCH_ENABLE;
  87    }
  88    if (multisampled_fbo) {
  89       /* _NEW_MULTISAMPLE */
  90       if (ctx->Multisample.Enabled)
  91          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
  92       else
  93          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
  94
  95       if (prog_data->persample_dispatch)
  96          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
  97       else
  98          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
  99    } else {
 100       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 101       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 102    }
 103
 104    if (prog_data->uses_sample_mask) {
 105       dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
 106    }
 107
 108    /* BRW_NEW_FS_PROG_DATA */
 109    if (prog_data->early_fragment_tests)
 110       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
 111    else if (prog_data->has_side_effects)
 112       dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
 113
 114    /* The "UAV access enable" bits are unnecessary on HSW because they only
 115     * seem to have an effect on the HW-assisted coherency mechanism which we
 116     * don't need, and the rasterization-related UAV_ONLY flag and the
 117     * DISPATCH_ENABLE bit can be set independently from it.
 118     * C.f. gen8_upload_ps_extra().
 119     *
 120     * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | _NEW_COLOR
 121     */
 122    if (brw->is_haswell &&
 123        !(brw_color_buffer_write_enabled(brw) || writes_depth) &&
 124        prog_data->has_side_effects)
 125       dw2 |= HSW_WM_UAV_ONLY;
 126
 127    BEGIN_BATCH(3);
 128    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 129    OUT_BATCH(dw1);
 130    OUT_BATCH(dw2);
 131    ADVANCE_BATCH();
 132 }
 133
 134 const struct brw_tracked_state gen7_wm_state = {
 135    .dirty = {
 136       .mesa  = _NEW_BUFFERS |
 137                _NEW_COLOR |
 138                _NEW_LINE |
 139                _NEW_MULTISAMPLE |
 140                _NEW_POLYGON,
 141       .brw   = BRW_NEW_BATCH |
 142                BRW_NEW_BLORP |
 143                BRW_NEW_FS_PROG_DATA,
 144    },
 145    .emit = upload_wm_state,
 146 };
 147
 148 static void
 149 gen7_upload_ps_state(struct brw_context *brw,
 150                      const struct brw_stage_state *stage_state,
 151                      const struct brw_wm_prog_data *prog_data,
 152                      bool enable_dual_src_blend, unsigned sample_mask,
 153                      unsigned fast_clear_op)
 154 {
 155    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 156    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 157    const int max_threads_shift = brw->is_haswell ?
 158       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 159
 160    dw2 = dw4 = dw5 = ksp2 = 0;
 161
 162    const unsigned sampler_count =
 163       DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
 164    dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
 165
 166    dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
 167            GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 168
 169    if (prog_data->base.use_alt_mode)
 170       dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 171
 172    /* Haswell requires the sample mask to be set in this packet as well as
 173     * in 3DSTATE_SAMPLE_MASK; the values should match. */
 174    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 175    if (brw->is_haswell)
 176       dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
 177
 178    dw4 |= (devinfo->max_wm_threads - 1) << max_threads_shift;
 179
 180    if (prog_data->base.nr_params > 0)
 181       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 182
 183    /* From the IVB PRM, volume 2 part 1, page 287:
 184     * "This bit is inserted in the PS payload header and made available to
 185     * the DataPort (either via the message header or via header bypass) to
 186     * indicate that oMask data (one or two phases) is included in Render
 187     * Target Write messages. If present, the oMask data is used to mask off
 188     * samples."
 189     */
 190    if (prog_data->uses_omask)
 191       dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
 192
 193    /* From the IVB PRM, volume 2 part 1, page 287:
 194     * "If the PS kernel does not need the Position XY Offsets to
 195     * compute a Position Value, then this field should be programmed
 196     * to POSOFFSET_NONE."
 197     * "SW Recommendation: If the PS kernel needs the Position Offsets
 198     * to compute a Position XY value, this field should match Position
 199     * ZW Interpolation Mode to ensure a consistent position.xyzw
 200     * computation."
 201     * We only require XY sample offsets. So, this recommendation doesn't
 202     * look useful at the moment. We might need this in future.
 203     */
 204    if (prog_data->uses_pos_offset)
 205       dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
 206    else
 207       dw4 |= GEN7_PS_POSOFFSET_NONE;
 208
 209    /* The hardware wedges if you have this bit set but don't turn on any dual
 210     * source blend factors.
 211     */
 212    if (enable_dual_src_blend)
 213       dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
 214
 215    /* BRW_NEW_FS_PROG_DATA */
 216    if (prog_data->num_varying_inputs != 0)
 217       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 218
 219    dw4 |= fast_clear_op;
 220
 221    if (prog_data->dispatch_16)
 222       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 223
 224    if (prog_data->dispatch_8)
 225       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 226
 227    dw5 |= prog_data->base.dispatch_grf_start_reg <<
 228           GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 229    dw5 |= prog_data->dispatch_grf_start_reg_2 <<
 230           GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 231
 232    ksp0 = stage_state->prog_offset;
 233    ksp2 = stage_state->prog_offset + prog_data->prog_offset_2;
 234
 235    BEGIN_BATCH(8);
 236    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 237    OUT_BATCH(ksp0);
 238    OUT_BATCH(dw2);
 239    if (prog_data->base.total_scratch) {
 240       OUT_RELOC(brw->wm.base.scratch_bo,
 241                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 242                 ffs(stage_state->per_thread_scratch) - 11);
 243    } else {
 244       OUT_BATCH(0);
 245    }
 246    OUT_BATCH(dw4);
 247    OUT_BATCH(dw5);
 248    OUT_BATCH(0); /* kernel 1 pointer */
 249    OUT_BATCH(ksp2);
 250    ADVANCE_BATCH();
 251 }
 252
 253 static void
 254 upload_ps_state(struct brw_context *brw)
 255 {
 256    /* BRW_NEW_FS_PROG_DATA */
 257    const struct brw_wm_prog_data *prog_data =
 258       brw_wm_prog_data(brw->wm.base.prog_data);
 259    const struct gl_context *ctx = &brw->ctx;
 260    /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
 261    const bool enable_dual_src_blend = prog_data->dual_src_blend &&
 262                                       (ctx->Color.BlendEnabled & 1) &&
 263                                       ctx->Color.Blend[0]._UsesDualSrc;
 264    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 265    const unsigned sample_mask =
 266       brw->is_haswell ? gen6_determine_sample_mask(brw) : 0;
 267
 268    gen7_upload_ps_state(brw, &brw->wm.base, prog_data,
 269                         enable_dual_src_blend, sample_mask,
 270                         brw->wm.fast_clear_op);
 271 }
 272
 273 const struct brw_tracked_state gen7_ps_state = {
 274    .dirty = {
 275       .mesa  = _NEW_BUFFERS |
 276                _NEW_COLOR |
 277                _NEW_MULTISAMPLE,
 278       .brw   = BRW_NEW_BATCH |
 279                BRW_NEW_BLORP |
 280                BRW_NEW_FS_PROG_DATA,
 281    },
 282    .emit = upload_ps_state,
 283 };