src/mesa/drivers/dri/i965/gen7_wm_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdbool.h>
  25 #include "brw_context.h"
  26 #include "brw_state.h"
  27 #include "brw_defines.h"
  28 #include "brw_util.h"
  29 #include "brw_wm.h"
  30 #include "program/prog_parameter.h"
  31 #include "program/prog_statevars.h"
  32 #include "intel_batchbuffer.h"
  33
  34 static void
  35 gen7_prepare_wm_constants(struct brw_context *brw)
  36 {
  37    struct intel_context *intel = &brw->intel;
  38    struct gl_context *ctx = &intel->ctx;
  39    /* BRW_NEW_FRAGMENT_PROGRAM */
  40    const struct brw_fragment_program *fp =
  41       brw_fragment_program_const(brw->fragment_program);
  42
  43    /* Updates the ParameterValues[i] pointers for all parameters of the
  44     * basic type of PROGRAM_STATE_VAR.
  45     */
  46    /* XXX: Should this happen somewhere before to get our state flag set? */
  47    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  48
  49    /* CACHE_NEW_WM_PROG */
  50    if (brw->wm.prog_data->nr_params != 0) {
  51       float *constants;
  52       unsigned int i;
  53
  54       constants = brw_state_batch(brw, AUB_TRACE_NO_TYPE,
  55                                   brw->wm.prog_data->nr_params *
  56                                   sizeof(float),
  57                                   32, &brw->wm.push_const_offset);
  58
  59       for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  60          constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
  61                                       *brw->wm.prog_data->param[i]);
  62       }
  63
  64       if (0) {
  65          printf("WM constants:\n");
  66          for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
  67             if ((i & 7) == 0)
  68                printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
  69             printf("%8f ", constants[i]);
  70             if ((i & 7) == 7)
  71                printf("\n");
  72          }
  73          if ((i & 7) != 0)
  74             printf("\n");
  75          printf("\n");
  76       }
  77    }
  78 }
  79
  80 const struct brw_tracked_state gen7_wm_constants = {
  81    .dirty = {
  82       .mesa  = _NEW_PROGRAM_CONSTANTS,
  83       .brw   = (BRW_NEW_BATCH | BRW_NEW_FRAGMENT_PROGRAM),
  84       .cache = CACHE_NEW_WM_PROG,
  85    },
  86    .prepare = gen7_prepare_wm_constants,
  87 };
  88
  89 static void
  90 upload_wm_state(struct brw_context *brw)
  91 {
  92    struct intel_context *intel = &brw->intel;
  93    struct gl_context *ctx = &intel->ctx;
  94    const struct brw_fragment_program *fp =
  95       brw_fragment_program_const(brw->fragment_program);
  96    bool writes_depth = false;
  97    uint32_t dw1;
  98
  99    dw1 = 0;
 100    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 101    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 102    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 103
 104    /* _NEW_LINE */
 105    if (ctx->Line.StippleFlag)
 106       dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
 107
 108    /* _NEW_POLYGON */
 109    if (ctx->Polygon.StippleFlag)
 110       dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
 111
 112    /* BRW_NEW_FRAGMENT_PROGRAM */
 113    if (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
 114       dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
 115    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
 116       writes_depth = true;
 117       dw1 |= GEN7_WM_PSCDEPTH_ON;
 118    }
 119
 120    /* _NEW_COLOR */
 121    if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
 122       dw1 |= GEN7_WM_KILL_ENABLE;
 123
 124    /* _NEW_BUFFERS */
 125    if (brw_color_buffer_write_enabled(brw) || writes_depth ||
 126        dw1 & GEN7_WM_KILL_ENABLE) {
 127       dw1 |= GEN7_WM_DISPATCH_ENABLE;
 128    }
 129
 130    dw1 |= GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
 131
 132    BEGIN_BATCH(3);
 133    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 134    OUT_BATCH(dw1);
 135    OUT_BATCH(0);
 136    ADVANCE_BATCH();
 137 }
 138
 139 const struct brw_tracked_state gen7_wm_state = {
 140    .dirty = {
 141       .mesa  = (_NEW_LINE | _NEW_POLYGON |
 142                 _NEW_COLOR | _NEW_BUFFERS),
 143       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 144                 BRW_NEW_URB_FENCE |
 145                 BRW_NEW_BATCH),
 146       .cache = 0,
 147    },
 148    .emit = upload_wm_state,
 149 };
 150
 151 static void
 152 upload_ps_state(struct brw_context *brw)
 153 {
 154    struct intel_context *intel = &brw->intel;
 155    uint32_t dw2, dw4, dw5;
 156
 157    BEGIN_BATCH(2);
 158    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 159    OUT_BATCH(brw->wm.bind_bo_offset);
 160    ADVANCE_BATCH();
 161
 162    /* CACHE_NEW_SAMPLER */
 163    BEGIN_BATCH(2);
 164    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 165    OUT_BATCH(brw->wm.sampler_offset);
 166    ADVANCE_BATCH();
 167
 168    /* CACHE_NEW_WM_PROG */
 169    if (brw->wm.prog_data->nr_params == 0) {
 170       /* Disable the push constant buffers. */
 171       BEGIN_BATCH(7);
 172       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 173       OUT_BATCH(0);
 174       OUT_BATCH(0);
 175       OUT_BATCH(0);
 176       OUT_BATCH(0);
 177       OUT_BATCH(0);
 178       OUT_BATCH(0);
 179       ADVANCE_BATCH();
 180    } else {
 181       BEGIN_BATCH(7);
 182       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 183
 184       OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
 185                       brw->wm.prog_data->dispatch_width) / 8);
 186       OUT_BATCH(0);
 187       /* Pointer to the WM constant buffer.  Covered by the set of
 188        * state flags from gen7_prepare_wm_constants
 189        */
 190       OUT_BATCH(brw->wm.push_const_offset);
 191       OUT_BATCH(0);
 192       OUT_BATCH(0);
 193       OUT_BATCH(0);
 194       ADVANCE_BATCH();
 195    }
 196
 197    dw2 = dw4 = dw5 = 0;
 198
 199    dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
 200
 201    /* BRW_NEW_NR_WM_SURFACES */
 202    dw2 |= brw->wm.nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 203
 204    /* OpenGL non-ieee floating point mode */
 205    dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 206
 207    /* CACHE_NEW_SAMPLER */
 208    dw4 |= (brw->wm_max_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;
 209
 210    /* CACHE_NEW_WM_PROG */
 211    if (brw->wm.prog_data->nr_params > 0)
 212       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 213
 214    /* BRW_NEW_FRAGMENT_PROGRAM */
 215    if (brw->fragment_program->Base.InputsRead != 0)
 216       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 217
 218    if (brw->wm.prog_data->dispatch_width == 8)
 219       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 220    else
 221       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 222
 223    /* BRW_NEW_CURBE_OFFSETS */
 224    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 225            GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
 226
 227    BEGIN_BATCH(8);
 228    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 229    OUT_BATCH(brw->wm.prog_offset);
 230    OUT_BATCH(dw2);
 231    OUT_BATCH(0); /* scratch space base offset */
 232    OUT_BATCH(dw4);
 233    OUT_BATCH(dw5);
 234    OUT_BATCH(0); /* kernel 1 pointer */
 235    OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
 236    ADVANCE_BATCH();
 237 }
 238
 239 const struct brw_tracked_state gen7_ps_state = {
 240    .dirty = {
 241       .mesa  = _NEW_PROGRAM_CONSTANTS,
 242       .brw   = (BRW_NEW_CURBE_OFFSETS |
 243                 BRW_NEW_FRAGMENT_PROGRAM |
 244                 BRW_NEW_NR_WM_SURFACES |
 245                 BRW_NEW_PS_BINDING_TABLE |
 246                 BRW_NEW_URB_FENCE |
 247                 BRW_NEW_BATCH),
 248       .cache = (CACHE_NEW_SAMPLER |
 249                 CACHE_NEW_WM_PROG)
 250    },
 251    .emit = upload_ps_state,
 252 };