src/mesa/drivers/dri/i965/gen7_wm_surface_state.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "main/mtypes.h"
  24 #include "main/samplerobj.h"
  25 #include "main/texstore.h"
  26 #include "program/prog_parameter.h"
  27
  28 #include "intel_mipmap_tree.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_tex.h"
  31 #include "intel_fbo.h"
  32
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35 #include "brw_defines.h"
  36 #include "brw_wm.h"
  37
  38 static void
  39 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
  40 {
  41    switch (tiling) {
  42    case I915_TILING_NONE:
  43       surf->ss0.tiled_surface = 0;
  44       surf->ss0.tile_walk = 0;
  45       break;
  46    case I915_TILING_X:
  47       surf->ss0.tiled_surface = 1;
  48       surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
  49       break;
  50    case I915_TILING_Y:
  51       surf->ss0.tiled_surface = 1;
  52       surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
  53       break;
  54    }
  55 }
  56
  57 static void
  58 gen7_update_texture_surface(struct gl_context *ctx, GLuint unit)
  59 {
  60    struct brw_context *brw = brw_context(ctx);
  61    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
  62    struct intel_texture_object *intelObj = intel_texture_object(tObj);
  63    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
  64    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
  65    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
  66    struct gen7_surface_state *surf;
  67
  68    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  69                           sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]);
  70    memset(surf, 0, sizeof(*surf));
  71
  72    surf->ss0.surface_type = translate_tex_target(tObj->Target);
  73    surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat,
  74                                                    firstImage->InternalFormat,
  75                                                    sampler->DepthMode,
  76                                                    sampler->sRGBDecode);
  77    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
  78       surf->ss0.cube_pos_x = 1;
  79       surf->ss0.cube_pos_y = 1;
  80       surf->ss0.cube_pos_z = 1;
  81       surf->ss0.cube_neg_x = 1;
  82       surf->ss0.cube_neg_y = 1;
  83       surf->ss0.cube_neg_z = 1;
  84    }
  85
  86    gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
  87
  88    /* ss0 remaining fields:
  89     * - is_array
  90     * - vertical_alignment
  91     * - horizontal_alignment
  92     * - vert_line_stride (exists on gen6 but we ignore it)
  93     * - vert_line_stride_ofs (exists on gen6 but we ignore it)
  94     * - surface_array_spacing
  95     * - render_cache_read_write (exists on gen6 but ignored here)
  96     */
  97
  98    surf->ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
  99
 100    surf->ss2.width = firstImage->Width - 1;
 101    surf->ss2.height = firstImage->Height - 1;
 102
 103    surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 104    surf->ss3.depth = firstImage->Depth - 1;
 105
 106    /* ss4: ignored? */
 107
 108    surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
 109    surf->ss5.min_lod = 0;
 110
 111    /* ss5 remaining fields:
 112     * - x_offset (N/A for textures?)
 113     * - y_offset (ditto)
 114     * - cache_control
 115     */
 116
 117    /* Emit relocation to surface contents */
 118    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 119                            brw->wm.surf_offset[surf_index] +
 120                            offsetof(struct gen7_surface_state, ss1),
 121                            intelObj->mt->region->buffer, 0,
 122                            I915_GEM_DOMAIN_SAMPLER, 0);
 123 }
 124
 125 /**
 126  * Create the constant buffer surface.  Vertex/fragment shader constants will
 127  * be read from this buffer with Data Port Read instructions/messages.
 128  */
 129 void
 130 gen7_create_constant_surface(struct brw_context *brw,
 131                              drm_intel_bo *bo,
 132                              int width,
 133                              uint32_t *out_offset)
 134 {
 135    const GLint w = width - 1;
 136    struct gen7_surface_state *surf;
 137
 138    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 139                           sizeof(*surf), 32, out_offset);
 140    memset(surf, 0, sizeof(*surf));
 141
 142    surf->ss0.surface_type = BRW_SURFACE_BUFFER;
 143    surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 144
 145    surf->ss0.render_cache_read_write = 1;
 146
 147    assert(bo);
 148    surf->ss1.base_addr = bo->offset; /* reloc */
 149
 150    surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 151    surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 152    surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 153    surf->ss3.pitch = (width * 16) - 1; /* ignored?? */
 154    gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
 155
 156    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 157     * bspec ("Data Cache") says that the data cache does not exist as
 158     * a separate cache and is just the sampler cache.
 159     */
 160    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 161                            (*out_offset +
 162                             offsetof(struct gen7_surface_state, ss1)),
 163                            bo, 0,
 164                            I915_GEM_DOMAIN_SAMPLER, 0);
 165 }
 166
 167 /**
 168  * Updates surface / buffer for fragment shader constant buffer, if
 169  * one is required.
 170  *
 171  * This consumes the state updates for the constant buffer, and produces
 172  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 173  * inclusion in the binding table.
 174  */
 175 static void upload_wm_constant_surface(struct brw_context *brw)
 176 {
 177    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 178    struct brw_fragment_program *fp =
 179       (struct brw_fragment_program *) brw->fragment_program;
 180    const struct gl_program_parameter_list *params =
 181       fp->program.Base.Parameters;
 182
 183    /* If there's no constant buffer, then no surface BO is needed to point at
 184     * it.
 185     */
 186    if (brw->wm.const_bo == 0) {
 187       if (brw->wm.surf_offset[surf]) {
 188          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 189          brw->wm.surf_offset[surf] = 0;
 190       }
 191       return;
 192    }
 193
 194    gen7_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 195                                 &brw->wm.surf_offset[surf]);
 196    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 197 }
 198
 199 const struct brw_tracked_state gen7_wm_constant_surface = {
 200    .dirty = {
 201       .mesa = 0,
 202       .brw = (BRW_NEW_WM_CONSTBUF |
 203               BRW_NEW_BATCH),
 204       .cache = 0
 205    },
 206    .emit = upload_wm_constant_surface,
 207 };
 208
 209 static void
 210 gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
 211 {
 212    struct gen7_surface_state *surf;
 213
 214    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 215                           sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
 216    memset(surf, 0, sizeof(*surf));
 217
 218    surf->ss0.surface_type = BRW_SURFACE_NULL;
 219    surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 220 }
 221
 222 /**
 223  * Sets up a surface state structure to point at the given region.
 224  * While it is only used for the front/back buffer currently, it should be
 225  * usable for further buffers when doing ARB_draw_buffer support.
 226  */
 227 static void
 228 gen7_update_renderbuffer_surface(struct brw_context *brw,
 229                                  struct gl_renderbuffer *rb,
 230                                  unsigned int unit)
 231 {
 232    struct intel_context *intel = &brw->intel;
 233    struct gl_context *ctx = &intel->ctx;
 234    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 235    struct intel_region *region = irb->region;
 236    struct gen7_surface_state *surf;
 237    uint32_t tile_x, tile_y;
 238
 239    surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
 240                           sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
 241    memset(surf, 0, sizeof(*surf));
 242
 243    switch (irb->Base.Format) {
 244    case MESA_FORMAT_XRGB8888:
 245       /* XRGB is handled as ARGB because the chips in this family
 246        * cannot render to XRGB targets.  This means that we have to
 247        * mask writes to alpha (ala glColorMask) and reconfigure the
 248        * alpha blending hardware to use GL_ONE (or GL_ZERO) for
 249        * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
 250        * used.
 251        */
 252       surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 253       break;
 254    case MESA_FORMAT_INTENSITY_FLOAT32:
 255    case MESA_FORMAT_LUMINANCE_FLOAT32:
 256       /* For these formats, we just need to read/write the first
 257        * channel into R, which is to say that we just treat them as
 258        * GL_RED.
 259        */
 260       surf->ss0.surface_format = BRW_SURFACEFORMAT_R32_FLOAT;
 261       break;
 262    case MESA_FORMAT_SARGB8:
 263       /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB
 264          surfaces to the blend/update as sRGB */
 265       if (ctx->Color.sRGBEnabled)
 266          surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
 267       else
 268          surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 269       break;
 270    default:
 271       assert(brw_render_target_supported(irb->Base.Format));
 272       surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format);
 273    }
 274
 275    surf->ss0.surface_type = BRW_SURFACE_2D;
 276    /* reloc */
 277    surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
 278    surf->ss1.base_addr += region->buffer->offset; /* reloc */
 279
 280    assert(brw->has_surface_tile_offset);
 281    /* Note that the low bits of these fields are missing, so
 282     * there's the possibility of getting in trouble.
 283     */
 284    assert(tile_x % 4 == 0);
 285    assert(tile_y % 2 == 0);
 286    surf->ss5.x_offset = tile_x / 4;
 287    surf->ss5.y_offset = tile_y / 2;
 288
 289    surf->ss2.width = rb->Width - 1;
 290    surf->ss2.height = rb->Height - 1;
 291    gen7_set_surface_tiling(surf, region->tiling);
 292    surf->ss3.pitch = (region->pitch * region->cpp) - 1;
 293
 294    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 295                            brw->wm.surf_offset[unit] +
 296                            offsetof(struct gen7_surface_state, ss1),
 297                            region->buffer,
 298                            surf->ss1.base_addr - region->buffer->offset,
 299                            I915_GEM_DOMAIN_RENDER,
 300                            I915_GEM_DOMAIN_RENDER);
 301 }
 302
 303 static void
 304 prepare_wm_surfaces(struct brw_context *brw)
 305 {
 306    struct gl_context *ctx = &brw->intel.ctx;
 307    int i;
 308    int nr_surfaces = 0;
 309
 310    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 311       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 312          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
 313          struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 314          struct intel_region *region = irb ? irb->region : NULL;
 315
 316          if (region)
 317             brw_add_validated_bo(brw, region->buffer);
 318          nr_surfaces = SURF_INDEX_DRAW(i) + 1;
 319       }
 320    }
 321
 322    if (brw->wm.const_bo) {
 323       brw_add_validated_bo(brw, brw->wm.const_bo);
 324       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 325    }
 326
 327    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 328       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 329       struct gl_texture_object *tObj = texUnit->_Current;
 330       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 331
 332       if (texUnit->_ReallyEnabled) {
 333          brw_add_validated_bo(brw, intelObj->mt->region->buffer);
 334          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 335       }
 336    }
 337
 338    /* Have to update this in our prepare, since the unit's prepare
 339     * relies on it.
 340     */
 341    if (brw->wm.nr_surfaces != nr_surfaces) {
 342       brw->wm.nr_surfaces = nr_surfaces;
 343       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 344    }
 345 }
 346
 347 /**
 348  * Constructs the set of surface state objects pointed to by the
 349  * binding table.
 350  */
 351 static void
 352 upload_wm_surfaces(struct brw_context *brw)
 353 {
 354    struct gl_context *ctx = &brw->intel.ctx;
 355    GLuint i;
 356
 357    /* _NEW_BUFFERS | _NEW_COLOR */
 358    /* Update surfaces for drawing buffers */
 359    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 360       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 361          if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
 362             gen7_update_renderbuffer_surface(brw,
 363                ctx->DrawBuffer->_ColorDrawBuffers[i], i);
 364          } else {
 365             gen7_update_null_renderbuffer_surface(brw, i);
 366          }
 367       }
 368    } else {
 369       gen7_update_null_renderbuffer_surface(brw, 0);
 370    }
 371
 372    /* Update surfaces for textures */
 373    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 374       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 375       const GLuint surf = SURF_INDEX_TEXTURE(i);
 376
 377       /* _NEW_TEXTURE */
 378       if (texUnit->_ReallyEnabled) {
 379          gen7_update_texture_surface(ctx, i);
 380       } else {
 381          brw->wm.surf_offset[surf] = 0;
 382       }
 383    }
 384
 385    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 386 }
 387
 388 const struct brw_tracked_state gen7_wm_surfaces = {
 389    .dirty = {
 390       .mesa = (_NEW_COLOR |
 391                _NEW_TEXTURE |
 392                _NEW_BUFFERS),
 393       .brw = BRW_NEW_BATCH,
 394       .cache = 0
 395    },
 396    .prepare = prepare_wm_surfaces,
 397    .emit = upload_wm_surfaces,
 398 };