2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct brw_context
*brw
,
148 const struct intel_mipmap_tree
*mt
,
149 unsigned *width_px
, unsigned *height
)
151 switch (mt
->tiling
) {
153 unreachable("Non-MSRT MCS requires X or Y tiling");
154 /* In release builds, fall through */
156 *width_px
= 32 / mt
->cpp
;
160 /* The docs are somewhat confusing with the way the tables are displayed.
161 * However, it does clearly state: "MCS and Lossless compression is
162 * supported for TiledY/TileYs/TileYf non-MSRTs only."
164 assert(brw
->gen
< 9);
165 *width_px
= 64 / mt
->cpp
;
171 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
174 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
175 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
177 * - Support is limited to tiled render targets.
179 * Gen9 changes the restriction to Y-tile only.
182 return tiling
== I915_TILING_Y
;
183 else if (brw
->gen
>= 7)
184 return tiling
!= I915_TILING_NONE
;
190 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
191 * can be used. This doesn't (and should not) inspect any of the properties of
194 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
195 * beneath the "Fast Color Clear" bullet (p326):
197 * - Support is for non-mip-mapped and non-array surface types only.
199 * And then later, on p327:
201 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
204 * From the Skylake documentation, it is made clear that X-tiling is no longer
207 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
211 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
212 const struct intel_mipmap_tree
*mt
)
214 /* MCS support does not exist prior to Gen7 */
218 if (mt
->disable_aux_buffers
)
221 /* This function applies only to non-multisampled render targets. */
222 if (mt
->num_samples
> 1)
225 /* MCS is only supported for color buffers */
226 switch (_mesa_get_format_base_format(mt
->format
)) {
227 case GL_DEPTH_COMPONENT
:
228 case GL_DEPTH_STENCIL
:
229 case GL_STENCIL_INDEX
:
233 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
235 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
237 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
238 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
244 /* Check for layered surfaces. */
245 if (mt
->physical_depth0
!= 1) {
246 /* Multisample surfaces with the CMS layout are not layered surfaces,
247 * yet still have physical_depth0 > 1. Assert that we don't
248 * accidentally reject a multisampled surface here. We should have
249 * rejected it earlier by explicitly checking the sample count.
251 assert(mt
->num_samples
<= 1);
254 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
255 mt
->logical_width0
, mt
->logical_height0
,
256 mt
->physical_depth0
);
262 /* There's no point in using an MCS buffer if the surface isn't in a
265 if (!brw
->format_supported_as_render_target
[mt
->format
])
269 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
270 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
271 return brw_losslessly_compressible_format(brw
, brw_format
);
276 /* On Gen9 support for color buffer compression was extended to single
277 * sampled surfaces. This is a helper considering both auxiliary buffer
278 * type and number of samples telling if the given miptree represents
279 * the new single sampled case - also called lossless compression.
282 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
283 const struct intel_mipmap_tree
*mt
)
285 /* Only available from Gen9 onwards. */
289 /* Compression always requires auxiliary buffer. */
293 /* Single sample compression is represented re-using msaa compression
294 * layout type: "Compressed Multisampled Surfaces".
296 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
299 /* And finally distinguish between msaa and single sample case. */
300 return mt
->num_samples
<= 1;
304 * Determine depth format corresponding to a depth+stencil format,
305 * for separate stencil.
308 intel_depth_format_for_depthstencil_format(mesa_format format
) {
310 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
311 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
312 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
313 return MESA_FORMAT_Z_FLOAT32
;
321 * @param for_bo Indicates that the caller is
322 * intel_miptree_create_for_bo(). If true, then do not create
325 static struct intel_mipmap_tree
*
326 intel_miptree_create_layout(struct brw_context
*brw
,
335 uint32_t layout_flags
)
337 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
341 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
342 _mesa_enum_to_string(target
),
343 _mesa_get_format_name(format
),
344 first_level
, last_level
, depth0
, mt
);
346 if (target
== GL_TEXTURE_1D_ARRAY
) {
347 /* For a 1D Array texture the OpenGL API will treat the height0
348 * parameter as the number of array slices. For Intel hardware, we treat
349 * the 1D array as a 2D Array with a height of 1.
351 * So, when we first come through this path to create a 1D Array
352 * texture, height0 stores the number of slices, and depth0 is 1. In
353 * this case, we want to swap height0 and depth0.
355 * Since some miptrees will be created based on the base miptree, we may
356 * come through this path and see height0 as 1 and depth0 being the
357 * number of slices. In this case we don't need to do the swap.
359 assert(height0
== 1 || depth0
== 1);
368 mt
->first_level
= first_level
;
369 mt
->last_level
= last_level
;
370 mt
->logical_width0
= width0
;
371 mt
->logical_height0
= height0
;
372 mt
->logical_depth0
= depth0
;
373 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
374 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
375 exec_list_make_empty(&mt
->hiz_map
);
376 mt
->cpp
= _mesa_get_format_bytes(format
);
377 mt
->num_samples
= num_samples
;
378 mt
->compressed
= _mesa_is_format_compressed(format
);
379 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
382 if (num_samples
> 1) {
383 /* Adjust width/height/depth for MSAA */
384 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
385 mt
->disable_aux_buffers
);
386 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
387 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
388 * "If the surface is multisampled and it is a depth or stencil
389 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
390 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
393 * +----------------------------------------------------------------+
394 * | Num Multisamples | W_l = | H_l = |
395 * +----------------------------------------------------------------+
396 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
397 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
398 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
399 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
400 * +----------------------------------------------------------------+
403 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
404 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
405 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
407 * Another more complicated explanation for these adjustments comes
408 * from the Sandybridge PRM, volume 4, part 1, page 31:
410 * "Any of the other messages (sample*, LOD, load4) used with a
411 * (4x) multisampled surface will in-effect sample a surface with
412 * double the height and width as that indicated in the surface
413 * state. Each pixel position on the original-sized surface is
414 * replaced with a 2x2 of samples with the following arrangement:
419 * Thus, when sampling from a multisampled texture, it behaves as
420 * though the layout in memory for (x,y,sample) is:
422 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
423 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
425 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
426 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
428 * However, the actual layout of multisampled data in memory is:
430 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
431 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
433 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
434 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
436 * This pattern repeats for each 2x2 pixel block.
438 * As a result, when calculating the size of our 4-sample buffer for
439 * an odd width or height, we have to align before scaling up because
440 * sample 3 is in that bottom right 2x2 block.
442 switch (num_samples
) {
444 assert(brw
->gen
>= 8);
445 width0
= ALIGN(width0
, 2) * 2;
446 height0
= ALIGN(height0
, 2);
449 width0
= ALIGN(width0
, 2) * 2;
450 height0
= ALIGN(height0
, 2) * 2;
453 width0
= ALIGN(width0
, 2) * 4;
454 height0
= ALIGN(height0
, 2) * 2;
457 width0
= ALIGN(width0
, 2) * 4;
458 height0
= ALIGN(height0
, 2) * 4;
461 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
464 unreachable("not reached");
467 /* Non-interleaved */
468 depth0
*= num_samples
;
472 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
473 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
474 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
475 * used on Gen8 to make it pick a qpitch value which doesn't include space
476 * for the mipmaps. On Gen9 this is not necessary because it will
477 * automatically pick a packed qpitch value whenever mt->first_level ==
479 * TODO: can we use it elsewhere?
480 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
483 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
485 switch (mt
->msaa_layout
) {
486 case INTEL_MSAA_LAYOUT_NONE
:
487 case INTEL_MSAA_LAYOUT_IMS
:
488 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
490 case INTEL_MSAA_LAYOUT_UMS
:
491 case INTEL_MSAA_LAYOUT_CMS
:
492 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
497 if (target
== GL_TEXTURE_CUBE_MAP
) {
502 mt
->physical_width0
= width0
;
503 mt
->physical_height0
= height0
;
504 mt
->physical_depth0
= depth0
;
506 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
507 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
508 (brw
->must_use_separate_stencil
||
509 (brw
->has_separate_stencil
&&
510 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
511 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
513 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
514 MIPTREE_LAYOUT_TILING_ANY
;
517 mt
->stencil_mt
= intel_miptree_create(brw
,
528 if (!mt
->stencil_mt
) {
529 intel_miptree_release(&mt
);
533 /* Fix up the Z miptree format for how we're splitting out separate
534 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
536 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
539 if (format
== mt
->format
) {
540 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
541 _mesa_get_format_name(mt
->format
));
545 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
546 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
549 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
550 * multisampled or have an AUX buffer attached to it.
552 * GEN | MSRT | AUX_CCS_* or AUX_MCS
553 * -------------------------------------------
554 * 9 | HALIGN_16 | HALIGN_16
555 * 8 | HALIGN_ANY | HALIGN_16
559 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
560 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
561 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
562 } else if (brw
->gen
>= 9 && num_samples
> 1) {
563 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
565 /* For now, nothing else has this requirement */
566 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
569 brw_miptree_layout(brw
, mt
, layout_flags
);
571 if (mt
->disable_aux_buffers
)
572 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
579 * Choose an appropriate uncompressed format for a requested
580 * compressed format, if unsupported.
583 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
585 /* No need to lower ETC formats on these platforms,
586 * they are supported natively.
588 if (brw
->gen
>= 8 || brw
->is_baytrail
)
592 case MESA_FORMAT_ETC1_RGB8
:
593 return MESA_FORMAT_R8G8B8X8_UNORM
;
594 case MESA_FORMAT_ETC2_RGB8
:
595 return MESA_FORMAT_R8G8B8X8_UNORM
;
596 case MESA_FORMAT_ETC2_SRGB8
:
597 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
598 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
599 return MESA_FORMAT_B8G8R8A8_SRGB
;
600 case MESA_FORMAT_ETC2_RGBA8_EAC
:
601 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
602 return MESA_FORMAT_R8G8B8A8_UNORM
;
603 case MESA_FORMAT_ETC2_R11_EAC
:
604 return MESA_FORMAT_R_UNORM16
;
605 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
606 return MESA_FORMAT_R_SNORM16
;
607 case MESA_FORMAT_ETC2_RG11_EAC
:
608 return MESA_FORMAT_R16G16_UNORM
;
609 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
610 return MESA_FORMAT_R16G16_SNORM
;
612 /* Non ETC1 / ETC2 format */
617 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
619 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
620 unsigned long *pitch
)
622 uint32_t tile_width
, tile_height
;
623 unsigned long stride
, size
, aligned_y
;
625 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
626 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
627 &tile_width
, &tile_height
);
629 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
630 stride
= mt
->total_width
* mt
->cpp
;
631 stride
= ALIGN(stride
, tile_width
);
632 size
= stride
* aligned_y
;
634 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
635 assert(size
% 4096 == 0);
638 assert(size
% (64 * 1024) == 0);
639 *alignment
= 64 * 1024;
645 static struct intel_mipmap_tree
*
646 miptree_create(struct brw_context
*brw
,
655 uint32_t layout_flags
)
657 struct intel_mipmap_tree
*mt
;
658 mesa_format tex_format
= format
;
659 mesa_format etc_format
= MESA_FORMAT_NONE
;
660 uint32_t alloc_flags
= 0;
662 format
= intel_lower_compressed_format(brw
, format
);
664 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
666 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
667 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
668 mt
= intel_miptree_create_layout(brw
, target
, format
,
669 first_level
, last_level
, width0
,
670 height0
, depth0
, num_samples
,
673 * pitch == 0 || height == 0 indicates the null texture
675 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
676 intel_miptree_release(&mt
);
680 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
681 mt
->tiling
= I915_TILING_Y
;
683 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
684 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
687 mt
->etc_format
= etc_format
;
689 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
690 unsigned alignment
= 0;
692 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
694 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
697 if (format
== MESA_FORMAT_S_UINT8
) {
698 /* Align to size of W tile, 64x64. */
699 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
700 ALIGN(mt
->total_width
, 64),
701 ALIGN(mt
->total_height
, 64),
702 mt
->cpp
, &mt
->tiling
, &pitch
,
705 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
706 mt
->total_width
, mt
->total_height
,
707 mt
->cpp
, &mt
->tiling
, &pitch
,
717 struct intel_mipmap_tree
*
718 intel_miptree_create(struct brw_context
*brw
,
727 uint32_t layout_flags
)
729 struct intel_mipmap_tree
*mt
= miptree_create(
731 first_level
, last_level
,
732 width0
, height0
, depth0
, num_samples
,
735 /* If the BO is too large to fit in the aperture, we need to use the
736 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
737 * handle Y-tiling, so we need to fall back to X.
739 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
740 mt
->tiling
== I915_TILING_Y
) {
741 unsigned long pitch
= mt
->pitch
;
742 const uint32_t alloc_flags
=
743 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
744 BO_ALLOC_FOR_RENDER
: 0;
745 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
746 mt
->total_width
, mt
->total_height
);
748 mt
->tiling
= I915_TILING_X
;
749 drm_intel_bo_unreference(mt
->bo
);
750 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
751 mt
->total_width
, mt
->total_height
, mt
->cpp
,
752 &mt
->tiling
, &pitch
, alloc_flags
);
759 intel_miptree_release(&mt
);
764 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
765 assert(mt
->num_samples
> 1);
766 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
767 intel_miptree_release(&mt
);
772 /* If this miptree is capable of supporting fast color clears, set
773 * fast_clear_state appropriately to ensure that fast clears will occur.
774 * Allocation of the MCS miptree will be deferred until the first fast
775 * clear actually occurs.
777 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
778 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
779 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
780 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
786 struct intel_mipmap_tree
*
787 intel_miptree_create_for_bo(struct brw_context
*brw
,
795 uint32_t layout_flags
)
797 struct intel_mipmap_tree
*mt
;
798 uint32_t tiling
, swizzle
;
801 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
803 /* Nothing will be able to use this miptree with the BO if the offset isn't
806 if (tiling
!= I915_TILING_NONE
)
807 assert(offset
% 4096 == 0);
809 /* miptrees can't handle negative pitch. If you need flipping of images,
810 * that's outside of the scope of the mt.
814 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
816 /* The BO already has a tiling format and we shouldn't confuse the lower
817 * layers by making it try to find a tiling format again.
819 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
820 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
822 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
823 mt
= intel_miptree_create_layout(brw
, target
, format
,
825 width
, height
, depth
, 0,
830 drm_intel_bo_reference(bo
);
840 * For a singlesample renderbuffer, this simply wraps the given BO with a
843 * For a multisample renderbuffer, this wraps the window system's
844 * (singlesample) BO with a singlesample miptree attached to the
845 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
846 * that will contain the actual rendering (which is lazily resolved to
847 * irb->singlesample_mt).
850 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
851 struct intel_renderbuffer
*irb
,
853 uint32_t width
, uint32_t height
,
856 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
857 struct intel_mipmap_tree
*multisample_mt
= NULL
;
858 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
859 mesa_format format
= rb
->Format
;
860 int num_samples
= rb
->NumSamples
;
862 /* Only the front and back buffers, which are color buffers, are allocated
863 * through the image loader.
865 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
866 _mesa_get_format_base_format(format
) == GL_RGBA
);
868 singlesample_mt
= intel_miptree_create_for_bo(intel
,
877 if (!singlesample_mt
)
880 /* If this miptree is capable of supporting fast color clears, set
881 * mcs_state appropriately to ensure that fast clears will occur.
882 * Allocation of the MCS miptree will be deferred until the first fast
883 * clear actually occurs.
885 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
886 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
887 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
890 if (num_samples
== 0) {
891 intel_miptree_release(&irb
->mt
);
892 irb
->mt
= singlesample_mt
;
894 assert(!irb
->singlesample_mt
);
896 intel_miptree_release(&irb
->singlesample_mt
);
897 irb
->singlesample_mt
= singlesample_mt
;
900 irb
->mt
->logical_width0
!= width
||
901 irb
->mt
->logical_height0
!= height
) {
902 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
910 irb
->need_downsample
= false;
911 intel_miptree_release(&irb
->mt
);
912 irb
->mt
= multisample_mt
;
918 intel_miptree_release(&irb
->singlesample_mt
);
919 intel_miptree_release(&irb
->mt
);
923 struct intel_mipmap_tree
*
924 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
928 uint32_t num_samples
)
930 struct intel_mipmap_tree
*mt
;
933 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
934 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
935 MIPTREE_LAYOUT_TILING_ANY
;
938 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
939 width
, height
, depth
, num_samples
,
944 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
945 ok
= intel_miptree_alloc_hiz(brw
, mt
);
953 intel_miptree_release(&mt
);
958 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
959 struct intel_mipmap_tree
*src
)
964 intel_miptree_release(dst
);
968 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
976 intel_miptree_release(struct intel_mipmap_tree
**mt
)
981 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
982 if (--(*mt
)->refcount
<= 0) {
985 DBG("%s deleting %p\n", __func__
, *mt
);
987 drm_intel_bo_unreference((*mt
)->bo
);
988 intel_miptree_release(&(*mt
)->stencil_mt
);
989 if ((*mt
)->hiz_buf
) {
990 if ((*mt
)->hiz_buf
->mt
)
991 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
993 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
994 free((*mt
)->hiz_buf
);
996 intel_miptree_release(&(*mt
)->mcs_mt
);
997 intel_resolve_map_clear(&(*mt
)->hiz_map
);
999 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1000 free((*mt
)->level
[i
].slice
);
1010 intel_get_image_dims(struct gl_texture_image
*image
,
1011 int *width
, int *height
, int *depth
)
1013 switch (image
->TexObject
->Target
) {
1014 case GL_TEXTURE_1D_ARRAY
:
1015 /* For a 1D Array texture the OpenGL API will treat the image height as
1016 * the number of array slices. For Intel hardware, we treat the 1D array
1017 * as a 2D Array with a height of 1. So, here we want to swap image
1020 *width
= image
->Width
;
1022 *depth
= image
->Height
;
1025 *width
= image
->Width
;
1026 *height
= image
->Height
;
1027 *depth
= image
->Depth
;
1033 * Can the image be pulled into a unified mipmap tree? This mirrors
1034 * the completeness test in a lot of ways.
1036 * Not sure whether I want to pass gl_texture_image here.
1039 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1040 struct gl_texture_image
*image
)
1042 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1043 GLuint level
= intelImage
->base
.Base
.Level
;
1044 int width
, height
, depth
;
1046 /* glTexImage* choose the texture object based on the target passed in, and
1047 * objects can't change targets over their lifetimes, so this should be
1050 assert(image
->TexObject
->Target
== mt
->target
);
1052 mesa_format mt_format
= mt
->format
;
1053 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1054 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1055 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1056 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1057 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1058 mt_format
= mt
->etc_format
;
1060 if (image
->TexFormat
!= mt_format
)
1063 intel_get_image_dims(image
, &width
, &height
, &depth
);
1065 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1068 int level_depth
= mt
->level
[level
].depth
;
1069 if (mt
->num_samples
> 1) {
1070 switch (mt
->msaa_layout
) {
1071 case INTEL_MSAA_LAYOUT_NONE
:
1072 case INTEL_MSAA_LAYOUT_IMS
:
1074 case INTEL_MSAA_LAYOUT_UMS
:
1075 case INTEL_MSAA_LAYOUT_CMS
:
1076 level_depth
/= mt
->num_samples
;
1081 /* Test image dimensions against the base level image adjusted for
1082 * minification. This will also catch images not present in the
1083 * tree, changed targets, etc.
1085 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1086 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1087 depth
!= level_depth
) {
1091 if (image
->NumSamples
!= mt
->num_samples
)
1099 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1101 GLuint x
, GLuint y
, GLuint d
)
1103 mt
->level
[level
].depth
= d
;
1104 mt
->level
[level
].level_x
= x
;
1105 mt
->level
[level
].level_y
= y
;
1107 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1110 assert(mt
->level
[level
].slice
== NULL
);
1112 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1113 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1114 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1119 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1120 GLuint level
, GLuint img
,
1123 if (img
== 0 && level
== 0)
1124 assert(x
== 0 && y
== 0);
1126 assert(img
< mt
->level
[level
].depth
);
1128 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1129 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1131 DBG("%s level %d img %d pos %d,%d\n",
1132 __func__
, level
, img
,
1133 mt
->level
[level
].slice
[img
].x_offset
,
1134 mt
->level
[level
].slice
[img
].y_offset
);
1138 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1139 GLuint level
, GLuint slice
,
1140 GLuint
*x
, GLuint
*y
)
1142 assert(slice
< mt
->level
[level
].depth
);
1144 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1145 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1150 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1151 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1152 * and tile_h is set to 1.
1155 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1156 uint32_t *tile_w
, uint32_t *tile_h
)
1158 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1168 case I915_TILING_NONE
:
1173 unreachable("not reached");
1176 uint32_t aspect_ratio
= 1;
1177 assert(_mesa_is_pow_two(cpp
));
1192 unreachable("not reached");
1195 if (cpp
== 2 || cpp
== 8)
1198 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1201 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1207 * This function computes masks that may be used to select the bits of the X
1208 * and Y coordinates that indicate the offset within a tile. If the BO is
1209 * untiled, the masks are set to 0.
1212 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1213 bool map_stencil_as_y_tiled
,
1214 uint32_t *mask_x
, uint32_t *mask_y
)
1216 uint32_t tile_w_bytes
, tile_h
;
1217 if (map_stencil_as_y_tiled
)
1218 tiling
= I915_TILING_Y
;
1220 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1222 *mask_x
= tile_w_bytes
/ cpp
- 1;
1223 *mask_y
= tile_h
- 1;
1227 * Compute the offset (in bytes) from the start of the BO to the given x
1228 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1229 * multiples of the tile size.
1232 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1233 uint32_t x
, uint32_t y
,
1234 bool map_stencil_as_y_tiled
)
1237 uint32_t pitch
= mt
->pitch
;
1238 uint32_t tiling
= mt
->tiling
;
1240 if (map_stencil_as_y_tiled
) {
1241 tiling
= I915_TILING_Y
;
1243 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1244 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1245 * the resulting surface is twice the pitch of the original miptree,
1246 * since each row in the Y-tiled view corresponds to two rows in the
1247 * actual W-tiled surface. So we need to correct the pitch before
1248 * computing the offsets.
1255 unreachable("not reached");
1256 case I915_TILING_NONE
:
1257 return y
* pitch
+ x
* cpp
;
1259 assert((x
% (512 / cpp
)) == 0);
1260 assert((y
% 8) == 0);
1261 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1263 assert((x
% (128 / cpp
)) == 0);
1264 assert((y
% 32) == 0);
1265 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1270 * Rendering with tiled buffers requires that the base address of the buffer
1271 * be aligned to a page boundary. For renderbuffers, and sometimes with
1272 * textures, we may want the surface to point at a texture image level that
1273 * isn't at a page boundary.
1275 * This function returns an appropriately-aligned base offset
1276 * according to the tiling restrictions, plus any required x/y offset
1280 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1281 GLuint level
, GLuint slice
,
1286 uint32_t mask_x
, mask_y
;
1288 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1289 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1291 *tile_x
= x
& mask_x
;
1292 *tile_y
= y
& mask_y
;
1294 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1298 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1299 struct intel_mipmap_tree
*dst_mt
,
1300 struct intel_mipmap_tree
*src_mt
,
1307 ptrdiff_t src_stride
, dst_stride
;
1308 int cpp
= dst_mt
->cpp
;
1310 intel_miptree_map(brw
, src_mt
,
1314 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1317 intel_miptree_map(brw
, dst_mt
,
1321 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1325 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1326 _mesa_get_format_name(src_mt
->format
),
1327 src_mt
, src
, src_stride
,
1328 _mesa_get_format_name(dst_mt
->format
),
1329 dst_mt
, dst
, dst_stride
,
1332 int row_size
= cpp
* width
;
1333 if (src_stride
== row_size
&&
1334 dst_stride
== row_size
) {
1335 memcpy(dst
, src
, row_size
* height
);
1337 for (int i
= 0; i
< height
; i
++) {
1338 memcpy(dst
, src
, row_size
);
1344 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1345 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1347 /* Don't forget to copy the stencil data over, too. We could have skipped
1348 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1349 * shuffling the two data sources in/out of temporary storage instead of
1350 * the direct mapping we get this way.
1352 if (dst_mt
->stencil_mt
) {
1353 assert(src_mt
->stencil_mt
);
1354 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1355 level
, slice
, width
, height
);
1360 intel_miptree_copy_slice(struct brw_context
*brw
,
1361 struct intel_mipmap_tree
*dst_mt
,
1362 struct intel_mipmap_tree
*src_mt
,
1368 mesa_format format
= src_mt
->format
;
1369 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1370 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1378 assert(depth
< src_mt
->level
[level
].depth
);
1379 assert(src_mt
->format
== dst_mt
->format
);
1381 if (dst_mt
->compressed
) {
1383 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1384 height
= ALIGN_NPOT(height
, j
) / j
;
1385 width
= ALIGN_NPOT(width
, i
) / i
;
1388 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1389 * below won't apply since we can't do the depth's Y tiling or the
1390 * stencil's W tiling in the blitter.
1392 if (src_mt
->stencil_mt
) {
1393 intel_miptree_copy_slice_sw(brw
,
1400 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1401 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1402 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1404 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1405 _mesa_get_format_name(src_mt
->format
),
1406 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1407 _mesa_get_format_name(dst_mt
->format
),
1408 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1411 if (!intel_miptree_blit(brw
,
1412 src_mt
, level
, slice
, 0, 0, false,
1413 dst_mt
, level
, slice
, 0, 0, false,
1414 width
, height
, GL_COPY
)) {
1415 perf_debug("miptree validate blit for %s failed\n",
1416 _mesa_get_format_name(format
));
1418 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1424 * Copies the image's current data to the given miptree, and associates that
1425 * miptree with the image.
1427 * If \c invalidate is true, then the actual image data does not need to be
1428 * copied, but the image still needs to be associated to the new miptree (this
1429 * is set to true if we're about to clear the image).
1432 intel_miptree_copy_teximage(struct brw_context
*brw
,
1433 struct intel_texture_image
*intelImage
,
1434 struct intel_mipmap_tree
*dst_mt
,
1437 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1438 struct intel_texture_object
*intel_obj
=
1439 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1440 int level
= intelImage
->base
.Base
.Level
;
1441 int face
= intelImage
->base
.Base
.Face
;
1444 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1445 depth
= intelImage
->base
.Base
.Height
;
1447 depth
= intelImage
->base
.Base
.Depth
;
1450 for (int slice
= 0; slice
< depth
; slice
++) {
1451 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1455 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1456 intel_obj
->needs_validate
= true;
1460 intel_miptree_init_mcs(struct brw_context
*brw
,
1461 struct intel_mipmap_tree
*mt
,
1464 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1466 * When MCS buffer is enabled and bound to MSRT, it is required that it
1467 * is cleared prior to any rendering.
1469 * Since we don't use the MCS buffer for any purpose other than rendering,
1470 * it makes sense to just clear it immediately upon allocation.
1472 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1474 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1475 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1476 intel_miptree_unmap_raw(mt
->mcs_mt
);
1477 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1481 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1482 struct intel_mipmap_tree
*mt
,
1485 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1486 assert(mt
->mcs_mt
== NULL
);
1487 assert(!mt
->disable_aux_buffers
);
1489 /* Choose the correct format for the MCS buffer. All that really matters
1490 * is that we allocate the right buffer size, since we'll always be
1491 * accessing this miptree using MCS-specific hardware mechanisms, which
1492 * infer the correct format based on num_samples.
1495 switch (num_samples
) {
1498 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1501 format
= MESA_FORMAT_R_UNORM8
;
1504 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1505 * for each sample, plus 8 padding bits).
1507 format
= MESA_FORMAT_R_UINT32
;
1510 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1513 format
= MESA_FORMAT_RG_UINT32
;
1516 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1519 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1521 * "The MCS surface must be stored as Tile Y."
1523 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1524 MIPTREE_LAYOUT_TILING_Y
;
1525 mt
->mcs_mt
= miptree_create(brw
,
1531 mt
->logical_height0
,
1533 0 /* num_samples */,
1536 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1543 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1544 struct intel_mipmap_tree
*mt
)
1546 assert(mt
->mcs_mt
== NULL
);
1547 assert(!mt
->disable_aux_buffers
);
1549 /* The format of the MCS buffer is opaque to the driver; all that matters
1550 * is that we get its size and pitch right. We'll pretend that the format
1551 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1552 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1553 * the block width and then a further factor of 4. Since an MCS tile
1554 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1555 * we'll need to scale the height down by the block height and then a
1556 * further factor of 8.
1558 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1559 unsigned block_width_px
;
1560 unsigned block_height
;
1561 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1562 unsigned width_divisor
= block_width_px
* 4;
1563 unsigned height_divisor
= block_height
* 8;
1565 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1567 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1568 * in the main surface. In Skylake, it's two bits. The extra bit
1569 * doubles the MCS height, not width, because in Skylake the MCS is always
1573 height_divisor
/= 2;
1575 unsigned mcs_width
=
1576 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1577 unsigned mcs_height
=
1578 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1579 assert(mt
->logical_depth0
== 1);
1580 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1581 MIPTREE_LAYOUT_TILING_Y
;
1582 if (brw
->gen
>= 8) {
1583 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1585 mt
->mcs_mt
= miptree_create(brw
,
1593 0 /* num_samples */,
1601 * Helper for intel_miptree_alloc_hiz() that sets
1602 * \c mt->level[level].has_hiz. Return true if and only if
1603 * \c has_hiz was set.
1606 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1607 struct intel_mipmap_tree
*mt
,
1610 assert(mt
->hiz_buf
);
1612 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1613 uint32_t width
= minify(mt
->physical_width0
, level
);
1614 uint32_t height
= minify(mt
->physical_height0
, level
);
1616 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1617 * and the height is 4 aligned. This allows our HiZ support
1618 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1619 * we can grow the width & height to allow the HiZ op to
1620 * force the proper size alignments.
1622 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1623 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1628 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1629 mt
->level
[level
].has_hiz
= true;
1635 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1636 * buffer dimensions and allocates a bo for the hiz buffer.
1638 static struct intel_miptree_aux_buffer
*
1639 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1640 struct intel_mipmap_tree
*mt
)
1642 unsigned z_width
= mt
->logical_width0
;
1643 unsigned z_height
= mt
->logical_height0
;
1644 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1645 unsigned hz_width
, hz_height
;
1646 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1651 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1652 * adjustments required for Z_Height and Z_Width based on multisampling.
1654 switch (mt
->num_samples
) {
1668 unreachable("unsupported sample count");
1671 const unsigned vertical_align
= 8; /* 'j' in the docs */
1672 const unsigned H0
= z_height
;
1673 const unsigned h0
= ALIGN(H0
, vertical_align
);
1674 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1675 const unsigned Z0
= z_depth
;
1677 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1678 hz_width
= ALIGN(z_width
, 16);
1680 if (mt
->target
== GL_TEXTURE_3D
) {
1684 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1685 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1686 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1687 hz_height
+= h_i
* Z_i
;
1688 H_i
= minify(H_i
, 1);
1689 Z_i
= minify(Z_i
, 1);
1692 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1694 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1696 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1697 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1698 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1699 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1700 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1702 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1703 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1707 unsigned long pitch
;
1708 uint32_t tiling
= I915_TILING_Y
;
1709 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1710 hz_width
, hz_height
, 1,
1712 BO_ALLOC_FOR_RENDER
);
1716 } else if (tiling
!= I915_TILING_Y
) {
1717 drm_intel_bo_unreference(buf
->bo
);
1729 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1730 * buffer dimensions and allocates a bo for the hiz buffer.
1732 static struct intel_miptree_aux_buffer
*
1733 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1734 struct intel_mipmap_tree
*mt
)
1736 unsigned z_width
= mt
->logical_width0
;
1737 unsigned z_height
= mt
->logical_height0
;
1738 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1739 unsigned hz_width
, hz_height
;
1740 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1745 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1746 * adjustments required for Z_Height and Z_Width based on multisampling.
1749 switch (mt
->num_samples
) {
1763 unreachable("unsupported sample count");
1767 const unsigned vertical_align
= 8; /* 'j' in the docs */
1768 const unsigned H0
= z_height
;
1769 const unsigned h0
= ALIGN(H0
, vertical_align
);
1770 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1771 const unsigned Z0
= z_depth
;
1773 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1774 hz_width
= ALIGN(z_width
, 16);
1778 unsigned sum_h_i
= 0;
1779 unsigned hz_height_3d_sum
= 0;
1780 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1781 unsigned i
= level
- mt
->first_level
;
1782 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1783 /* sum(i=2 to m; h_i) */
1787 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1788 hz_height_3d_sum
+= h_i
* Z_i
;
1789 H_i
= minify(H_i
, 1);
1790 Z_i
= minify(Z_i
, 1);
1792 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1793 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1795 if (mt
->target
== GL_TEXTURE_3D
) {
1796 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1797 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1799 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1800 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1801 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1802 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1803 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1805 * We can can just take our hz_height calculation from above, and
1806 * multiply by 6 for the cube map and cube map array types.
1812 unsigned long pitch
;
1813 uint32_t tiling
= I915_TILING_Y
;
1814 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1815 hz_width
, hz_height
, 1,
1817 BO_ALLOC_FOR_RENDER
);
1821 } else if (tiling
!= I915_TILING_Y
) {
1822 drm_intel_bo_unreference(buf
->bo
);
1833 static struct intel_miptree_aux_buffer
*
1834 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1835 struct intel_mipmap_tree
*mt
)
1837 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1838 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1841 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1846 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1847 buf
->mt
= intel_miptree_create(brw
,
1853 mt
->logical_height0
,
1862 buf
->bo
= buf
->mt
->bo
;
1863 buf
->pitch
= buf
->mt
->pitch
;
1864 buf
->qpitch
= buf
->mt
->qpitch
;
1870 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1871 struct intel_mipmap_tree
*mt
)
1876 if (mt
->hiz_buf
!= NULL
)
1879 if (mt
->disable_aux_buffers
)
1882 switch (mt
->format
) {
1883 case MESA_FORMAT_Z_FLOAT32
:
1884 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1885 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1886 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1887 case MESA_FORMAT_Z_UNORM16
:
1895 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1896 struct intel_mipmap_tree
*mt
)
1898 assert(mt
->hiz_buf
== NULL
);
1899 assert(!mt
->disable_aux_buffers
);
1901 if (brw
->gen
== 7) {
1902 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1903 } else if (brw
->gen
>= 8) {
1904 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1906 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1912 /* Mark that all slices need a HiZ resolve. */
1913 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1914 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1917 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1918 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1919 exec_node_init(&m
->link
);
1922 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1924 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1932 * Does the miptree slice have hiz enabled?
1935 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1937 intel_miptree_check_level_layer(mt
, level
, 0);
1938 return mt
->level
[level
].has_hiz
;
1942 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1946 if (!intel_miptree_level_has_hiz(mt
, level
))
1949 intel_resolve_map_set(&mt
->hiz_map
,
1950 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1955 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1959 if (!intel_miptree_level_has_hiz(mt
, level
))
1962 intel_resolve_map_set(&mt
->hiz_map
,
1963 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1967 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1971 uint32_t end_layer
= mt
->level
[level
].depth
;
1973 for (layer
= 0; layer
< end_layer
; layer
++) {
1974 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1979 intel_miptree_slice_resolve(struct brw_context
*brw
,
1980 struct intel_mipmap_tree
*mt
,
1983 enum gen6_hiz_op need
)
1985 intel_miptree_check_level_layer(mt
, level
, layer
);
1987 struct intel_resolve_map
*item
=
1988 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1990 if (!item
|| item
->need
!= need
)
1993 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1994 intel_resolve_map_remove(item
);
1999 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2000 struct intel_mipmap_tree
*mt
,
2004 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2005 GEN6_HIZ_OP_HIZ_RESOLVE
);
2009 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2010 struct intel_mipmap_tree
*mt
,
2014 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2015 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2019 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2020 struct intel_mipmap_tree
*mt
,
2021 enum gen6_hiz_op need
)
2023 bool did_resolve
= false;
2025 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2026 if (map
->need
!= need
)
2029 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2030 intel_resolve_map_remove(map
);
2038 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2039 struct intel_mipmap_tree
*mt
)
2041 return intel_miptree_all_slices_resolve(brw
, mt
,
2042 GEN6_HIZ_OP_HIZ_RESOLVE
);
2046 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2047 struct intel_mipmap_tree
*mt
)
2049 return intel_miptree_all_slices_resolve(brw
, mt
,
2050 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2055 intel_miptree_resolve_color(struct brw_context
*brw
,
2056 struct intel_mipmap_tree
*mt
,
2059 /* From gen9 onwards there is new compression scheme for single sampled
2060 * surfaces called "lossless compressed". These don't need to be always
2063 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2064 intel_miptree_is_lossless_compressed(brw
, mt
))
2067 switch (mt
->fast_clear_state
) {
2068 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2069 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2070 /* No resolve needed */
2072 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2073 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2074 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2075 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2076 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2077 brw_blorp_resolve_color(brw
, mt
);
2085 * Make it possible to share the BO backing the given miptree with another
2086 * process or another miptree.
2088 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2089 * then discard the MCS buffer, if present. We also set the fast_clear_state
2090 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2091 * allocated in the future.
2094 intel_miptree_make_shareable(struct brw_context
*brw
,
2095 struct intel_mipmap_tree
*mt
)
2097 /* MCS buffers are also used for multisample buffers, but we can't resolve
2098 * away a multisample MCS buffer because it's an integral part of how the
2099 * pixel data is stored. Fortunately this code path should never be
2100 * reached for multisample buffers.
2102 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2105 intel_miptree_resolve_color(brw
, mt
, 0);
2106 intel_miptree_release(&mt
->mcs_mt
);
2107 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2113 * \brief Get pointer offset into stencil buffer.
2115 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2116 * must decode the tile's layout in software.
2119 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2121 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2123 * Even though the returned offset is always positive, the return type is
2125 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2126 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2129 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2131 uint32_t tile_size
= 4096;
2132 uint32_t tile_width
= 64;
2133 uint32_t tile_height
= 64;
2134 uint32_t row_size
= 64 * stride
;
2136 uint32_t tile_x
= x
/ tile_width
;
2137 uint32_t tile_y
= y
/ tile_height
;
2139 /* The byte's address relative to the tile's base addres. */
2140 uint32_t byte_x
= x
% tile_width
;
2141 uint32_t byte_y
= y
% tile_height
;
2143 uintptr_t u
= tile_y
* row_size
2144 + tile_x
* tile_size
2145 + 512 * (byte_x
/ 8)
2147 + 32 * ((byte_y
/ 4) % 2)
2148 + 16 * ((byte_x
/ 4) % 2)
2149 + 8 * ((byte_y
/ 2) % 2)
2150 + 4 * ((byte_x
/ 2) % 2)
2155 /* adjust for bit6 swizzling */
2156 if (((byte_x
/ 8) % 2) == 1) {
2157 if (((byte_y
/ 8) % 2) == 0) {
2169 intel_miptree_updownsample(struct brw_context
*brw
,
2170 struct intel_mipmap_tree
*src
,
2171 struct intel_mipmap_tree
*dst
)
2173 /* There is support for only up to eight samples. */
2174 const bool use_blorp
= src
->num_samples
<= 8 && dst
->num_samples
<= 8;
2177 brw_blorp_blit_miptrees(brw
,
2178 src
, 0 /* level */, 0 /* layer */,
2179 src
->format
, SWIZZLE_XYZW
,
2180 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2182 src
->logical_width0
, src
->logical_height0
,
2184 dst
->logical_width0
, dst
->logical_height0
,
2185 GL_NEAREST
, false, false /*mirror x, y*/,
2187 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2188 brw_meta_stencil_updownsample(brw
, src
, dst
);
2190 brw_meta_updownsample(brw
, src
, dst
);
2193 if (src
->stencil_mt
) {
2195 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2199 brw_blorp_blit_miptrees(brw
,
2200 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2201 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2202 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2203 dst
->stencil_mt
->format
,
2205 src
->logical_width0
, src
->logical_height0
,
2207 dst
->logical_width0
, dst
->logical_height0
,
2208 GL_NEAREST
, false, false /*mirror x, y*/,
2209 false, false /* decode/encode srgb */);
2214 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2216 /* CPU accesses to color buffers don't understand fast color clears, so
2217 * resolve any pending fast color clears before we map.
2219 intel_miptree_resolve_color(brw
, mt
, 0);
2221 drm_intel_bo
*bo
= mt
->bo
;
2223 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2224 intel_batchbuffer_flush(brw
);
2226 if (mt
->tiling
!= I915_TILING_NONE
)
2227 brw_bo_map_gtt(brw
, bo
, "miptree");
2229 brw_bo_map(brw
, bo
, true, "miptree");
2235 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2237 drm_intel_bo_unmap(mt
->bo
);
2241 intel_miptree_map_gtt(struct brw_context
*brw
,
2242 struct intel_mipmap_tree
*mt
,
2243 struct intel_miptree_map
*map
,
2244 unsigned int level
, unsigned int slice
)
2246 unsigned int bw
, bh
;
2248 unsigned int image_x
, image_y
;
2249 intptr_t x
= map
->x
;
2250 intptr_t y
= map
->y
;
2252 /* For compressed formats, the stride is the number of bytes per
2253 * row of blocks. intel_miptree_get_image_offset() already does
2256 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2257 assert(y
% bh
== 0);
2258 assert(x
% bw
== 0);
2262 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2267 /* Note that in the case of cube maps, the caller must have passed the
2268 * slice number referencing the face.
2270 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2274 map
->stride
= mt
->pitch
;
2275 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2278 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2279 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2280 map
->x
, map
->y
, map
->w
, map
->h
,
2281 mt
, _mesa_get_format_name(mt
->format
),
2282 x
, y
, map
->ptr
, map
->stride
);
2286 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2288 intel_miptree_unmap_raw(mt
);
2292 intel_miptree_map_blit(struct brw_context
*brw
,
2293 struct intel_mipmap_tree
*mt
,
2294 struct intel_miptree_map
*map
,
2295 unsigned int level
, unsigned int slice
)
2297 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2298 /* first_level */ 0,
2302 MIPTREE_LAYOUT_TILING_NONE
);
2304 if (!map
->linear_mt
) {
2305 fprintf(stderr
, "Failed to allocate blit temporary\n");
2308 map
->stride
= map
->linear_mt
->pitch
;
2310 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2311 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2312 * invalidate is set, since we'll be writing the whole rectangle from our
2313 * temporary buffer back out.
2315 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2316 if (!intel_miptree_blit(brw
,
2318 map
->x
, map
->y
, false,
2319 map
->linear_mt
, 0, 0,
2321 map
->w
, map
->h
, GL_COPY
)) {
2322 fprintf(stderr
, "Failed to blit\n");
2327 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2329 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2330 map
->x
, map
->y
, map
->w
, map
->h
,
2331 mt
, _mesa_get_format_name(mt
->format
),
2332 level
, slice
, map
->ptr
, map
->stride
);
2337 intel_miptree_release(&map
->linear_mt
);
2343 intel_miptree_unmap_blit(struct brw_context
*brw
,
2344 struct intel_mipmap_tree
*mt
,
2345 struct intel_miptree_map
*map
,
2349 struct gl_context
*ctx
= &brw
->ctx
;
2351 intel_miptree_unmap_raw(map
->linear_mt
);
2353 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2354 bool ok
= intel_miptree_blit(brw
,
2355 map
->linear_mt
, 0, 0,
2358 map
->x
, map
->y
, false,
2359 map
->w
, map
->h
, GL_COPY
);
2360 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2363 intel_miptree_release(&map
->linear_mt
);
2367 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2369 #if defined(USE_SSE41)
2371 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2372 struct intel_mipmap_tree
*mt
,
2373 struct intel_miptree_map
*map
,
2374 unsigned int level
, unsigned int slice
)
2376 assert(map
->mode
& GL_MAP_READ_BIT
);
2377 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2379 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2380 map
->x
, map
->y
, map
->w
, map
->h
,
2381 mt
, _mesa_get_format_name(mt
->format
),
2382 level
, slice
, map
->ptr
, map
->stride
);
2384 /* Map the original image */
2387 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2391 void *src
= intel_miptree_map_raw(brw
, mt
);
2394 src
+= image_y
* mt
->pitch
;
2395 src
+= image_x
* mt
->cpp
;
2397 /* Due to the pixel offsets for the particular image being mapped, our
2398 * src pointer may not be 16-byte aligned. However, if the pitch is
2399 * divisible by 16, then the amount by which it's misaligned will remain
2400 * consistent from row to row.
2402 assert((mt
->pitch
% 16) == 0);
2403 const int misalignment
= ((uintptr_t) src
) & 15;
2405 /* Create an untiled temporary buffer for the mapping. */
2406 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2408 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2410 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2411 /* Offset the destination so it has the same misalignment as src. */
2412 map
->ptr
= map
->buffer
+ misalignment
;
2414 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2416 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2417 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2418 void *src_ptr
= src
+ y
* mt
->pitch
;
2420 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2423 intel_miptree_unmap_raw(mt
);
2427 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2428 struct intel_mipmap_tree
*mt
,
2429 struct intel_miptree_map
*map
,
2433 _mesa_align_free(map
->buffer
);
2440 intel_miptree_map_s8(struct brw_context
*brw
,
2441 struct intel_mipmap_tree
*mt
,
2442 struct intel_miptree_map
*map
,
2443 unsigned int level
, unsigned int slice
)
2445 map
->stride
= map
->w
;
2446 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2450 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2451 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2452 * invalidate is set, since we'll be writing the whole rectangle from our
2453 * temporary buffer back out.
2455 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2456 uint8_t *untiled_s8_map
= map
->ptr
;
2457 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2458 unsigned int image_x
, image_y
;
2460 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2462 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2463 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2464 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2465 x
+ image_x
+ map
->x
,
2466 y
+ image_y
+ map
->y
,
2467 brw
->has_swizzling
);
2468 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2472 intel_miptree_unmap_raw(mt
);
2474 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2475 map
->x
, map
->y
, map
->w
, map
->h
,
2476 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2478 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2479 map
->x
, map
->y
, map
->w
, map
->h
,
2480 mt
, map
->ptr
, map
->stride
);
2485 intel_miptree_unmap_s8(struct brw_context
*brw
,
2486 struct intel_mipmap_tree
*mt
,
2487 struct intel_miptree_map
*map
,
2491 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2492 unsigned int image_x
, image_y
;
2493 uint8_t *untiled_s8_map
= map
->ptr
;
2494 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2496 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2498 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2499 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2500 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2501 image_x
+ x
+ map
->x
,
2502 image_y
+ y
+ map
->y
,
2503 brw
->has_swizzling
);
2504 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2508 intel_miptree_unmap_raw(mt
);
2515 intel_miptree_map_etc(struct brw_context
*brw
,
2516 struct intel_mipmap_tree
*mt
,
2517 struct intel_miptree_map
*map
,
2521 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2522 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2523 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2526 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2527 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2529 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2530 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2531 map
->w
, map
->h
, 1));
2532 map
->ptr
= map
->buffer
;
2536 intel_miptree_unmap_etc(struct brw_context
*brw
,
2537 struct intel_mipmap_tree
*mt
,
2538 struct intel_miptree_map
*map
,
2544 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2549 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2550 + image_y
* mt
->pitch
2551 + image_x
* mt
->cpp
;
2553 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2554 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2555 map
->ptr
, map
->stride
,
2558 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2559 map
->ptr
, map
->stride
,
2560 map
->w
, map
->h
, mt
->etc_format
);
2562 intel_miptree_unmap_raw(mt
);
2567 * Mapping function for packed depth/stencil miptrees backed by real separate
2568 * miptrees for depth and stencil.
2570 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2571 * separate from the depth buffer. Yet at the GL API level, we have to expose
2572 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2573 * be able to map that memory for texture storage and glReadPixels-type
2574 * operations. We give Mesa core that access by mallocing a temporary and
2575 * copying the data between the actual backing store and the temporary.
2578 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2579 struct intel_mipmap_tree
*mt
,
2580 struct intel_miptree_map
*map
,
2581 unsigned int level
, unsigned int slice
)
2583 struct intel_mipmap_tree
*z_mt
= mt
;
2584 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2585 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2586 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2588 map
->stride
= map
->w
* packed_bpp
;
2589 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2593 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2594 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2595 * invalidate is set, since we'll be writing the whole rectangle from our
2596 * temporary buffer back out.
2598 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2599 uint32_t *packed_map
= map
->ptr
;
2600 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2601 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2602 unsigned int s_image_x
, s_image_y
;
2603 unsigned int z_image_x
, z_image_y
;
2605 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2606 &s_image_x
, &s_image_y
);
2607 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2608 &z_image_x
, &z_image_y
);
2610 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2611 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2612 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2613 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2616 brw
->has_swizzling
);
2617 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2619 (map_x
+ z_image_x
));
2620 uint8_t s
= s_map
[s_offset
];
2621 uint32_t z
= z_map
[z_offset
];
2623 if (map_z32f_x24s8
) {
2624 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2625 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2627 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2632 intel_miptree_unmap_raw(s_mt
);
2633 intel_miptree_unmap_raw(z_mt
);
2635 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2637 map
->x
, map
->y
, map
->w
, map
->h
,
2638 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2639 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2640 map
->ptr
, map
->stride
);
2642 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2643 map
->x
, map
->y
, map
->w
, map
->h
,
2644 mt
, map
->ptr
, map
->stride
);
2649 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2650 struct intel_mipmap_tree
*mt
,
2651 struct intel_miptree_map
*map
,
2655 struct intel_mipmap_tree
*z_mt
= mt
;
2656 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2657 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2659 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2660 uint32_t *packed_map
= map
->ptr
;
2661 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2662 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2663 unsigned int s_image_x
, s_image_y
;
2664 unsigned int z_image_x
, z_image_y
;
2666 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2667 &s_image_x
, &s_image_y
);
2668 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2669 &z_image_x
, &z_image_y
);
2671 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2672 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2673 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2674 x
+ s_image_x
+ map
->x
,
2675 y
+ s_image_y
+ map
->y
,
2676 brw
->has_swizzling
);
2677 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2679 (x
+ z_image_x
+ map
->x
));
2681 if (map_z32f_x24s8
) {
2682 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2683 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2685 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2686 s_map
[s_offset
] = packed
>> 24;
2687 z_map
[z_offset
] = packed
;
2692 intel_miptree_unmap_raw(s_mt
);
2693 intel_miptree_unmap_raw(z_mt
);
2695 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2697 map
->x
, map
->y
, map
->w
, map
->h
,
2698 z_mt
, _mesa_get_format_name(z_mt
->format
),
2699 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2700 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2701 map
->ptr
, map
->stride
);
2708 * Create and attach a map to the miptree at (level, slice). Return the
2711 static struct intel_miptree_map
*
2712 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2721 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2726 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2727 mt
->level
[level
].slice
[slice
].map
= map
;
2739 * Release the map at (level, slice).
2742 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2746 struct intel_miptree_map
**map
;
2748 map
= &mt
->level
[level
].slice
[slice
].map
;
2754 can_blit_slice(struct intel_mipmap_tree
*mt
,
2755 unsigned int level
, unsigned int slice
)
2759 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2760 if (image_x
>= 32768 || image_y
>= 32768)
2763 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2764 if (mt
->pitch
>= 32768)
2771 use_intel_mipree_map_blit(struct brw_context
*brw
,
2772 struct intel_mipmap_tree
*mt
,
2778 /* It's probably not worth swapping to the blit ring because of
2779 * all the overhead involved. But, we must use blitter for the
2780 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2782 (!(mode
& GL_MAP_WRITE_BIT
) ||
2783 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2785 (mt
->tiling
== I915_TILING_X
||
2786 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2787 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2788 /* Fast copy blit on skl+ supports all tiling formats. */
2790 can_blit_slice(mt
, level
, slice
))
2793 if (mt
->tiling
!= I915_TILING_NONE
&&
2794 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2795 assert(can_blit_slice(mt
, level
, slice
));
2803 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2804 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2805 * arithmetic overflow.
2807 * If you call this function and use \a out_stride, then you're doing pointer
2808 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2809 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2810 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2811 * which usually have type uint32_t or GLuint.
2814 intel_miptree_map(struct brw_context
*brw
,
2815 struct intel_mipmap_tree
*mt
,
2824 ptrdiff_t *out_stride
)
2826 struct intel_miptree_map
*map
;
2828 assert(mt
->num_samples
<= 1);
2830 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2837 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2838 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2839 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2842 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2843 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2844 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2845 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2846 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2847 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2848 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2849 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2850 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2851 #if defined(USE_SSE41)
2852 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2853 !mt
->compressed
&& cpu_has_sse4_1
&&
2854 (mt
->pitch
% 16 == 0)) {
2855 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2858 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2859 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2860 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2863 *out_ptr
= map
->ptr
;
2864 *out_stride
= map
->stride
;
2866 if (map
->ptr
== NULL
)
2867 intel_miptree_release_map(mt
, level
, slice
);
2871 intel_miptree_unmap(struct brw_context
*brw
,
2872 struct intel_mipmap_tree
*mt
,
2876 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2878 assert(mt
->num_samples
<= 1);
2883 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2884 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2886 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2887 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2888 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2889 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2890 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2891 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2892 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2893 } else if (map
->linear_mt
) {
2894 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2895 #if defined(USE_SSE41)
2896 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2897 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2900 intel_miptree_unmap_gtt(mt
);
2903 intel_miptree_release_map(mt
, level
, slice
);