2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include "drm-uapi/drm_fourcc.h"
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
49 #include "util/format_srgb.h"
51 #include "x86/common_x86_asm.h"
53 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
55 static void *intel_miptree_map_raw(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*mt
,
59 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
67 /* MCS compression only applies to multisampled miptrees */
68 if (mt
->surf
.samples
<= 1)
71 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
75 /* See isl_surf_get_mcs_surf for details. */
76 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
79 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
80 switch (_mesa_get_format_base_format(mt
->format
)) {
81 case GL_DEPTH_COMPONENT
:
82 case GL_STENCIL_INDEX
:
83 case GL_DEPTH_STENCIL
:
86 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
88 * This field must be set to 0 for all SINT MSRTs when all RT channels
91 * In practice this means that we have to disable MCS for all signed
92 * integer MSAA buffers. The alternative, to disable MCS only when one
93 * of the render target channels is disabled, is impractical because it
94 * would require converting between CMS and UMS MSAA layouts on the fly,
97 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
106 intel_tiling_supports_ccs(const struct brw_context
*brw
,
107 enum isl_tiling tiling
)
109 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
111 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
112 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
114 * - Support is limited to tiled render targets.
116 * Gen9 changes the restriction to Y-tile only.
118 if (devinfo
->gen
>= 9)
119 return tiling
== ISL_TILING_Y0
;
120 else if (devinfo
->gen
>= 7)
121 return tiling
!= ISL_TILING_LINEAR
;
127 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
128 * can be used. This doesn't (and should not) inspect any of the properties of
131 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
132 * beneath the "Fast Color Clear" bullet (p326):
134 * - Support is for non-mip-mapped and non-array surface types only.
136 * And then later, on p327:
138 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
141 * From the Skylake documentation, it is made clear that X-tiling is no longer
144 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
148 intel_miptree_supports_ccs(struct brw_context
*brw
,
149 const struct intel_mipmap_tree
*mt
)
151 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
153 /* MCS support does not exist prior to Gen7 */
154 if (devinfo
->gen
< 7)
157 /* This function applies only to non-multisampled render targets. */
158 if (mt
->surf
.samples
> 1)
161 /* MCS is only supported for color buffers */
162 if (!_mesa_is_format_color_format(mt
->format
))
165 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
168 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
169 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
170 mt
->surf
.logical_level0_px
.depth
> 1;
173 /* Multisample surfaces with the CMS layout are not layered surfaces,
174 * yet still have physical_depth0 > 1. Assert that we don't
175 * accidentally reject a multisampled surface here. We should have
176 * rejected it earlier by explicitly checking the sample count.
178 assert(mt
->surf
.samples
== 1);
181 /* Handle the hardware restrictions...
183 * All GENs have the following restriction: "MCS buffer for non-MSRT is
184 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
186 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
187 * Non-MultiSampler Render Target Restrictions) Support is for
188 * non-mip-mapped and non-array surface types only.
190 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
195 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
196 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
197 * surfaces are supported with MCS buffer layout with these alignments in
198 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
200 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
203 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
204 * work for 3D textures until gen9 where the layout of 3D textures changes
205 * to match 2D array textures.
207 if (devinfo
->gen
<= 8 && mt
->surf
.dim
!= ISL_SURF_DIM_2D
)
210 /* There's no point in using an MCS buffer if the surface isn't in a
213 if (!brw
->mesa_format_supports_render
[mt
->format
])
220 intel_tiling_supports_hiz(const struct brw_context
*brw
,
221 enum isl_tiling tiling
)
223 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
225 if (devinfo
->gen
< 6)
228 return tiling
== ISL_TILING_Y0
;
232 intel_miptree_supports_hiz(const struct brw_context
*brw
,
233 const struct intel_mipmap_tree
*mt
)
238 switch (mt
->format
) {
239 case MESA_FORMAT_Z_FLOAT32
:
240 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
241 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
242 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
243 case MESA_FORMAT_Z_UNORM16
:
251 * Return true if the format that will be used to access the miptree is
252 * CCS_E-compatible with the miptree's linear/non-sRGB format.
254 * Why use the linear format? Well, although the miptree may be specified with
255 * an sRGB format, the usage of that color space/format can be toggled. Since
256 * our HW tends to support more linear formats than sRGB ones, we use this
257 * format variant for check for CCS_E compatibility.
260 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
261 const struct intel_mipmap_tree
*mt
,
262 enum isl_format access_format
)
264 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
266 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
267 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
268 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
272 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
273 const struct intel_mipmap_tree
*mt
)
275 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
277 if (devinfo
->gen
< 9)
280 /* For now compression is only enabled for integer formats even though
281 * there exist supported floating point formats also. This is a heuristic
282 * decision based on current public benchmarks. In none of the cases these
283 * formats provided any improvement but a few cases were seen to regress.
284 * Hence these are left to to be enabled in the future when they are known
287 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
290 if (!intel_miptree_supports_ccs(brw
, mt
))
293 /* Many window system buffers are sRGB even if they are never rendered as
294 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
295 * surface is used as sRGB, we fall back to CCS_D.
297 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
298 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
299 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
303 * Determine depth format corresponding to a depth+stencil format,
304 * for separate stencil.
307 intel_depth_format_for_depthstencil_format(mesa_format format
) {
309 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
310 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
311 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
312 return MESA_FORMAT_Z_FLOAT32
;
319 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
320 unsigned depth0
, struct intel_mipmap_level
*table
)
322 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
324 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
326 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
327 if (!table
[level
].slice
)
334 for (unsigned level
= first_level
; level
<= last_level
; level
++)
335 free(table
[level
].slice
);
341 needs_separate_stencil(const struct brw_context
*brw
,
342 struct intel_mipmap_tree
*mt
,
345 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
347 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
350 if (devinfo
->must_use_separate_stencil
)
353 return brw
->has_separate_stencil
&&
354 intel_miptree_supports_hiz(brw
, mt
);
358 * Choose the aux usage for this miptree. This function must be called fairly
359 * late in the miptree create process after we have a tiling.
362 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
363 struct intel_mipmap_tree
*mt
)
365 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
367 if (intel_miptree_supports_mcs(brw
, mt
)) {
368 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
369 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
370 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
371 intel_miptree_supports_ccs(brw
, mt
)) {
372 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
373 intel_miptree_supports_ccs_e(brw
, mt
)) {
374 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
376 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
378 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
379 intel_miptree_supports_hiz(brw
, mt
)) {
380 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
383 /* We can do fast-clear on all auxiliary surface types that are
384 * allocated through the normal texture creation paths.
386 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
387 mt
->supports_fast_clear
= true;
392 * Choose an appropriate uncompressed format for a requested
393 * compressed format, if unsupported.
396 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
398 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
400 /* No need to lower ETC formats on these platforms,
401 * they are supported natively.
403 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
407 case MESA_FORMAT_ETC1_RGB8
:
408 return MESA_FORMAT_R8G8B8X8_UNORM
;
409 case MESA_FORMAT_ETC2_RGB8
:
410 return MESA_FORMAT_R8G8B8X8_UNORM
;
411 case MESA_FORMAT_ETC2_SRGB8
:
412 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
413 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
414 return MESA_FORMAT_B8G8R8A8_SRGB
;
415 case MESA_FORMAT_ETC2_RGBA8_EAC
:
416 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
417 return MESA_FORMAT_R8G8B8A8_UNORM
;
418 case MESA_FORMAT_ETC2_R11_EAC
:
419 return MESA_FORMAT_R_UNORM16
;
420 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
421 return MESA_FORMAT_R_SNORM16
;
422 case MESA_FORMAT_ETC2_RG11_EAC
:
423 return MESA_FORMAT_R16G16_UNORM
;
424 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
425 return MESA_FORMAT_R16G16_SNORM
;
427 /* Non ETC1 / ETC2 format */
433 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
435 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
436 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
438 return mt
->surf
.logical_level0_px
.array_len
;
441 UNUSED
static unsigned
442 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
444 /* In case of physical dimensions one needs to consider also the layout.
445 * See isl_calc_phys_level0_extent_sa().
447 if (surf
->dim
!= ISL_SURF_DIM_3D
)
448 return surf
->phys_level0_sa
.array_len
;
450 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
451 return minify(surf
->phys_level0_sa
.array_len
, level
);
453 return minify(surf
->phys_level0_sa
.depth
, level
);
456 /** \brief Assert that the level and layer are valid for the miptree. */
458 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
466 assert(level
>= mt
->first_level
);
467 assert(level
<= mt
->last_level
);
468 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
471 static enum isl_aux_state
**
472 create_aux_state_map(struct intel_mipmap_tree
*mt
,
473 enum isl_aux_state initial
)
475 const uint32_t levels
= mt
->last_level
+ 1;
477 uint32_t total_slices
= 0;
478 for (uint32_t level
= 0; level
< levels
; level
++)
479 total_slices
+= brw_get_num_logical_layers(mt
, level
);
481 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
483 /* We're going to allocate a single chunk of data for both the per-level
484 * reference array and the arrays of aux_state. This makes cleanup
485 * significantly easier.
487 const size_t total_size
= per_level_array_size
+
488 total_slices
* sizeof(enum isl_aux_state
);
489 void *data
= malloc(total_size
);
493 enum isl_aux_state
**per_level_arr
= data
;
494 enum isl_aux_state
*s
= data
+ per_level_array_size
;
495 for (uint32_t level
= 0; level
< levels
; level
++) {
496 per_level_arr
[level
] = s
;
497 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
498 for (uint32_t a
= 0; a
< level_layers
; a
++)
501 assert((void *)s
== data
+ total_size
);
503 return per_level_arr
;
507 free_aux_state_map(enum isl_aux_state
**state
)
513 need_to_retile_as_linear(struct brw_context
*brw
, unsigned blt_pitch
,
514 enum isl_tiling tiling
, unsigned samples
)
519 if (tiling
== ISL_TILING_LINEAR
)
522 if (blt_pitch
>= 32768) {
523 perf_debug("blt pitch %u too large to blit, falling back to untiled",
532 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
533 enum isl_tiling tiling
)
535 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
537 /* If the BO is too large to fit in the aperture, we need to use the
538 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
539 * handle Y-tiling, so we need to fall back to X.
541 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
542 tiling
== ISL_TILING_Y0
)
548 static struct intel_mipmap_tree
*
549 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
550 unsigned first_level
, unsigned last_level
,
551 unsigned width0
, unsigned height0
, unsigned depth0
,
552 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
553 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
554 unsigned row_pitch_B
, struct brw_bo
*bo
)
556 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
560 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
568 if (target
== GL_TEXTURE_CUBE_MAP
||
569 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
570 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
572 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
574 _mesa_enum_to_string(target
),
575 _mesa_get_format_name(format
),
576 num_samples
, width0
, height0
, depth0
,
577 first_level
, last_level
, mt
);
579 struct isl_surf_init_info init_info
= {
580 .dim
= get_isl_surf_dim(target
),
581 .format
= translate_tex_format(brw
, format
, false),
584 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
585 .levels
= last_level
- first_level
+ 1,
586 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
587 .samples
= num_samples
,
588 .row_pitch_B
= row_pitch_B
,
589 .usage
= isl_usage_flags
,
590 .tiling_flags
= tiling_flags
,
593 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
596 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
597 * on gen7 platforms we also need to create Y-tiled copies of stencil for
598 * texturing since the hardware can't sample from W-tiled surfaces. For
599 * everything else, check for corner cases needing special treatment.
601 bool is_depth_stencil
=
602 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
603 if (!is_depth_stencil
) {
604 if (need_to_retile_as_linear(brw
, intel_miptree_blt_pitch(mt
),
605 mt
->surf
.tiling
, mt
->surf
.samples
)) {
606 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
607 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
609 } else if (need_to_retile_as_x(brw
, mt
->surf
.size_B
, mt
->surf
.tiling
)) {
610 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
611 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
616 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
617 * the size may not be multiple of row_pitch.
618 * See isl_apply_surface_padding().
620 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
621 assert(mt
->surf
.size_B
% mt
->surf
.row_pitch_B
== 0);
624 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
627 isl_tiling_to_i915_tiling(
629 mt
->surf
.row_pitch_B
, alloc_flags
);
636 mt
->first_level
= first_level
;
637 mt
->last_level
= last_level
;
640 mt
->aux_state
= NULL
;
641 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
642 mt
->compressed
= _mesa_is_format_compressed(format
);
643 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
648 intel_miptree_release(&mt
);
652 /* Return the usual surface usage flags for the given format. */
653 static isl_surf_usage_flags_t
654 mt_surf_usage(mesa_format format
)
656 switch(_mesa_get_format_base_format(format
)) {
657 case GL_DEPTH_COMPONENT
:
658 return ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
659 case GL_DEPTH_STENCIL
:
660 return ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
661 ISL_SURF_USAGE_TEXTURE_BIT
;
662 case GL_STENCIL_INDEX
:
663 return ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
665 return ISL_SURF_USAGE_RENDER_TARGET_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
669 static struct intel_mipmap_tree
*
670 miptree_create(struct brw_context
*brw
,
679 enum intel_miptree_create_flags flags
)
681 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
682 const uint32_t alloc_flags
=
683 (flags
& MIPTREE_CREATE_BUSY
|| num_samples
> 1) ? BO_ALLOC_BUSY
: 0;
684 isl_tiling_flags_t tiling_flags
= ISL_TILING_ANY_MASK
;
686 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
687 if (devinfo
->gen
< 6 && _mesa_is_format_color_format(format
))
688 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
691 if (_mesa_is_format_color_format(format
)) {
692 mt_fmt
= intel_lower_compressed_format(brw
, format
);
694 /* Fix up the Z miptree format for how we're splitting out separate
695 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
697 mt_fmt
= (devinfo
->gen
< 6) ? format
:
698 intel_depth_format_for_depthstencil_format(format
);
701 struct intel_mipmap_tree
*mt
=
702 make_surface(brw
, target
, mt_fmt
, first_level
, last_level
,
703 width0
, height0
, depth0
, num_samples
,
704 tiling_flags
, mt_surf_usage(mt_fmt
),
705 alloc_flags
, 0, NULL
);
710 if (needs_separate_stencil(brw
, mt
, format
)) {
712 make_surface(brw
, target
, MESA_FORMAT_S_UINT8
, first_level
, last_level
,
713 width0
, height0
, depth0
, num_samples
,
714 ISL_TILING_W_BIT
, mt_surf_usage(MESA_FORMAT_S_UINT8
),
715 alloc_flags
, 0, NULL
);
716 if (mt
->stencil_mt
== NULL
) {
717 intel_miptree_release(&mt
);
722 mt
->etc_format
= (_mesa_is_format_color_format(format
) && mt_fmt
!= format
) ?
723 format
: MESA_FORMAT_NONE
;
725 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
726 intel_miptree_choose_aux_usage(brw
, mt
);
731 struct intel_mipmap_tree
*
732 intel_miptree_create(struct brw_context
*brw
,
741 enum intel_miptree_create_flags flags
)
743 assert(num_samples
> 0);
745 struct intel_mipmap_tree
*mt
= miptree_create(
747 first_level
, last_level
,
748 width0
, height0
, depth0
, num_samples
,
755 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
756 * compress clear color so we wait until an actual fast-clear to allocate
759 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
760 !intel_miptree_alloc_aux(brw
, mt
)) {
761 intel_miptree_release(&mt
);
768 struct intel_mipmap_tree
*
769 intel_miptree_create_for_bo(struct brw_context
*brw
,
777 enum isl_tiling tiling
,
778 enum intel_miptree_create_flags flags
)
780 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
781 struct intel_mipmap_tree
*mt
;
782 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
783 const GLenum base_format
= _mesa_get_format_base_format(format
);
785 if ((base_format
== GL_DEPTH_COMPONENT
||
786 base_format
== GL_DEPTH_STENCIL
)) {
787 const mesa_format mt_fmt
= (devinfo
->gen
< 6) ? format
:
788 intel_depth_format_for_depthstencil_format(format
);
789 mt
= make_surface(brw
, target
, mt_fmt
,
790 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
791 mt_surf_usage(mt_fmt
),
796 brw_bo_reference(bo
);
798 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
799 intel_miptree_choose_aux_usage(brw
, mt
);
802 } else if (format
== MESA_FORMAT_S_UINT8
) {
803 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
804 0, 0, width
, height
, depth
, 1,
806 mt_surf_usage(MESA_FORMAT_S_UINT8
),
811 assert(bo
->size
>= mt
->surf
.size_B
);
813 brw_bo_reference(bo
);
817 /* Nothing will be able to use this miptree with the BO if the offset isn't
820 if (tiling
!= ISL_TILING_LINEAR
)
821 assert(offset
% 4096 == 0);
823 /* miptrees can't handle negative pitch. If you need flipping of images,
824 * that's outside of the scope of the mt.
828 mt
= make_surface(brw
, target
, format
,
829 0, 0, width
, height
, depth
, 1,
831 mt_surf_usage(format
),
836 brw_bo_reference(bo
);
840 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
841 intel_miptree_choose_aux_usage(brw
, mt
);
843 /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
844 * only compress clear color so we wait until an actual fast-clear to
847 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
848 !intel_miptree_alloc_aux(brw
, mt
)) {
849 intel_miptree_release(&mt
);
857 static struct intel_mipmap_tree
*
858 miptree_create_for_planar_image(struct brw_context
*brw
,
859 __DRIimage
*image
, GLenum target
,
860 enum isl_tiling tiling
)
862 const struct intel_image_format
*f
= image
->planar_format
;
863 struct intel_mipmap_tree
*planar_mt
= NULL
;
865 for (int i
= 0; i
< f
->nplanes
; i
++) {
866 const int index
= f
->planes
[i
].buffer_index
;
867 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
868 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
869 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
870 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
872 /* Disable creation of the texture's aux buffers because the driver
873 * exposes no EGL API to manage them. That is, there is no API for
874 * resolving the aux buffer's content to the main buffer nor for
875 * invalidating the aux buffer's content.
877 struct intel_mipmap_tree
*mt
=
878 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
879 image
->offsets
[index
],
881 image
->strides
[index
],
883 MIPTREE_CREATE_NO_AUX
);
885 intel_miptree_release(&planar_mt
);
894 planar_mt
->plane
[i
- 1] = mt
;
897 planar_mt
->drm_modifier
= image
->modifier
;
903 create_ccs_buf_for_image(struct brw_context
*brw
,
905 struct intel_mipmap_tree
*mt
,
906 enum isl_aux_state initial_state
)
908 struct isl_surf temp_ccs_surf
;
910 /* CCS is only supported for very simple miptrees */
911 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
912 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
913 assert(mt
->surf
.samples
== 1);
914 assert(mt
->surf
.levels
== 1);
915 assert(mt
->surf
.logical_level0_px
.depth
== 1);
916 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
917 assert(mt
->first_level
== 0);
918 assert(mt
->last_level
== 0);
920 /* We shouldn't already have a CCS */
921 assert(!mt
->aux_buf
);
923 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
927 assert(image
->aux_offset
< image
->bo
->size
);
928 assert(temp_ccs_surf
.size_B
<= image
->bo
->size
- image
->aux_offset
);
930 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
931 if (mt
->aux_buf
== NULL
)
934 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
935 if (!mt
->aux_state
) {
941 /* On gen10+ we start using an extra space in the aux buffer to store the
942 * indirect clear color. However, if we imported an image from the window
943 * system with CCS, we don't have the extra space at the end of the aux
944 * buffer. So create a new bo here that will store that clear color.
946 if (brw
->isl_dev
.ss
.clear_color_state_size
> 0) {
947 mt
->aux_buf
->clear_color_bo
=
948 brw_bo_alloc_tiled(brw
->bufmgr
, "clear_color_bo",
949 brw
->isl_dev
.ss
.clear_color_state_size
,
950 BRW_MEMZONE_OTHER
, I915_TILING_NONE
, 0,
952 if (!mt
->aux_buf
->clear_color_bo
) {
959 mt
->aux_buf
->bo
= image
->bo
;
960 brw_bo_reference(image
->bo
);
962 mt
->aux_buf
->offset
= image
->aux_offset
;
963 mt
->aux_buf
->surf
= temp_ccs_surf
;
968 struct intel_mipmap_tree
*
969 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
970 __DRIimage
*image
, GLenum target
,
972 bool allow_internal_aux
)
974 uint32_t bo_tiling
, bo_swizzle
;
975 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
977 const struct isl_drm_modifier_info
*mod_info
=
978 isl_drm_modifier_get_info(image
->modifier
);
980 const enum isl_tiling tiling
=
981 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
983 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
984 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
986 if (image
->planar_format
)
987 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
989 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
990 /* The texture storage paths in core Mesa detect if the driver does not
991 * support the user-requested format, and then searches for a
992 * fallback format. The DRIimage code bypasses core Mesa, though. So we
993 * do the fallbacks here for important formats.
995 * We must support DRM_FOURCC_XBGR8888 textures because the Android
996 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
997 * the Chrome OS compositor consumes as dma_buf EGLImages.
999 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1002 if (!brw
->ctx
.TextureFormatSupported
[format
])
1005 enum intel_miptree_create_flags mt_create_flags
= 0;
1007 /* If this image comes in from a window system, we have different
1008 * requirements than if it comes in via an EGL import operation. Window
1009 * system images can use any form of auxiliary compression we wish because
1010 * they get "flushed" before being handed off to the window system and we
1011 * have the opportunity to do resolves. Non window-system images, on the
1012 * other hand, have no resolve point so we can't have aux without a
1015 if (!allow_internal_aux
)
1016 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1018 /* If we have a modifier which specifies aux, don't create one yet */
1019 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1020 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1022 /* Disable creation of the texture's aux buffers because the driver exposes
1023 * no EGL API to manage them. That is, there is no API for resolving the aux
1024 * buffer's content to the main buffer nor for invalidating the aux buffer's
1027 struct intel_mipmap_tree
*mt
=
1028 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1029 image
->offset
, image
->width
, image
->height
, 1,
1030 image
->pitch
, tiling
, mt_create_flags
);
1034 mt
->target
= target
;
1035 mt
->level
[0].level_x
= image
->tile_x
;
1036 mt
->level
[0].level_y
= image
->tile_y
;
1037 mt
->drm_modifier
= image
->modifier
;
1039 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1040 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1041 * trouble resolving back to destination image due to alignment issues.
1043 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1044 if (!devinfo
->has_surface_tile_offset
) {
1045 uint32_t draw_x
, draw_y
;
1046 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1048 if (draw_x
!= 0 || draw_y
!= 0) {
1049 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1050 intel_miptree_release(&mt
);
1055 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1056 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1058 mt
->aux_usage
= mod_info
->aux_usage
;
1059 /* If we are a window system buffer, then we can support fast-clears
1060 * even if the modifier doesn't support them by doing a partial resolve
1061 * as part of the flush operation.
1063 mt
->supports_fast_clear
=
1064 allow_internal_aux
|| mod_info
->supports_clear_color
;
1066 /* We don't know the actual state of the surface when we get it but we
1067 * can make a pretty good guess based on the modifier. What we do know
1068 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1069 * a worst case of compression.
1071 enum isl_aux_state initial_state
=
1072 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1074 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1075 intel_miptree_release(&mt
);
1080 /* Don't assume coherency for imported EGLimages. We don't know what
1081 * external clients are going to do with it. They may scan it out.
1083 image
->bo
->cache_coherent
= false;
1089 * For a singlesample renderbuffer, this simply wraps the given BO with a
1092 * For a multisample renderbuffer, this wraps the window system's
1093 * (singlesample) BO with a singlesample miptree attached to the
1094 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1095 * that will contain the actual rendering (which is lazily resolved to
1096 * irb->singlesample_mt).
1099 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1100 struct intel_renderbuffer
*irb
,
1101 struct intel_mipmap_tree
*singlesample_mt
,
1102 uint32_t width
, uint32_t height
,
1105 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1106 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1107 mesa_format format
= rb
->Format
;
1108 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1110 /* Only the front and back buffers, which are color buffers, are allocated
1111 * through the image loader.
1113 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1114 _mesa_get_format_base_format(format
) == GL_RGBA
);
1116 assert(singlesample_mt
);
1118 if (num_samples
== 1) {
1119 intel_miptree_release(&irb
->mt
);
1120 irb
->mt
= singlesample_mt
;
1122 assert(!irb
->singlesample_mt
);
1124 intel_miptree_release(&irb
->singlesample_mt
);
1125 irb
->singlesample_mt
= singlesample_mt
;
1128 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1129 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1130 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1135 if (!multisample_mt
)
1138 irb
->need_downsample
= false;
1139 intel_miptree_release(&irb
->mt
);
1140 irb
->mt
= multisample_mt
;
1146 intel_miptree_release(&irb
->mt
);
1150 struct intel_mipmap_tree
*
1151 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1155 uint32_t num_samples
)
1157 struct intel_mipmap_tree
*mt
;
1159 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1161 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1162 width
, height
, depth
, num_samples
,
1163 MIPTREE_CREATE_BUSY
);
1170 intel_miptree_release(&mt
);
1175 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1176 struct intel_mipmap_tree
*src
)
1181 intel_miptree_release(dst
);
1185 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1192 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1194 if (aux_buf
== NULL
)
1197 brw_bo_unreference(aux_buf
->bo
);
1198 brw_bo_unreference(aux_buf
->clear_color_bo
);
1204 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1209 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1210 if (--(*mt
)->refcount
<= 0) {
1213 DBG("%s deleting %p\n", __func__
, *mt
);
1215 brw_bo_unreference((*mt
)->bo
);
1216 intel_miptree_release(&(*mt
)->stencil_mt
);
1217 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1218 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1219 free_aux_state_map((*mt
)->aux_state
);
1221 intel_miptree_release(&(*mt
)->plane
[0]);
1222 intel_miptree_release(&(*mt
)->plane
[1]);
1224 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1225 free((*mt
)->level
[i
].slice
);
1235 intel_get_image_dims(struct gl_texture_image
*image
,
1236 int *width
, int *height
, int *depth
)
1238 switch (image
->TexObject
->Target
) {
1239 case GL_TEXTURE_1D_ARRAY
:
1240 /* For a 1D Array texture the OpenGL API will treat the image height as
1241 * the number of array slices. For Intel hardware, we treat the 1D array
1242 * as a 2D Array with a height of 1. So, here we want to swap image
1245 assert(image
->Depth
== 1);
1246 *width
= image
->Width
;
1248 *depth
= image
->Height
;
1250 case GL_TEXTURE_CUBE_MAP
:
1251 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1252 * though we really have 6 slices.
1254 assert(image
->Depth
== 1);
1255 *width
= image
->Width
;
1256 *height
= image
->Height
;
1260 *width
= image
->Width
;
1261 *height
= image
->Height
;
1262 *depth
= image
->Depth
;
1268 * Can the image be pulled into a unified mipmap tree? This mirrors
1269 * the completeness test in a lot of ways.
1271 * Not sure whether I want to pass gl_texture_image here.
1274 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1275 struct gl_texture_image
*image
)
1277 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1278 GLuint level
= intelImage
->base
.Base
.Level
;
1279 int width
, height
, depth
;
1281 /* glTexImage* choose the texture object based on the target passed in, and
1282 * objects can't change targets over their lifetimes, so this should be
1285 assert(image
->TexObject
->Target
== mt
->target
);
1287 mesa_format mt_format
= mt
->format
;
1288 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1289 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1290 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1291 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1292 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1293 mt_format
= mt
->etc_format
;
1295 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1296 _mesa_get_srgb_format_linear(mt_format
))
1299 intel_get_image_dims(image
, &width
, &height
, &depth
);
1301 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1304 if (level
>= mt
->surf
.levels
)
1307 const unsigned level_depth
=
1308 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1309 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1310 mt
->surf
.logical_level0_px
.array_len
;
1312 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1313 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1314 depth
== level_depth
&&
1315 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1319 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1320 GLuint level
, GLuint slice
,
1321 GLuint
*x
, GLuint
*y
)
1323 if (level
== 0 && slice
== 0) {
1324 *x
= mt
->level
[0].level_x
;
1325 *y
= mt
->level
[0].level_y
;
1329 uint32_t x_offset_sa
, y_offset_sa
;
1331 /* Miptree itself can have an offset only if it represents a single
1332 * slice in an imported buffer object.
1333 * See intel_miptree_create_for_dri_image().
1335 assert(mt
->level
[0].level_x
== 0);
1336 assert(mt
->level
[0].level_y
== 0);
1338 /* Given level is relative to level zero while the miptree may be
1339 * represent just a subset of all levels starting from 'first_level'.
1341 assert(level
>= mt
->first_level
);
1342 level
-= mt
->first_level
;
1344 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1345 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1346 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1347 &x_offset_sa
, &y_offset_sa
);
1355 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1356 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1357 * and tile_h is set to 1.
1360 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1361 uint32_t *tile_w
, uint32_t *tile_h
)
1372 case ISL_TILING_LINEAR
:
1377 unreachable("not reached");
1383 * This function computes masks that may be used to select the bits of the X
1384 * and Y coordinates that indicate the offset within a tile. If the BO is
1385 * untiled, the masks are set to 0.
1388 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1389 uint32_t *mask_x
, uint32_t *mask_y
)
1391 uint32_t tile_w_bytes
, tile_h
;
1393 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1395 *mask_x
= tile_w_bytes
/ cpp
- 1;
1396 *mask_y
= tile_h
- 1;
1400 * Compute the offset (in bytes) from the start of the BO to the given x
1401 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1402 * multiples of the tile size.
1405 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1406 uint32_t x
, uint32_t y
)
1409 uint32_t pitch
= mt
->surf
.row_pitch_B
;
1411 switch (mt
->surf
.tiling
) {
1413 unreachable("not reached");
1414 case ISL_TILING_LINEAR
:
1415 return y
* pitch
+ x
* cpp
;
1417 assert((x
% (512 / cpp
)) == 0);
1418 assert((y
% 8) == 0);
1419 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1421 assert((x
% (128 / cpp
)) == 0);
1422 assert((y
% 32) == 0);
1423 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1428 * Rendering with tiled buffers requires that the base address of the buffer
1429 * be aligned to a page boundary. For renderbuffers, and sometimes with
1430 * textures, we may want the surface to point at a texture image level that
1431 * isn't at a page boundary.
1433 * This function returns an appropriately-aligned base offset
1434 * according to the tiling restrictions, plus any required x/y offset
1438 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1439 GLuint level
, GLuint slice
,
1444 uint32_t mask_x
, mask_y
;
1446 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1447 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1449 *tile_x
= x
& mask_x
;
1450 *tile_y
= y
& mask_y
;
1452 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1456 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1457 struct intel_mipmap_tree
*src_mt
,
1458 unsigned src_level
, unsigned src_layer
,
1459 struct intel_mipmap_tree
*dst_mt
,
1460 unsigned dst_level
, unsigned dst_layer
,
1461 unsigned width
, unsigned height
)
1464 ptrdiff_t src_stride
, dst_stride
;
1465 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1467 intel_miptree_map(brw
, src_mt
,
1468 src_level
, src_layer
,
1471 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1474 intel_miptree_map(brw
, dst_mt
,
1475 dst_level
, dst_layer
,
1478 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1482 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1483 _mesa_get_format_name(src_mt
->format
),
1484 src_mt
, src
, src_stride
,
1485 _mesa_get_format_name(dst_mt
->format
),
1486 dst_mt
, dst
, dst_stride
,
1489 int row_size
= cpp
* width
;
1490 if (src_stride
== row_size
&&
1491 dst_stride
== row_size
) {
1492 memcpy(dst
, src
, row_size
* height
);
1494 for (int i
= 0; i
< height
; i
++) {
1495 memcpy(dst
, src
, row_size
);
1501 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1502 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1504 /* Don't forget to copy the stencil data over, too. We could have skipped
1505 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1506 * shuffling the two data sources in/out of temporary storage instead of
1507 * the direct mapping we get this way.
1509 if (dst_mt
->stencil_mt
) {
1510 assert(src_mt
->stencil_mt
);
1511 intel_miptree_copy_slice_sw(brw
,
1512 src_mt
->stencil_mt
, src_level
, src_layer
,
1513 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1519 intel_miptree_copy_slice(struct brw_context
*brw
,
1520 struct intel_mipmap_tree
*src_mt
,
1521 unsigned src_level
, unsigned src_layer
,
1522 struct intel_mipmap_tree
*dst_mt
,
1523 unsigned dst_level
, unsigned dst_layer
)
1526 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1527 mesa_format format
= src_mt
->format
;
1528 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1529 src_level
- src_mt
->first_level
);
1530 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1531 src_level
- src_mt
->first_level
);
1533 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1534 src_level
- src_mt
->first_level
));
1536 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1537 _mesa_get_srgb_format_linear(dst_mt
->format
));
1539 DBG("validate blit mt %s %p %d,%d -> mt %s %p %d,%d (%dx%d)\n",
1540 _mesa_get_format_name(src_mt
->format
),
1541 src_mt
, src_level
, src_layer
,
1542 _mesa_get_format_name(dst_mt
->format
),
1543 dst_mt
, dst_level
, dst_layer
,
1546 if (devinfo
->gen
>= 6) {
1547 /* On gen6 and above, we just use blorp. It's faster than the blitter
1548 * and can handle everything without software fallbacks.
1550 brw_blorp_copy_miptrees(brw
,
1551 src_mt
, src_level
, src_layer
,
1552 dst_mt
, dst_level
, dst_layer
,
1553 0, 0, 0, 0, width
, height
);
1555 if (src_mt
->stencil_mt
) {
1556 assert(dst_mt
->stencil_mt
);
1557 brw_blorp_copy_miptrees(brw
,
1558 src_mt
->stencil_mt
, src_level
, src_layer
,
1559 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1560 0, 0, 0, 0, width
, height
);
1565 if (dst_mt
->compressed
) {
1567 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1568 height
= ALIGN_NPOT(height
, j
) / j
;
1569 width
= ALIGN_NPOT(width
, i
) / i
;
1572 /* Gen4-5 doesn't support separate stencil */
1573 assert(!src_mt
->stencil_mt
);
1575 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1576 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1578 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1581 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1582 _mesa_get_format_name(src_mt
->format
),
1583 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch_B
,
1584 _mesa_get_format_name(dst_mt
->format
),
1585 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch_B
,
1588 if (!intel_miptree_blit(brw
,
1589 src_mt
, src_level
, src_layer
, 0, 0, false,
1590 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1591 width
, height
, COLOR_LOGICOP_COPY
)) {
1592 perf_debug("miptree validate blit for %s failed\n",
1593 _mesa_get_format_name(format
));
1595 intel_miptree_copy_slice_sw(brw
,
1596 src_mt
, src_level
, src_layer
,
1597 dst_mt
, dst_level
, dst_layer
,
1603 * Copies the image's current data to the given miptree, and associates that
1604 * miptree with the image.
1607 intel_miptree_copy_teximage(struct brw_context
*brw
,
1608 struct intel_texture_image
*intelImage
,
1609 struct intel_mipmap_tree
*dst_mt
)
1611 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1612 struct intel_texture_object
*intel_obj
=
1613 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1614 int level
= intelImage
->base
.Base
.Level
;
1615 const unsigned face
= intelImage
->base
.Base
.Face
;
1616 unsigned start_layer
, end_layer
;
1618 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1620 assert(intelImage
->base
.Base
.Height
);
1622 end_layer
= intelImage
->base
.Base
.Height
- 1;
1623 } else if (face
> 0) {
1627 assert(intelImage
->base
.Base
.Depth
);
1629 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1632 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1633 intel_miptree_copy_slice(brw
,
1638 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1639 intel_obj
->needs_validate
= true;
1642 static struct intel_miptree_aux_buffer
*
1643 intel_alloc_aux_buffer(struct brw_context
*brw
,
1644 const struct isl_surf
*aux_surf
,
1646 uint8_t memset_value
)
1648 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1652 uint64_t size
= aux_surf
->size_B
;
1654 const bool has_indirect_clear
= brw
->isl_dev
.ss
.clear_color_state_size
> 0;
1655 if (has_indirect_clear
) {
1656 /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
1657 * will set a pointer to a dword somewhere that contains the color. So,
1658 * allocate the space for the clear color value here on the aux buffer.
1660 buf
->clear_color_offset
= size
;
1661 size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1664 /* If the buffer needs to be initialised (requiring the buffer to be
1665 * immediately mapped to cpu space for writing), do not use the gpu access
1666 * flag which can cause an unnecessary delay if the backing pages happened
1667 * to be just used by the GPU.
1669 const bool alloc_zeroed
= wants_memset
&& memset_value
== 0;
1670 const bool needs_memset
=
1671 !alloc_zeroed
&& (wants_memset
|| has_indirect_clear
);
1672 const uint32_t alloc_flags
=
1673 alloc_zeroed
? BO_ALLOC_ZEROED
: (needs_memset
? 0 : BO_ALLOC_BUSY
);
1675 /* ISL has stricter set of alignment rules then the drm allocator.
1676 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1677 * trying to recalculate based on different format block sizes.
1679 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "aux-miptree", size
,
1680 BRW_MEMZONE_OTHER
, I915_TILING_Y
,
1681 aux_surf
->row_pitch_B
, alloc_flags
);
1687 /* Initialize the bo to the desired value */
1689 assert(!(alloc_flags
& BO_ALLOC_BUSY
));
1691 void *map
= brw_bo_map(brw
, buf
->bo
, MAP_WRITE
| MAP_RAW
);
1693 intel_miptree_aux_buffer_free(buf
);
1697 /* Memset the aux_surf portion of the BO. */
1699 memset(map
, memset_value
, aux_surf
->size_B
);
1701 /* Zero the indirect clear color to match ::fast_clear_color. */
1702 if (has_indirect_clear
) {
1703 memset((char *)map
+ buf
->clear_color_offset
, 0,
1704 brw
->isl_dev
.ss
.clear_color_state_size
);
1707 brw_bo_unmap(buf
->bo
);
1710 if (has_indirect_clear
) {
1711 buf
->clear_color_bo
= buf
->bo
;
1712 brw_bo_reference(buf
->clear_color_bo
);
1715 buf
->surf
= *aux_surf
;
1722 * Helper for intel_miptree_alloc_aux() that sets
1723 * \c mt->level[level].has_hiz. Return true if and only if
1724 * \c has_hiz was set.
1727 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1728 struct intel_mipmap_tree
*mt
,
1731 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1733 assert(mt
->aux_buf
);
1734 assert(mt
->surf
.size_B
> 0);
1736 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1737 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1738 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1740 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1741 * and the height is 4 aligned. This allows our HiZ support
1742 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1743 * we can grow the width & height to allow the HiZ op to
1744 * force the proper size alignments.
1746 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1747 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1752 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1753 mt
->level
[level
].has_hiz
= true;
1759 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1761 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1762 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1763 * compress clear color so we wait until an actual fast-clear to allocate it.
1766 intel_miptree_alloc_aux(struct brw_context
*brw
,
1767 struct intel_mipmap_tree
*mt
)
1769 assert(mt
->aux_buf
== NULL
);
1771 /* Get the aux buf allocation parameters for this miptree. */
1772 enum isl_aux_state initial_state
;
1773 uint8_t memset_value
;
1774 struct isl_surf aux_surf
;
1775 MAYBE_UNUSED
bool aux_surf_ok
= false;
1777 switch (mt
->aux_usage
) {
1778 case ISL_AUX_USAGE_NONE
:
1779 aux_surf
.size_B
= 0;
1782 case ISL_AUX_USAGE_HIZ
:
1783 initial_state
= ISL_AUX_STATE_AUX_INVALID
;
1785 aux_surf_ok
= isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1787 case ISL_AUX_USAGE_MCS
:
1788 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1790 * When MCS buffer is enabled and bound to MSRT, it is required that
1791 * it is cleared prior to any rendering.
1793 * Since we don't use the MCS buffer for any purpose other than
1794 * rendering, it makes sense to just clear it immediately upon
1797 * Note: the clear value for MCS buffers is all 1's, so we memset to
1800 initial_state
= ISL_AUX_STATE_CLEAR
;
1801 memset_value
= 0xFF;
1802 aux_surf_ok
= isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
);
1804 case ISL_AUX_USAGE_CCS_D
:
1805 case ISL_AUX_USAGE_CCS_E
:
1806 /* When CCS_E is used, we need to ensure that the CCS starts off in a
1807 * valid state. From the Sky Lake PRM, "MCS Buffer for Render
1810 * "If Software wants to enable Color Compression without Fast
1811 * clear, Software needs to initialize MCS with zeros."
1813 * A CCS value of 0 indicates that the corresponding block is in the
1814 * pass-through state which is what we want.
1816 * For CCS_D, do the same thing. On gen9+, this avoids having any
1817 * undefined bits in the aux buffer.
1819 initial_state
= ISL_AUX_STATE_PASS_THROUGH
;
1822 isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &aux_surf
, 0);
1826 /* We should have a valid aux_surf. */
1827 assert(aux_surf_ok
);
1829 /* No work is needed for a zero-sized auxiliary buffer. */
1830 if (aux_surf
.size_B
== 0)
1833 /* Create the aux_state for the auxiliary buffer. */
1834 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
1835 if (mt
->aux_state
== NULL
)
1838 /* Allocate the auxiliary buffer. */
1839 const bool needs_memset
= initial_state
!= ISL_AUX_STATE_AUX_INVALID
;
1840 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, &aux_surf
, needs_memset
,
1842 if (mt
->aux_buf
== NULL
) {
1843 free_aux_state_map(mt
->aux_state
);
1844 mt
->aux_state
= NULL
;
1848 /* Perform aux_usage-specific initialization. */
1849 if (mt
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
1850 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1851 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1859 * Can the miptree sample using the hiz buffer?
1862 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1863 struct intel_mipmap_tree
*mt
)
1865 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1867 if (!devinfo
->has_sample_with_hiz
) {
1875 /* It seems the hardware won't fallback to the depth buffer if some of the
1876 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1877 * of the texture to be HiZ enabled.
1879 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1880 if (!intel_miptree_level_has_hiz(mt
, level
))
1884 /* If compressed multisampling is enabled, then we use it for the auxiliary
1887 * From the BDW PRM (Volume 2d: Command Reference: Structures
1888 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1890 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1891 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1893 * There is no such blurb for 1D textures, but there is sufficient evidence
1894 * that this is broken on SKL+.
1896 return (mt
->surf
.samples
== 1 &&
1897 mt
->target
!= GL_TEXTURE_3D
&&
1898 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1902 * Does the miptree slice have hiz enabled?
1905 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1907 intel_miptree_check_level_layer(mt
, level
, 0);
1908 return mt
->level
[level
].has_hiz
;
1911 static inline uint32_t
1912 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1913 uint32_t start_level
, uint32_t num_levels
)
1915 assert(start_level
>= mt
->first_level
);
1916 assert(start_level
<= mt
->last_level
);
1918 if (num_levels
== INTEL_REMAINING_LAYERS
)
1919 num_levels
= mt
->last_level
- start_level
+ 1;
1920 /* Check for overflow */
1921 assert(start_level
+ num_levels
>= start_level
);
1922 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1927 static inline uint32_t
1928 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1929 uint32_t start_layer
, uint32_t num_layers
)
1931 assert(level
<= mt
->last_level
);
1933 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1934 assert(start_layer
< total_num_layers
);
1935 if (num_layers
== INTEL_REMAINING_LAYERS
)
1936 num_layers
= total_num_layers
- start_layer
;
1937 /* Check for overflow */
1938 assert(start_layer
+ num_layers
>= start_layer
);
1939 assert(start_layer
+ num_layers
<= total_num_layers
);
1945 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1946 unsigned start_level
, unsigned num_levels
,
1947 unsigned start_layer
, unsigned num_layers
)
1949 assert(_mesa_is_format_color_format(mt
->format
));
1954 /* Clamp the level range to fit the miptree */
1955 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1957 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1958 const uint32_t level
= start_level
+ l
;
1959 const uint32_t level_layers
=
1960 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1961 for (unsigned a
= 0; a
< level_layers
; a
++) {
1962 enum isl_aux_state aux_state
=
1963 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1964 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1965 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1974 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1975 const struct intel_mipmap_tree
*mt
,
1976 unsigned level
, unsigned layer
)
1981 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1982 assert(brw
->screen
->devinfo
.gen
>= 8 ||
1983 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1985 /* Compression of arrayed msaa surfaces is supported. */
1986 if (mt
->surf
.samples
> 1)
1989 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1990 assert(brw
->screen
->devinfo
.gen
>= 8 ||
1992 mt
->surf
.logical_level0_px
.depth
== 1 &&
1993 mt
->surf
.logical_level0_px
.array_len
== 1));
1999 static enum isl_aux_op
2000 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2001 enum isl_aux_usage aux_usage
,
2002 bool fast_clear_supported
)
2004 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2006 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2008 assert(ccs_supported
== fast_clear_supported
);
2010 switch (aux_state
) {
2011 case ISL_AUX_STATE_CLEAR
:
2012 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2014 return ISL_AUX_OP_FULL_RESOLVE
;
2016 return ISL_AUX_OP_NONE
;
2018 case ISL_AUX_STATE_PASS_THROUGH
:
2019 return ISL_AUX_OP_NONE
;
2021 case ISL_AUX_STATE_RESOLVED
:
2022 case ISL_AUX_STATE_AUX_INVALID
:
2023 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2024 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2028 unreachable("Invalid aux state for CCS_D");
2031 static enum isl_aux_op
2032 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2033 enum isl_aux_usage aux_usage
,
2034 bool fast_clear_supported
)
2036 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2037 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2038 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2039 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2041 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2042 assert(fast_clear_supported
);
2044 switch (aux_state
) {
2045 case ISL_AUX_STATE_CLEAR
:
2046 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2047 if (fast_clear_supported
)
2048 return ISL_AUX_OP_NONE
;
2049 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2050 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2052 return ISL_AUX_OP_FULL_RESOLVE
;
2054 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2055 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2056 return ISL_AUX_OP_FULL_RESOLVE
;
2057 else if (!fast_clear_supported
)
2058 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2060 return ISL_AUX_OP_NONE
;
2062 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2063 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2064 return ISL_AUX_OP_FULL_RESOLVE
;
2066 return ISL_AUX_OP_NONE
;
2068 case ISL_AUX_STATE_PASS_THROUGH
:
2069 return ISL_AUX_OP_NONE
;
2071 case ISL_AUX_STATE_RESOLVED
:
2072 case ISL_AUX_STATE_AUX_INVALID
:
2076 unreachable("Invalid aux state for CCS_E");
2080 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2081 struct intel_mipmap_tree
*mt
,
2082 uint32_t level
, uint32_t layer
,
2083 enum isl_aux_usage aux_usage
,
2084 bool fast_clear_supported
)
2086 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2088 enum isl_aux_op resolve_op
;
2089 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2090 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2091 fast_clear_supported
);
2093 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2094 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2095 fast_clear_supported
);
2098 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2099 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2100 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2102 switch (resolve_op
) {
2103 case ISL_AUX_OP_FULL_RESOLVE
:
2104 /* The CCS full resolve operation destroys the CCS and sets it to the
2105 * pass-through state. (You can also think of this as being both a
2106 * resolve and an ambiguate in one operation.)
2108 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2109 ISL_AUX_STATE_PASS_THROUGH
);
2112 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2113 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2114 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2118 unreachable("Invalid resolve op");
2124 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2125 struct intel_mipmap_tree
*mt
,
2126 uint32_t level
, uint32_t layer
,
2127 enum isl_aux_usage aux_usage
)
2129 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2130 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2131 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2133 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2135 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2136 switch (aux_state
) {
2137 case ISL_AUX_STATE_CLEAR
:
2138 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2139 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2140 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2142 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2143 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2144 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2145 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2146 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2147 ISL_AUX_STATE_PARTIAL_CLEAR
);
2151 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2152 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2153 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2154 break; /* Nothing to do */
2156 case ISL_AUX_STATE_PASS_THROUGH
:
2157 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2158 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2159 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2165 case ISL_AUX_STATE_RESOLVED
:
2166 case ISL_AUX_STATE_AUX_INVALID
:
2167 unreachable("Invalid aux state for CCS_E");
2170 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2171 /* CCS_D is a bit simpler */
2172 switch (aux_state
) {
2173 case ISL_AUX_STATE_CLEAR
:
2174 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2175 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2176 ISL_AUX_STATE_PARTIAL_CLEAR
);
2179 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2180 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2181 break; /* Nothing to do */
2183 case ISL_AUX_STATE_PASS_THROUGH
:
2187 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2188 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2189 case ISL_AUX_STATE_RESOLVED
:
2190 case ISL_AUX_STATE_AUX_INVALID
:
2191 unreachable("Invalid aux state for CCS_D");
2197 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2198 struct intel_mipmap_tree
*mt
,
2200 enum isl_aux_usage aux_usage
,
2201 bool fast_clear_supported
)
2203 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2205 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2206 case ISL_AUX_STATE_CLEAR
:
2207 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2208 if (!fast_clear_supported
) {
2209 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2210 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2211 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2215 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2216 break; /* Nothing to do */
2218 case ISL_AUX_STATE_RESOLVED
:
2219 case ISL_AUX_STATE_PASS_THROUGH
:
2220 case ISL_AUX_STATE_AUX_INVALID
:
2221 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2222 unreachable("Invalid aux state for MCS");
2227 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2228 struct intel_mipmap_tree
*mt
,
2230 enum isl_aux_usage aux_usage
)
2232 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2234 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2235 case ISL_AUX_STATE_CLEAR
:
2236 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2237 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2240 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2241 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2242 break; /* Nothing to do */
2244 case ISL_AUX_STATE_RESOLVED
:
2245 case ISL_AUX_STATE_PASS_THROUGH
:
2246 case ISL_AUX_STATE_AUX_INVALID
:
2247 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2248 unreachable("Invalid aux state for MCS");
2253 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2254 struct intel_mipmap_tree
*mt
,
2255 uint32_t level
, uint32_t layer
,
2256 enum isl_aux_usage aux_usage
,
2257 bool fast_clear_supported
)
2259 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2261 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2262 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2263 case ISL_AUX_STATE_CLEAR
:
2264 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2265 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2266 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2269 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2270 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2271 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2274 case ISL_AUX_STATE_PASS_THROUGH
:
2275 case ISL_AUX_STATE_RESOLVED
:
2278 case ISL_AUX_STATE_AUX_INVALID
:
2279 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2280 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2283 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2284 unreachable("Invalid HiZ state");
2287 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2288 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2291 case ISL_AUX_OP_FULL_RESOLVE
:
2292 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2293 ISL_AUX_STATE_RESOLVED
);
2296 case ISL_AUX_OP_AMBIGUATE
:
2297 /* The HiZ resolve operation is actually an ambiguate */
2298 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2299 ISL_AUX_STATE_PASS_THROUGH
);
2303 unreachable("Invalid HiZ op");
2309 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2310 struct intel_mipmap_tree
*mt
,
2311 uint32_t level
, uint32_t layer
,
2312 enum isl_aux_usage aux_usage
)
2314 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2316 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2317 case ISL_AUX_STATE_CLEAR
:
2318 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2319 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2320 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2323 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2324 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2325 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2326 break; /* Nothing to do */
2328 case ISL_AUX_STATE_RESOLVED
:
2329 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2330 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2331 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2333 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2334 ISL_AUX_STATE_AUX_INVALID
);
2338 case ISL_AUX_STATE_PASS_THROUGH
:
2339 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2340 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2341 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2345 case ISL_AUX_STATE_AUX_INVALID
:
2346 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2349 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2350 unreachable("Invalid HiZ state");
2355 intel_miptree_prepare_access(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 uint32_t start_level
, uint32_t num_levels
,
2358 uint32_t start_layer
, uint32_t num_layers
,
2359 enum isl_aux_usage aux_usage
,
2360 bool fast_clear_supported
)
2362 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2364 switch (mt
->aux_usage
) {
2365 case ISL_AUX_USAGE_NONE
:
2369 case ISL_AUX_USAGE_MCS
:
2370 assert(mt
->aux_buf
);
2371 assert(start_level
== 0 && num_levels
== 1);
2372 const uint32_t level_layers
=
2373 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2374 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2375 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2376 aux_usage
, fast_clear_supported
);
2380 case ISL_AUX_USAGE_CCS_D
:
2381 case ISL_AUX_USAGE_CCS_E
:
2385 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2386 const uint32_t level
= start_level
+ l
;
2387 const uint32_t level_layers
=
2388 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2389 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2390 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2392 aux_usage
, fast_clear_supported
);
2397 case ISL_AUX_USAGE_HIZ
:
2398 assert(mt
->aux_buf
);
2399 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2400 const uint32_t level
= start_level
+ l
;
2401 if (!intel_miptree_level_has_hiz(mt
, level
))
2404 const uint32_t level_layers
=
2405 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2406 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2407 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2408 aux_usage
, fast_clear_supported
);
2414 unreachable("Invalid aux usage");
2419 intel_miptree_finish_write(struct brw_context
*brw
,
2420 struct intel_mipmap_tree
*mt
, uint32_t level
,
2421 uint32_t start_layer
, uint32_t num_layers
,
2422 enum isl_aux_usage aux_usage
)
2424 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2425 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2427 switch (mt
->aux_usage
) {
2428 case ISL_AUX_USAGE_NONE
:
2429 if (mt
->format
== MESA_FORMAT_S_UINT8
&& devinfo
->gen
<= 7)
2430 mt
->r8stencil_needs_update
= true;
2433 case ISL_AUX_USAGE_MCS
:
2434 assert(mt
->aux_buf
);
2435 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2436 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2441 case ISL_AUX_USAGE_CCS_D
:
2442 case ISL_AUX_USAGE_CCS_E
:
2446 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2447 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2452 case ISL_AUX_USAGE_HIZ
:
2453 if (!intel_miptree_level_has_hiz(mt
, level
))
2456 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2457 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2463 unreachable("Invavlid aux usage");
2468 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2469 uint32_t level
, uint32_t layer
)
2471 intel_miptree_check_level_layer(mt
, level
, layer
);
2473 if (_mesa_is_format_color_format(mt
->format
)) {
2474 assert(mt
->aux_buf
!= NULL
);
2475 assert(mt
->surf
.samples
== 1 ||
2476 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2477 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2478 unreachable("Cannot get aux state for stencil");
2480 assert(intel_miptree_level_has_hiz(mt
, level
));
2483 return mt
->aux_state
[level
][layer
];
2487 intel_miptree_set_aux_state(struct brw_context
*brw
,
2488 struct intel_mipmap_tree
*mt
, uint32_t level
,
2489 uint32_t start_layer
, uint32_t num_layers
,
2490 enum isl_aux_state aux_state
)
2492 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2494 if (_mesa_is_format_color_format(mt
->format
)) {
2495 assert(mt
->aux_buf
!= NULL
);
2496 assert(mt
->surf
.samples
== 1 ||
2497 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2498 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2499 unreachable("Cannot get aux state for stencil");
2501 assert(intel_miptree_level_has_hiz(mt
, level
));
2504 for (unsigned a
= 0; a
< num_layers
; a
++) {
2505 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2506 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2507 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2512 /* On Gen9 color buffers may be compressed by the hardware (lossless
2513 * compression). There are, however, format restrictions and care needs to be
2514 * taken that the sampler engine is capable for re-interpreting a buffer with
2515 * format different the buffer was originally written with.
2517 * For example, SRGB formats are not compressible and the sampler engine isn't
2518 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2519 * color buffer needs to be resolved so that the sampling surface can be
2520 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2524 can_texture_with_ccs(struct brw_context
*brw
,
2525 struct intel_mipmap_tree
*mt
,
2526 enum isl_format view_format
)
2528 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2531 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2533 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2534 isl_format_get_layout(view_format
)->name
,
2535 _mesa_get_format_name(mt
->format
));
2543 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2544 struct intel_mipmap_tree
*mt
,
2545 enum isl_format view_format
,
2546 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
2548 assert(brw
->screen
->devinfo
.gen
== 9 || astc5x5_wa_bits
== 0);
2550 /* On gen9, ASTC 5x5 textures cannot live in the sampler cache along side
2551 * CCS or HiZ compressed textures. See gen9_apply_astc5x5_wa_flush() for
2554 if ((astc5x5_wa_bits
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
2555 mt
->aux_usage
!= ISL_AUX_USAGE_MCS
)
2556 return ISL_AUX_USAGE_NONE
;
2558 switch (mt
->aux_usage
) {
2559 case ISL_AUX_USAGE_HIZ
:
2560 if (intel_miptree_sample_with_hiz(brw
, mt
))
2561 return ISL_AUX_USAGE_HIZ
;
2564 case ISL_AUX_USAGE_MCS
:
2565 return ISL_AUX_USAGE_MCS
;
2567 case ISL_AUX_USAGE_CCS_D
:
2568 case ISL_AUX_USAGE_CCS_E
:
2570 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2571 return ISL_AUX_USAGE_NONE
;
2574 /* If we don't have any unresolved color, report an aux usage of
2575 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2576 * aux surface and we can save some bandwidth.
2578 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2579 0, INTEL_REMAINING_LAYERS
))
2580 return ISL_AUX_USAGE_NONE
;
2582 if (can_texture_with_ccs(brw
, mt
, view_format
))
2583 return ISL_AUX_USAGE_CCS_E
;
2590 return ISL_AUX_USAGE_NONE
;
2594 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2596 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2597 * values so sRGB curve application was a no-op for all fast-clearable
2600 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2601 * values, the hardware interprets the floats, not as what would be
2602 * returned from the sampler (or written by the shader), but as being
2603 * between format conversion and sRGB curve application. This means that
2604 * we can switch between sRGB and UNORM without having to whack the clear
2607 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2611 intel_miptree_prepare_texture(struct brw_context
*brw
,
2612 struct intel_mipmap_tree
*mt
,
2613 enum isl_format view_format
,
2614 uint32_t start_level
, uint32_t num_levels
,
2615 uint32_t start_layer
, uint32_t num_layers
,
2616 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
)
2618 enum isl_aux_usage aux_usage
=
2619 intel_miptree_texture_aux_usage(brw
, mt
, view_format
, astc5x5_wa_bits
);
2621 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2623 /* Clear color is specified as ints or floats and the conversion is done by
2624 * the sampler. If we have a texture view, we would have to perform the
2625 * clear color conversion manually. Just disable clear color.
2627 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2628 clear_supported
= false;
2630 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2631 start_layer
, num_layers
,
2632 aux_usage
, clear_supported
);
2636 intel_miptree_prepare_image(struct brw_context
*brw
,
2637 struct intel_mipmap_tree
*mt
)
2639 /* The data port doesn't understand any compression */
2640 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2641 0, INTEL_REMAINING_LAYERS
,
2642 ISL_AUX_USAGE_NONE
, false);
2646 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2647 struct intel_mipmap_tree
*mt
,
2648 enum isl_format render_format
,
2650 bool draw_aux_disabled
)
2652 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2654 if (draw_aux_disabled
)
2655 return ISL_AUX_USAGE_NONE
;
2657 switch (mt
->aux_usage
) {
2658 case ISL_AUX_USAGE_MCS
:
2659 assert(mt
->aux_buf
);
2660 return ISL_AUX_USAGE_MCS
;
2662 case ISL_AUX_USAGE_CCS_D
:
2663 case ISL_AUX_USAGE_CCS_E
:
2665 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2666 return ISL_AUX_USAGE_NONE
;
2669 /* gen9+ hardware technically supports non-0/1 clear colors with sRGB
2670 * formats. However, there are issues with blending where it doesn't
2671 * properly apply the sRGB curve to the clear color when blending.
2673 if (devinfo
->gen
>= 9 && blend_enabled
&&
2674 isl_format_is_srgb(render_format
) &&
2675 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2676 return ISL_AUX_USAGE_NONE
;
2678 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2679 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2681 return ISL_AUX_USAGE_CCS_E
;
2683 /* Otherwise, we have to fall back to CCS_D */
2684 return ISL_AUX_USAGE_CCS_D
;
2687 return ISL_AUX_USAGE_NONE
;
2692 intel_miptree_prepare_render(struct brw_context
*brw
,
2693 struct intel_mipmap_tree
*mt
, uint32_t level
,
2694 uint32_t start_layer
, uint32_t layer_count
,
2695 enum isl_aux_usage aux_usage
)
2697 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2698 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2702 intel_miptree_finish_render(struct brw_context
*brw
,
2703 struct intel_mipmap_tree
*mt
, uint32_t level
,
2704 uint32_t start_layer
, uint32_t layer_count
,
2705 enum isl_aux_usage aux_usage
)
2707 assert(_mesa_is_format_color_format(mt
->format
));
2709 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2714 intel_miptree_prepare_depth(struct brw_context
*brw
,
2715 struct intel_mipmap_tree
*mt
, uint32_t level
,
2716 uint32_t start_layer
, uint32_t layer_count
)
2718 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2719 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2723 intel_miptree_finish_depth(struct brw_context
*brw
,
2724 struct intel_mipmap_tree
*mt
, uint32_t level
,
2725 uint32_t start_layer
, uint32_t layer_count
,
2728 if (depth_written
) {
2729 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2735 intel_miptree_prepare_external(struct brw_context
*brw
,
2736 struct intel_mipmap_tree
*mt
)
2738 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2739 bool supports_fast_clear
= false;
2741 const struct isl_drm_modifier_info
*mod_info
=
2742 isl_drm_modifier_get_info(mt
->drm_modifier
);
2744 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2745 /* CCS_E is the only supported aux for external images and it's only
2746 * supported on very simple images.
2748 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2749 assert(_mesa_is_format_color_format(mt
->format
));
2750 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2751 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2752 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2753 assert(mt
->surf
.samples
== 1);
2754 assert(mt
->aux_buf
!= NULL
);
2756 aux_usage
= mod_info
->aux_usage
;
2757 supports_fast_clear
= mod_info
->supports_clear_color
;
2760 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2761 0, INTEL_REMAINING_LAYERS
,
2762 aux_usage
, supports_fast_clear
);
2766 intel_miptree_finish_external(struct brw_context
*brw
,
2767 struct intel_mipmap_tree
*mt
)
2772 /* We don't know the actual aux state of the aux surface. The previous
2773 * owner could have given it to us in a number of different states.
2774 * Because we don't know the aux state, we reset the aux state to the
2775 * least common denominator of possible valid states.
2777 enum isl_aux_state default_aux_state
=
2778 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2779 assert(mt
->last_level
== mt
->first_level
);
2780 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2785 * Make it possible to share the BO backing the given miptree with another
2786 * process or another miptree.
2788 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2789 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2790 * ensure that no MCS buffer gets allocated in the future.
2792 * HiZ is similarly unsafe with shared buffers.
2795 intel_miptree_make_shareable(struct brw_context
*brw
,
2796 struct intel_mipmap_tree
*mt
)
2798 /* MCS buffers are also used for multisample buffers, but we can't resolve
2799 * away a multisample MCS buffer because it's an integral part of how the
2800 * pixel data is stored. Fortunately this code path should never be
2801 * reached for multisample buffers.
2803 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2804 mt
->surf
.samples
== 1);
2806 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2807 0, INTEL_REMAINING_LAYERS
,
2808 ISL_AUX_USAGE_NONE
, false);
2811 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2814 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2815 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2816 mt
->level
[l
].has_hiz
= false;
2819 free(mt
->aux_state
);
2820 mt
->aux_state
= NULL
;
2821 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2824 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2825 mt
->supports_fast_clear
= false;
2830 * \brief Get pointer offset into stencil buffer.
2832 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2833 * must decode the tile's layout in software.
2836 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2838 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2840 * Even though the returned offset is always positive, the return type is
2842 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2843 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2846 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2848 uint32_t tile_size
= 4096;
2849 uint32_t tile_width
= 64;
2850 uint32_t tile_height
= 64;
2851 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2853 uint32_t tile_x
= x
/ tile_width
;
2854 uint32_t tile_y
= y
/ tile_height
;
2856 /* The byte's address relative to the tile's base addres. */
2857 uint32_t byte_x
= x
% tile_width
;
2858 uint32_t byte_y
= y
% tile_height
;
2860 uintptr_t u
= tile_y
* row_size
2861 + tile_x
* tile_size
2862 + 512 * (byte_x
/ 8)
2864 + 32 * ((byte_y
/ 4) % 2)
2865 + 16 * ((byte_x
/ 4) % 2)
2866 + 8 * ((byte_y
/ 2) % 2)
2867 + 4 * ((byte_x
/ 2) % 2)
2872 /* adjust for bit6 swizzling */
2873 if (((byte_x
/ 8) % 2) == 1) {
2874 if (((byte_y
/ 8) % 2) == 0) {
2886 intel_miptree_updownsample(struct brw_context
*brw
,
2887 struct intel_mipmap_tree
*src
,
2888 struct intel_mipmap_tree
*dst
)
2890 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2891 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2892 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2893 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2895 brw_blorp_blit_miptrees(brw
,
2896 src
, 0 /* level */, 0 /* layer */,
2897 src
->format
, SWIZZLE_XYZW
,
2898 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2901 GL_NEAREST
, false, false /*mirror x, y*/,
2904 if (src
->stencil_mt
) {
2905 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2906 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2907 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2908 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2910 brw_blorp_blit_miptrees(brw
,
2911 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2912 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2913 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2914 dst
->stencil_mt
->format
,
2917 GL_NEAREST
, false, false /*mirror x, y*/,
2918 false, false /* decode/encode srgb */);
2923 intel_update_r8stencil(struct brw_context
*brw
,
2924 struct intel_mipmap_tree
*mt
)
2926 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2928 assert(devinfo
->gen
>= 7);
2929 struct intel_mipmap_tree
*src
=
2930 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2931 if (!src
|| devinfo
->gen
>= 8)
2934 assert(src
->surf
.size_B
> 0);
2936 if (!mt
->r8stencil_mt
) {
2937 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2938 mt
->r8stencil_mt
= make_surface(
2941 MESA_FORMAT_R_UINT8
,
2942 src
->first_level
, src
->last_level
,
2943 src
->surf
.logical_level0_px
.width
,
2944 src
->surf
.logical_level0_px
.height
,
2945 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2946 src
->surf
.logical_level0_px
.depth
:
2947 src
->surf
.logical_level0_px
.array_len
,
2950 ISL_SURF_USAGE_TEXTURE_BIT
,
2951 BO_ALLOC_BUSY
, 0, NULL
);
2952 assert(mt
->r8stencil_mt
);
2955 if (src
->r8stencil_needs_update
== false)
2958 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2960 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2961 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2962 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2963 src
->surf
.phys_level0_sa
.array_len
;
2965 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2966 brw_blorp_copy_miptrees(brw
,
2970 minify(src
->surf
.logical_level0_px
.width
,
2972 minify(src
->surf
.logical_level0_px
.height
,
2977 brw_cache_flush_for_read(brw
, dst
->bo
);
2978 src
->r8stencil_needs_update
= false;
2982 intel_miptree_map_raw(struct brw_context
*brw
,
2983 struct intel_mipmap_tree
*mt
,
2986 struct brw_bo
*bo
= mt
->bo
;
2988 if (brw_batch_references(&brw
->batch
, bo
))
2989 intel_batchbuffer_flush(brw
);
2991 return brw_bo_map(brw
, bo
, mode
);
2995 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2997 brw_bo_unmap(mt
->bo
);
3001 intel_miptree_unmap_map(struct brw_context
*brw
,
3002 struct intel_mipmap_tree
*mt
,
3003 struct intel_miptree_map
*map
,
3004 unsigned int level
, unsigned int slice
)
3006 intel_miptree_unmap_raw(mt
);
3010 intel_miptree_map_map(struct brw_context
*brw
,
3011 struct intel_mipmap_tree
*mt
,
3012 struct intel_miptree_map
*map
,
3013 unsigned int level
, unsigned int slice
)
3015 unsigned int bw
, bh
;
3017 unsigned int image_x
, image_y
;
3018 intptr_t x
= map
->x
;
3019 intptr_t y
= map
->y
;
3021 /* For compressed formats, the stride is the number of bytes per
3022 * row of blocks. intel_miptree_get_image_offset() already does
3025 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3026 assert(y
% bh
== 0);
3027 assert(x
% bw
== 0);
3031 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3032 map
->mode
& GL_MAP_WRITE_BIT
);
3034 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3041 /* Note that in the case of cube maps, the caller must have passed the
3042 * slice number referencing the face.
3044 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3048 map
->stride
= mt
->surf
.row_pitch_B
;
3049 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3052 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3053 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3054 map
->x
, map
->y
, map
->w
, map
->h
,
3055 mt
, _mesa_get_format_name(mt
->format
),
3056 x
, y
, map
->ptr
, map
->stride
);
3058 map
->unmap
= intel_miptree_unmap_map
;
3062 intel_miptree_unmap_blit(struct brw_context
*brw
,
3063 struct intel_mipmap_tree
*mt
,
3064 struct intel_miptree_map
*map
,
3068 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3069 struct gl_context
*ctx
= &brw
->ctx
;
3071 intel_miptree_unmap_raw(map
->linear_mt
);
3073 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3074 if (devinfo
->gen
>= 6) {
3075 brw_blorp_copy_miptrees(brw
, map
->linear_mt
, 0, 0,
3077 0, 0, map
->x
, map
->y
, map
->w
, map
->h
);
3079 bool ok
= intel_miptree_copy(brw
,
3080 map
->linear_mt
, 0, 0, 0, 0,
3081 mt
, level
, slice
, map
->x
, map
->y
,
3083 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3087 intel_miptree_release(&map
->linear_mt
);
3090 /* Compute extent parameters for use with tiled_memcpy functions.
3091 * xs are in units of bytes and ys are in units of strides.
3094 tile_extents(struct intel_mipmap_tree
*mt
, struct intel_miptree_map
*map
,
3095 unsigned int level
, unsigned int slice
, unsigned int *x1_B
,
3096 unsigned int *x2_B
, unsigned int *y1_el
, unsigned int *y2_el
)
3098 unsigned int block_width
, block_height
;
3099 unsigned int x0_el
, y0_el
;
3101 _mesa_get_format_block_size(mt
->format
, &block_width
, &block_height
);
3103 assert(map
->x
% block_width
== 0);
3104 assert(map
->y
% block_height
== 0);
3106 intel_miptree_get_image_offset(mt
, level
, slice
, &x0_el
, &y0_el
);
3107 *x1_B
= (map
->x
/ block_width
+ x0_el
) * mt
->cpp
;
3108 *y1_el
= map
->y
/ block_height
+ y0_el
;
3109 *x2_B
= (DIV_ROUND_UP(map
->x
+ map
->w
, block_width
) + x0_el
) * mt
->cpp
;
3110 *y2_el
= DIV_ROUND_UP(map
->y
+ map
->h
, block_height
) + y0_el
;
3114 intel_miptree_unmap_tiled_memcpy(struct brw_context
*brw
,
3115 struct intel_mipmap_tree
*mt
,
3116 struct intel_miptree_map
*map
,
3120 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3121 unsigned int x1
, x2
, y1
, y2
;
3122 tile_extents(mt
, map
, level
, slice
, &x1
, &x2
, &y1
, &y2
);
3124 char *dst
= intel_miptree_map_raw(brw
, mt
, map
->mode
| MAP_RAW
);
3127 isl_memcpy_linear_to_tiled(
3128 x1
, x2
, y1
, y2
, dst
, map
->ptr
, mt
->surf
.row_pitch_B
, map
->stride
,
3129 brw
->has_swizzling
, mt
->surf
.tiling
, ISL_MEMCPY
);
3131 intel_miptree_unmap_raw(mt
);
3133 _mesa_align_free(map
->buffer
);
3134 map
->buffer
= map
->ptr
= NULL
;
3138 * Determine which copy function to use for the given format combination
3140 * The only two possible copy functions which are ever returned are a
3141 * direct memcpy and a RGBA <-> BGRA copy function. Since RGBA -> BGRA and
3142 * BGRA -> RGBA are exactly the same operation (and memcpy is obviously
3143 * symmetric), it doesn't matter whether the copy is from the tiled image
3144 * to the untiled or vice versa. The copy function required is the same in
3145 * either case so this function can be used.
3147 * \param[in] tiledFormat The format of the tiled image
3148 * \param[in] format The GL format of the client data
3149 * \param[in] type The GL type of the client data
3150 * \param[out] mem_copy Will be set to one of either the standard
3151 * library's memcpy or a different copy function
3152 * that performs an RGBA to BGRA conversion
3153 * \param[out] cpp Number of bytes per channel
3155 * \return true if the format and type combination are valid
3157 MAYBE_UNUSED isl_memcpy_type
3158 intel_miptree_get_memcpy_type(mesa_format tiledFormat
, GLenum format
, GLenum type
,
3161 if (type
== GL_UNSIGNED_INT_8_8_8_8_REV
&&
3162 !(format
== GL_RGBA
|| format
== GL_BGRA
))
3163 return ISL_MEMCPY_INVALID
; /* Invalid type/format combination */
3165 if ((tiledFormat
== MESA_FORMAT_L_UNORM8
&& format
== GL_LUMINANCE
) ||
3166 (tiledFormat
== MESA_FORMAT_A_UNORM8
&& format
== GL_ALPHA
)) {
3169 } else if ((tiledFormat
== MESA_FORMAT_B8G8R8A8_UNORM
) ||
3170 (tiledFormat
== MESA_FORMAT_B8G8R8X8_UNORM
) ||
3171 (tiledFormat
== MESA_FORMAT_B8G8R8A8_SRGB
) ||
3172 (tiledFormat
== MESA_FORMAT_B8G8R8X8_SRGB
)) {
3174 if (format
== GL_BGRA
) {
3176 } else if (format
== GL_RGBA
) {
3177 return ISL_MEMCPY_BGRA8
;
3179 } else if ((tiledFormat
== MESA_FORMAT_R8G8B8A8_UNORM
) ||
3180 (tiledFormat
== MESA_FORMAT_R8G8B8X8_UNORM
) ||
3181 (tiledFormat
== MESA_FORMAT_R8G8B8A8_SRGB
) ||
3182 (tiledFormat
== MESA_FORMAT_R8G8B8X8_SRGB
)) {
3184 if (format
== GL_BGRA
) {
3185 /* Copying from RGBA to BGRA is the same as BGRA to RGBA so we can
3186 * use the same function.
3188 return ISL_MEMCPY_BGRA8
;
3189 } else if (format
== GL_RGBA
) {
3194 return ISL_MEMCPY_INVALID
;
3198 intel_miptree_map_tiled_memcpy(struct brw_context
*brw
,
3199 struct intel_mipmap_tree
*mt
,
3200 struct intel_miptree_map
*map
,
3201 unsigned int level
, unsigned int slice
)
3203 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3204 map
->mode
& GL_MAP_WRITE_BIT
);
3206 unsigned int x1
, x2
, y1
, y2
;
3207 tile_extents(mt
, map
, level
, slice
, &x1
, &x2
, &y1
, &y2
);
3208 map
->stride
= ALIGN(_mesa_format_row_stride(mt
->format
, map
->w
), 16);
3210 /* The tiling and detiling functions require that the linear buffer
3211 * has proper 16-byte alignment (that is, its `x0` is 16-byte
3212 * aligned). Here we over-allocate the linear buffer by enough
3213 * bytes to get the proper alignment.
3215 map
->buffer
= _mesa_align_malloc(map
->stride
* (y2
- y1
) + (x1
& 0xf), 16);
3216 map
->ptr
= (char *)map
->buffer
+ (x1
& 0xf);
3217 assert(map
->buffer
);
3219 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3220 char *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
| MAP_RAW
);
3223 const isl_memcpy_type copy_type
=
3224 #if defined(USE_SSE41)
3225 cpu_has_sse4_1
? ISL_MEMCPY_STREAMING_LOAD
:
3229 isl_memcpy_tiled_to_linear(
3230 x1
, x2
, y1
, y2
, map
->ptr
, src
, map
->stride
,
3231 mt
->surf
.row_pitch_B
, brw
->has_swizzling
, mt
->surf
.tiling
,
3234 intel_miptree_unmap_raw(mt
);
3237 map
->unmap
= intel_miptree_unmap_tiled_memcpy
;
3241 intel_miptree_map_blit(struct brw_context
*brw
,
3242 struct intel_mipmap_tree
*mt
,
3243 struct intel_miptree_map
*map
,
3244 unsigned int level
, unsigned int slice
)
3246 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3247 map
->linear_mt
= make_surface(brw
, GL_TEXTURE_2D
, mt
->format
,
3248 0, 0, map
->w
, map
->h
, 1, 1,
3249 ISL_TILING_LINEAR_BIT
,
3250 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
3251 ISL_SURF_USAGE_TEXTURE_BIT
,
3254 if (!map
->linear_mt
) {
3255 fprintf(stderr
, "Failed to allocate blit temporary\n");
3258 map
->stride
= map
->linear_mt
->surf
.row_pitch_B
;
3260 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3261 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3262 * invalidate is set, since we'll be writing the whole rectangle from our
3263 * temporary buffer back out.
3265 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3266 if (devinfo
->gen
>= 6) {
3267 brw_blorp_copy_miptrees(brw
, mt
, level
, slice
,
3268 map
->linear_mt
, 0, 0,
3269 map
->x
, map
->y
, 0, 0, map
->w
, map
->h
);
3271 if (!intel_miptree_copy(brw
,
3272 mt
, level
, slice
, map
->x
, map
->y
,
3273 map
->linear_mt
, 0, 0, 0, 0,
3275 fprintf(stderr
, "Failed to blit\n");
3281 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3283 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3284 map
->x
, map
->y
, map
->w
, map
->h
,
3285 mt
, _mesa_get_format_name(mt
->format
),
3286 level
, slice
, map
->ptr
, map
->stride
);
3288 map
->unmap
= intel_miptree_unmap_blit
;
3292 intel_miptree_release(&map
->linear_mt
);
3298 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3300 #if defined(USE_SSE41)
3302 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3303 struct intel_mipmap_tree
*mt
,
3304 struct intel_miptree_map
*map
,
3308 _mesa_align_free(map
->buffer
);
3314 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3315 struct intel_mipmap_tree
*mt
,
3316 struct intel_miptree_map
*map
,
3317 unsigned int level
, unsigned int slice
)
3319 assert(map
->mode
& GL_MAP_READ_BIT
);
3320 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3322 intel_miptree_access_raw(brw
, mt
, level
, slice
, false);
3324 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3325 map
->x
, map
->y
, map
->w
, map
->h
,
3326 mt
, _mesa_get_format_name(mt
->format
),
3327 level
, slice
, map
->ptr
, map
->stride
);
3329 /* Map the original image */
3332 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3336 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3342 src
+= image_y
* mt
->surf
.row_pitch_B
;
3343 src
+= image_x
* mt
->cpp
;
3345 /* Due to the pixel offsets for the particular image being mapped, our
3346 * src pointer may not be 16-byte aligned. However, if the pitch is
3347 * divisible by 16, then the amount by which it's misaligned will remain
3348 * consistent from row to row.
3350 assert((mt
->surf
.row_pitch_B
% 16) == 0);
3351 const int misalignment
= ((uintptr_t) src
) & 15;
3353 /* Create an untiled temporary buffer for the mapping. */
3354 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3356 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3358 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3359 /* Offset the destination so it has the same misalignment as src. */
3360 map
->ptr
= map
->buffer
+ misalignment
;
3362 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3364 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3365 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3366 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch_B
;
3368 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3371 intel_miptree_unmap_raw(mt
);
3373 map
->unmap
= intel_miptree_unmap_movntdqa
;
3378 intel_miptree_unmap_s8(struct brw_context
*brw
,
3379 struct intel_mipmap_tree
*mt
,
3380 struct intel_miptree_map
*map
,
3384 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3385 unsigned int image_x
, image_y
;
3386 uint8_t *untiled_s8_map
= map
->ptr
;
3387 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3389 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3391 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3392 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3393 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch_B
,
3394 image_x
+ x
+ map
->x
,
3395 image_y
+ y
+ map
->y
,
3396 brw
->has_swizzling
);
3397 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3401 intel_miptree_unmap_raw(mt
);
3408 intel_miptree_map_s8(struct brw_context
*brw
,
3409 struct intel_mipmap_tree
*mt
,
3410 struct intel_miptree_map
*map
,
3411 unsigned int level
, unsigned int slice
)
3413 map
->stride
= map
->w
;
3414 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3418 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3419 map
->mode
& GL_MAP_WRITE_BIT
);
3421 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3422 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3423 * invalidate is set, since we'll be writing the whole rectangle from our
3424 * temporary buffer back out.
3426 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3427 uint8_t *untiled_s8_map
= map
->ptr
;
3428 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3429 unsigned int image_x
, image_y
;
3431 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3433 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3434 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3435 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch_B
,
3436 x
+ image_x
+ map
->x
,
3437 y
+ image_y
+ map
->y
,
3438 brw
->has_swizzling
);
3439 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3443 intel_miptree_unmap_raw(mt
);
3445 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3446 map
->x
, map
->y
, map
->w
, map
->h
,
3447 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3449 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3450 map
->x
, map
->y
, map
->w
, map
->h
,
3451 mt
, map
->ptr
, map
->stride
);
3454 map
->unmap
= intel_miptree_unmap_s8
;
3458 intel_miptree_unmap_etc(struct brw_context
*brw
,
3459 struct intel_mipmap_tree
*mt
,
3460 struct intel_miptree_map
*map
,
3466 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3471 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3472 + image_y
* mt
->surf
.row_pitch_B
3473 + image_x
* mt
->cpp
;
3475 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3476 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch_B
,
3477 map
->ptr
, map
->stride
,
3480 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch_B
,
3481 map
->ptr
, map
->stride
,
3482 map
->w
, map
->h
, mt
->etc_format
, true);
3484 intel_miptree_unmap_raw(mt
);
3489 intel_miptree_map_etc(struct brw_context
*brw
,
3490 struct intel_mipmap_tree
*mt
,
3491 struct intel_miptree_map
*map
,
3495 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3496 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3497 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3500 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3501 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3503 intel_miptree_access_raw(brw
, mt
, level
, slice
, true);
3505 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3506 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3507 map
->w
, map
->h
, 1));
3508 map
->ptr
= map
->buffer
;
3509 map
->unmap
= intel_miptree_unmap_etc
;
3513 * Mapping functions for packed depth/stencil miptrees backed by real separate
3514 * miptrees for depth and stencil.
3516 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3517 * separate from the depth buffer. Yet at the GL API level, we have to expose
3518 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3519 * be able to map that memory for texture storage and glReadPixels-type
3520 * operations. We give Mesa core that access by mallocing a temporary and
3521 * copying the data between the actual backing store and the temporary.
3524 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3525 struct intel_mipmap_tree
*mt
,
3526 struct intel_miptree_map
*map
,
3530 struct intel_mipmap_tree
*z_mt
= mt
;
3531 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3532 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3534 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3535 uint32_t *packed_map
= map
->ptr
;
3536 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3537 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3538 unsigned int s_image_x
, s_image_y
;
3539 unsigned int z_image_x
, z_image_y
;
3541 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3542 &s_image_x
, &s_image_y
);
3543 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3544 &z_image_x
, &z_image_y
);
3546 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3547 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3548 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch_B
,
3549 x
+ s_image_x
+ map
->x
,
3550 y
+ s_image_y
+ map
->y
,
3551 brw
->has_swizzling
);
3552 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3553 (z_mt
->surf
.row_pitch_B
/ 4) +
3554 (x
+ z_image_x
+ map
->x
));
3556 if (map_z32f_x24s8
) {
3557 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3558 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3560 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3561 s_map
[s_offset
] = packed
>> 24;
3562 z_map
[z_offset
] = packed
;
3567 intel_miptree_unmap_raw(s_mt
);
3568 intel_miptree_unmap_raw(z_mt
);
3570 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3572 map
->x
, map
->y
, map
->w
, map
->h
,
3573 z_mt
, _mesa_get_format_name(z_mt
->format
),
3574 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3575 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3576 map
->ptr
, map
->stride
);
3583 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3584 struct intel_mipmap_tree
*mt
,
3585 struct intel_miptree_map
*map
,
3586 unsigned int level
, unsigned int slice
)
3588 struct intel_mipmap_tree
*z_mt
= mt
;
3589 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3590 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3591 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3593 map
->stride
= map
->w
* packed_bpp
;
3594 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3598 intel_miptree_access_raw(brw
, z_mt
, level
, slice
,
3599 map
->mode
& GL_MAP_WRITE_BIT
);
3600 intel_miptree_access_raw(brw
, s_mt
, level
, slice
,
3601 map
->mode
& GL_MAP_WRITE_BIT
);
3603 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3604 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3605 * invalidate is set, since we'll be writing the whole rectangle from our
3606 * temporary buffer back out.
3608 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3609 uint32_t *packed_map
= map
->ptr
;
3610 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3611 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3612 unsigned int s_image_x
, s_image_y
;
3613 unsigned int z_image_x
, z_image_y
;
3615 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3616 &s_image_x
, &s_image_y
);
3617 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3618 &z_image_x
, &z_image_y
);
3620 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3621 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3622 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3623 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch_B
,
3626 brw
->has_swizzling
);
3627 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3628 (z_mt
->surf
.row_pitch_B
/ 4) +
3629 (map_x
+ z_image_x
));
3630 uint8_t s
= s_map
[s_offset
];
3631 uint32_t z
= z_map
[z_offset
];
3633 if (map_z32f_x24s8
) {
3634 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3635 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3637 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3642 intel_miptree_unmap_raw(s_mt
);
3643 intel_miptree_unmap_raw(z_mt
);
3645 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3647 map
->x
, map
->y
, map
->w
, map
->h
,
3648 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3649 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3650 map
->ptr
, map
->stride
);
3652 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3653 map
->x
, map
->y
, map
->w
, map
->h
,
3654 mt
, map
->ptr
, map
->stride
);
3657 map
->unmap
= intel_miptree_unmap_depthstencil
;
3661 * Create and attach a map to the miptree at (level, slice). Return the
3664 static struct intel_miptree_map
*
3665 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3674 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3679 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3680 mt
->level
[level
].slice
[slice
].map
= map
;
3692 * Release the map at (level, slice).
3695 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3699 struct intel_miptree_map
**map
;
3701 map
= &mt
->level
[level
].slice
[slice
].map
;
3707 can_blit_slice(struct intel_mipmap_tree
*mt
,
3708 const struct intel_miptree_map
*map
)
3710 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3711 const unsigned src_blt_pitch
= intel_miptree_blt_pitch(mt
);
3712 const unsigned dst_blt_pitch
= ALIGN(map
->w
* mt
->cpp
, 64);
3713 return src_blt_pitch
< 32768 && dst_blt_pitch
< 32768;
3717 use_intel_mipree_map_blit(struct brw_context
*brw
,
3718 struct intel_mipmap_tree
*mt
,
3719 const struct intel_miptree_map
*map
)
3721 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3723 if (devinfo
->has_llc
&&
3724 /* It's probably not worth swapping to the blit ring because of
3725 * all the overhead involved.
3727 !(map
->mode
& GL_MAP_WRITE_BIT
) &&
3729 (mt
->surf
.tiling
== ISL_TILING_X
||
3730 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3731 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3732 /* Fast copy blit on skl+ supports all tiling formats. */
3733 devinfo
->gen
>= 9) &&
3734 can_blit_slice(mt
, map
))
3737 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3738 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3739 assert(can_blit_slice(mt
, map
));
3747 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3748 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3749 * arithmetic overflow.
3751 * If you call this function and use \a out_stride, then you're doing pointer
3752 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3753 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3754 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3755 * which usually have type uint32_t or GLuint.
3758 intel_miptree_map(struct brw_context
*brw
,
3759 struct intel_mipmap_tree
*mt
,
3768 ptrdiff_t *out_stride
)
3770 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3771 struct intel_miptree_map
*map
;
3773 assert(mt
->surf
.samples
== 1);
3775 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3782 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3783 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3784 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3785 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3786 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3787 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3788 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3789 } else if (use_intel_mipree_map_blit(brw
, mt
, map
)) {
3790 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3791 } else if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&& devinfo
->gen
> 4) {
3792 intel_miptree_map_tiled_memcpy(brw
, mt
, map
, level
, slice
);
3793 #if defined(USE_SSE41)
3794 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3795 !mt
->compressed
&& cpu_has_sse4_1
&&
3796 (mt
->surf
.row_pitch_B
% 16 == 0)) {
3797 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3800 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
3801 perf_debug("intel_miptree_map: mapping via gtt");
3802 intel_miptree_map_map(brw
, mt
, map
, level
, slice
);
3805 *out_ptr
= map
->ptr
;
3806 *out_stride
= map
->stride
;
3808 if (map
->ptr
== NULL
)
3809 intel_miptree_release_map(mt
, level
, slice
);
3813 intel_miptree_unmap(struct brw_context
*brw
,
3814 struct intel_mipmap_tree
*mt
,
3818 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3820 assert(mt
->surf
.samples
== 1);
3825 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3826 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3829 map
->unmap(brw
, mt
, map
, level
, slice
);
3831 intel_miptree_release_map(mt
, level
, slice
);
3835 get_isl_surf_dim(GLenum target
)
3839 case GL_TEXTURE_1D_ARRAY
:
3840 return ISL_SURF_DIM_1D
;
3843 case GL_TEXTURE_2D_ARRAY
:
3844 case GL_TEXTURE_RECTANGLE
:
3845 case GL_TEXTURE_CUBE_MAP
:
3846 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3847 case GL_TEXTURE_2D_MULTISAMPLE
:
3848 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3849 case GL_TEXTURE_EXTERNAL_OES
:
3850 return ISL_SURF_DIM_2D
;
3853 return ISL_SURF_DIM_3D
;
3856 unreachable("Invalid texture target");
3860 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3861 enum isl_tiling tiling
, GLenum target
)
3865 case GL_TEXTURE_1D_ARRAY
:
3866 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3867 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3870 case GL_TEXTURE_2D_ARRAY
:
3871 case GL_TEXTURE_RECTANGLE
:
3872 case GL_TEXTURE_2D_MULTISAMPLE
:
3873 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3874 case GL_TEXTURE_EXTERNAL_OES
:
3875 return ISL_DIM_LAYOUT_GEN4_2D
;
3877 case GL_TEXTURE_CUBE_MAP
:
3878 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3879 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3880 ISL_DIM_LAYOUT_GEN4_2D
);
3883 return (devinfo
->gen
>= 9 ?
3884 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3887 unreachable("Invalid texture target");
3891 intel_miptree_set_clear_color(struct brw_context
*brw
,
3892 struct intel_mipmap_tree
*mt
,
3893 union isl_color_value clear_color
)
3895 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3896 mt
->fast_clear_color
= clear_color
;
3897 if (mt
->aux_buf
->clear_color_bo
) {
3898 /* We can't update the clear color while the hardware is still using
3899 * the previous one for a resolve or sampling from it. Make sure that
3900 * there are no pending commands at this point.
3902 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
3903 for (int i
= 0; i
< 4; i
++) {
3904 brw_store_data_imm32(brw
, mt
->aux_buf
->clear_color_bo
,
3905 mt
->aux_buf
->clear_color_offset
+ i
* 4,
3906 mt
->fast_clear_color
.u32
[i
]);
3908 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_STATE_CACHE_INVALIDATE
);
3910 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3916 union isl_color_value
3917 intel_miptree_get_clear_color(const struct gen_device_info
*devinfo
,
3918 const struct intel_mipmap_tree
*mt
,
3919 enum isl_format view_format
, bool sampling
,
3920 struct brw_bo
**clear_color_bo
,
3921 uint64_t *clear_color_offset
)
3923 assert(mt
->aux_buf
);
3925 if (devinfo
->gen
== 10 && isl_format_is_srgb(view_format
) && sampling
) {
3926 /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
3927 * we switch to using the inline clear color and do the sRGB color
3928 * conversion process defined in the OpenGL spec. The red, green, and
3929 * blue channels take part in gamma correction, while the alpha channel
3932 union isl_color_value srgb_decoded_value
= mt
->fast_clear_color
;
3933 for (unsigned i
= 0; i
< 3; i
++) {
3934 srgb_decoded_value
.f32
[i
] =
3935 util_format_srgb_to_linear_float(mt
->fast_clear_color
.f32
[i
]);
3937 *clear_color_bo
= 0;
3938 *clear_color_offset
= 0;
3939 return srgb_decoded_value
;
3941 *clear_color_bo
= mt
->aux_buf
->clear_color_bo
;
3942 *clear_color_offset
= mt
->aux_buf
->clear_color_offset
;
3943 return mt
->fast_clear_color
;