src/mesa/drivers/dri/i965/intel_mipmap_tree.h

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  27
  28 #ifndef INTEL_MIPMAP_TREE_H
  29 #define INTEL_MIPMAP_TREE_H
  30
  31 #include <assert.h>
  32
  33 #include "intel_regions.h"
  34 #include "intel_resolve_map.h"
  35 #include <GL/internal/dri_interface.h>
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 /* A layer on top of the intel_regions code which adds:
  42  *
  43  * - Code to size and layout a region to hold a set of mipmaps.
  44  * - Query to determine if a new image fits in an existing tree.
  45  * - More refcounting
  46  *     - maybe able to remove refcounting from intel_region?
  47  * - ?
  48  *
  49  * The fixed mipmap layout of intel hardware where one offset
  50  * specifies the position of all images in a mipmap hierachy
  51  * complicates the implementation of GL texture image commands,
  52  * compared to hardware where each image is specified with an
  53  * independent offset.
  54  *
  55  * In an ideal world, each texture object would be associated with a
  56  * single bufmgr buffer or 2d intel_region, and all the images within
  57  * the texture object would slot into the tree as they arrive.  The
  58  * reality can be a little messier, as images can arrive from the user
  59  * with sizes that don't fit in the existing tree, or in an order
  60  * where the tree layout cannot be guessed immediately.
  61  *
  62  * This structure encodes an idealized mipmap tree.  The GL image
  63  * commands build these where possible, otherwise store the images in
  64  * temporary system buffers.
  65  */
  66
  67 struct intel_resolve_map;
  68 struct intel_texture_image;
  69
  70 /**
  71  * When calling intel_miptree_map() on an ETC-transcoded-to-RGB miptree or a
  72  * depthstencil-split-to-separate-stencil miptree, we'll normally make a
  73  * tmeporary and recreate the kind of data requested by Mesa core, since we're
  74  * satisfying some glGetTexImage() request or something.
  75  *
  76  * However, occasionally you want to actually map the miptree's current data
  77  * without transcoding back.  This flag to intel_miptree_map() gets you that.
  78  */
  79 #define BRW_MAP_DIRECT_BIT      0x80000000
  80
  81 struct intel_miptree_map {
  82    /** Bitfield of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT, GL_MAP_INVALIDATE_BIT */
  83    GLbitfield mode;
  84    /** Region of interest for the map. */
  85    int x, y, w, h;
  86    /** Possibly malloced temporary buffer for the mapping. */
  87    void *buffer;
  88    /** Possible pointer to a temporary linear miptree for the mapping. */
  89    struct intel_mipmap_tree *mt;
  90    /** Pointer to the start of (map_x, map_y) returned by the mapping. */
  91    void *ptr;
  92    /** Stride of the mapping. */
  93    int stride;
  94
  95    /**
  96     * intel_mipmap_tree::singlesample_mt is temporary storage that persists
  97     * only for the duration of the map.
  98     */
  99    bool singlesample_mt_is_tmp;
 100 };
 101
 102 /**
 103  * Describes the location of each texture image within a texture region.
 104  */
 105 struct intel_mipmap_level
 106 {
 107    /** Offset to this miptree level, used in computing x_offset. */
 108    GLuint level_x;
 109    /** Offset to this miptree level, used in computing y_offset. */
 110    GLuint level_y;
 111    GLuint width;
 112    GLuint height;
 113
 114    /**
 115     * \brief Number of 2D slices in this miplevel.
 116     *
 117     * The exact semantics of depth varies according to the texture target:
 118     *    - For GL_TEXTURE_CUBE_MAP, depth is 6.
 119     *    - For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
 120     *      identical for all miplevels in the texture.
 121     *    - For GL_TEXTURE_3D, it is the texture's depth at this miplevel. Its
 122     *      value, like width and height, varies with miplevel.
 123     *    - For other texture types, depth is 1.
 124     */
 125    GLuint depth;
 126
 127    /**
 128     * \brief List of 2D images in this mipmap level.
 129     *
 130     * This may be a list of cube faces, array slices in 2D array texture, or
 131     * layers in a 3D texture. The list's length is \c depth.
 132     */
 133    struct intel_mipmap_slice {
 134       /**
 135        * \name Offset to slice
 136        * \{
 137        *
 138        * Hardware formats are so diverse that that there is no unified way to
 139        * compute the slice offsets, so we store them in this table.
 140        *
 141        * The (x, y) offset to slice \c s at level \c l relative the miptrees
 142        * base address is
 143        * \code
 144        *     x = mt->level[l].slice[s].x_offset
 145        *     y = mt->level[l].slice[s].y_offset
 146        */
 147       GLuint x_offset;
 148       GLuint y_offset;
 149       /** \} */
 150
 151       /**
 152        * Mapping information. Persistent for the duration of
 153        * intel_miptree_map/unmap on this slice.
 154        */
 155       struct intel_miptree_map *map;
 156
 157       /**
 158        * \brief Is HiZ enabled for this slice?
 159        *
 160        * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
 161        * has been allocated and (2) the HiZ memory corresponding to this slice
 162        * resides at \c mt->hiz_mt->level[l].slice[s].
 163        */
 164       bool has_hiz;
 165    } *slice;
 166 };
 167
 168 /**
 169  * Enum for keeping track of the different MSAA layouts supported by Gen7.
 170  */
 171 enum intel_msaa_layout
 172 {
 173    /**
 174     * Ordinary surface with no MSAA.
 175     */
 176    INTEL_MSAA_LAYOUT_NONE,
 177
 178    /**
 179     * Interleaved Multisample Surface.  The additional samples are
 180     * accommodated by scaling up the width and the height of the surface so
 181     * that all the samples corresponding to a pixel are located at nearby
 182     * memory locations.
 183     */
 184    INTEL_MSAA_LAYOUT_IMS,
 185
 186    /**
 187     * Uncompressed Multisample Surface.  The surface is stored as a 2D array,
 188     * with array slice n containing all pixel data for sample n.
 189     */
 190    INTEL_MSAA_LAYOUT_UMS,
 191
 192    /**
 193     * Compressed Multisample Surface.  The surface is stored as in
 194     * INTEL_MSAA_LAYOUT_UMS, but there is an additional buffer called the MCS
 195     * (Multisample Control Surface) buffer.  Each pixel in the MCS buffer
 196     * indicates the mapping from sample number to array slice.  This allows
 197     * the common case (where all samples constituting a pixel have the same
 198     * color value) to be stored efficiently by just using a single array
 199     * slice.
 200     */
 201    INTEL_MSAA_LAYOUT_CMS,
 202 };
 203
 204
 205 /**
 206  * Enum for keeping track of the fast clear state of a buffer associated with
 207  * a miptree.
 208  *
 209  * Fast clear works by deferring the memory writes that would be used to clear
 210  * the buffer, so that instead of performing them at the time of the clear
 211  * operation, the hardware automatically performs them at the time that the
 212  * buffer is later accessed for rendering.  The MCS buffer keeps track of
 213  * which regions of the buffer still have pending clear writes.
 214  *
 215  * This enum keeps track of the driver's knowledge of pending fast clears in
 216  * the MCS buffer.
 217  *
 218  * MCS buffers only exist on Gen7+.
 219  */
 220 enum intel_fast_clear_state
 221 {
 222    /**
 223     * There is no MCS buffer for this miptree, and one should never be
 224     * allocated.
 225     */
 226    INTEL_FAST_CLEAR_STATE_NO_MCS,
 227
 228    /**
 229     * No deferred clears are pending for this miptree, and the contents of the
 230     * color buffer are entirely correct.  An MCS buffer may or may not exist
 231     * for this miptree.  If it does exist, it is entirely in the "no deferred
 232     * clears pending" state.  If it does not exist, it will be created the
 233     * first time a fast color clear is executed.
 234     *
 235     * In this state, the color buffer can be used for purposes other than
 236     * rendering without needing a render target resolve.
 237     *
 238     * Since there is no such thing as a "fast color clear resolve" for MSAA
 239     * buffers, an MSAA buffer will never be in this state.
 240     */
 241    INTEL_FAST_CLEAR_STATE_RESOLVED,
 242
 243    /**
 244     * An MCS buffer exists for this miptree, and deferred clears are pending
 245     * for some regions of the color buffer, as indicated by the MCS buffer.
 246     * The contents of the color buffer are only correct for the regions where
 247     * the MCS buffer doesn't indicate a deferred clear.
 248     *
 249     * If a single-sample buffer is in this state, a render target resolve must
 250     * be performed before it can be used for purposes other than rendering.
 251     */
 252    INTEL_FAST_CLEAR_STATE_UNRESOLVED,
 253
 254    /**
 255     * An MCS buffer exists for this miptree, and deferred clears are pending
 256     * for the entire color buffer, and the contents of the MCS buffer reflect
 257     * this.  The contents of the color buffer are undefined.
 258     *
 259     * If a single-sample buffer is in this state, a render target resolve must
 260     * be performed before it can be used for purposes other than rendering.
 261     *
 262     * If the client attempts to clear a buffer which is already in this state,
 263     * the clear can be safely skipped, since the buffer is already clear.
 264     */
 265    INTEL_FAST_CLEAR_STATE_CLEAR,
 266 };
 267
 268 struct intel_mipmap_tree
 269 {
 270    /* Effectively the key:
 271     */
 272    GLenum target;
 273
 274    /**
 275     * Generally, this is just the same as the gl_texture_image->TexFormat or
 276     * gl_renderbuffer->Format.
 277     *
 278     * However, for textures and renderbuffers with packed depth/stencil formats
 279     * on hardware where we want or need to use separate stencil, there will be
 280     * two miptrees for storing the data.  If the depthstencil texture or rb is
 281     * MESA_FORMAT_Z32_FLOAT_X24S8, then mt->format will be
 282     * MESA_FORMAT_Z32_FLOAT, otherwise for MESA_FORMAT_S8_Z24 objects it will be
 283     * MESA_FORMAT_X8_Z24.
 284     *
 285     * For ETC1/ETC2 textures, this is one of the uncompressed mesa texture
 286     * formats if the hardware lacks support for ETC1/ETC2. See @ref wraps_etc.
 287     */
 288    gl_format format;
 289
 290    /** This variable stores the value of ETC compressed texture format */
 291    gl_format etc_format;
 292
 293    /**
 294     * The X offset of each image in the miptree must be aligned to this.
 295     * See the comments in brw_tex_layout.c.
 296     */
 297    unsigned int align_w;
 298    unsigned int align_h; /**< \see align_w */
 299
 300    GLuint first_level;
 301    GLuint last_level;
 302
 303    /**
 304     * Level zero image dimensions.  These dimensions correspond to the
 305     * physical layout of data in memory.  Accordingly, they account for the
 306     * extra width, height, and or depth that must be allocated in order to
 307     * accommodate multisample formats, and they account for the extra factor
 308     * of 6 in depth that must be allocated in order to accommodate cubemap
 309     * textures.
 310     */
 311    GLuint physical_width0, physical_height0, physical_depth0;
 312
 313    GLuint cpp;
 314    GLuint num_samples;
 315    bool compressed;
 316
 317    /**
 318     * Level zero image dimensions.  These dimensions correspond to the
 319     * logical width, height, and depth of the region as seen by client code.
 320     * Accordingly, they do not account for the extra width, height, and/or
 321     * depth that must be allocated in order to accommodate multisample
 322     * formats, nor do they account for the extra factor of 6 in depth that
 323     * must be allocated in order to accommodate cubemap textures.
 324     */
 325    uint32_t logical_width0, logical_height0, logical_depth0;
 326
 327    /**
 328     * For 1D array, 2D array, cube, and 2D multisampled surfaces on Gen7: true
 329     * if the surface only contains LOD 0, and hence no space is for LOD's
 330     * other than 0 in between array slices.
 331     *
 332     * Corresponds to the surface_array_spacing bit in gen7_surface_state.
 333     */
 334    bool array_spacing_lod0;
 335
 336    /**
 337     * The distance in rows between array slices.
 338     */
 339    uint32_t qpitch;
 340
 341    /**
 342     * MSAA layout used by this buffer.
 343     */
 344    enum intel_msaa_layout msaa_layout;
 345
 346    /* Derived from the above:
 347     */
 348    GLuint total_width;
 349    GLuint total_height;
 350
 351    /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to
 352     * this depth mipmap tree, if any.
 353     */
 354    uint32_t depth_clear_value;
 355
 356    /* Includes image offset tables:
 357     */
 358    struct intel_mipmap_level level[MAX_TEXTURE_LEVELS];
 359
 360    /* The data is held here:
 361     */
 362    struct intel_region *region;
 363
 364    /* Offset into region bo where miptree starts:
 365     */
 366    uint32_t offset;
 367
 368    /**
 369     * \brief Singlesample miptree.
 370     *
 371     * This is used under two cases.
 372     *
 373     * --- Case 1: As persistent singlesample storage for multisample window
 374     *  system front and back buffers ---
 375     *
 376     * Suppose that the window system FBO was created with a multisample
 377     * config.  Let `back_irb` be the `intel_renderbuffer` for the FBO's back
 378     * buffer. Then `back_irb` contains two miptrees: a parent multisample
 379     * miptree (back_irb->mt) and a child singlesample miptree
 380     * (back_irb->mt->singlesample_mt).  The DRM buffer shared with DRI2
 381     * belongs to `back_irb->mt->singlesample_mt` and contains singlesample
 382     * data.  The singlesample miptree is created at the same time as and
 383     * persists for the lifetime of its parent multisample miptree.
 384     *
 385     * When access to the singlesample data is needed, such as at
 386     * eglSwapBuffers and glReadPixels, an automatic downsample occurs from
 387     * `back_rb->mt` to `back_rb->mt->singlesample_mt` when necessary.
 388     *
 389     * This description of the back buffer applies analogously to the front
 390     * buffer.
 391     *
 392     *
 393     * --- Case 2: As temporary singlesample storage for mapping multisample
 394     *  miptrees ---
 395     *
 396     * Suppose the intel_miptree_map is called on a multisample miptree, `mt`,
 397     * for which case 1 does not apply (that is, `mt` does not belong to
 398     * a front or back buffer).  Then `mt->singlesample_mt` is null at the
 399     * start of the call. intel_miptree_map will create a temporary
 400     * singlesample miptree, store it at `mt->singlesample_mt`, downsample from
 401     * `mt` to `mt->singlesample_mt` if necessary, then map
 402     * `mt->singlesample_mt`. The temporary miptree is later deleted during
 403     * intel_miptree_unmap.
 404     */
 405    struct intel_mipmap_tree *singlesample_mt;
 406
 407    /**
 408     * \brief A downsample is needed from this miptree to singlesample_mt.
 409     */
 410    bool need_downsample;
 411
 412    /**
 413     * \brief HiZ miptree
 414     *
 415     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
 416     * miptree, use intel_miptree_alloc_hiz().
 417     *
 418     * To determine if hiz is enabled, do not check this pointer. Instead, use
 419     * intel_miptree_slice_has_hiz().
 420     */
 421    struct intel_mipmap_tree *hiz_mt;
 422
 423    /**
 424     * \brief Map of miptree slices to needed resolves.
 425     *
 426     * This is used only when the miptree has a child HiZ miptree.
 427     *
 428     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
 429     * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
 430     * mt->hiz_mt->hiz_map, is unused.
 431     */
 432    struct intel_resolve_map hiz_map;
 433
 434    /**
 435     * \brief Stencil miptree for depthstencil textures.
 436     *
 437     * This miptree is used for depthstencil textures and renderbuffers that
 438     * require separate stencil.  It always has the true copy of the stencil
 439     * bits, regardless of mt->format.
 440     *
 441     * \see intel_miptree_map_depthstencil()
 442     * \see intel_miptree_unmap_depthstencil()
 443     */
 444    struct intel_mipmap_tree *stencil_mt;
 445
 446    /**
 447     * \brief MCS miptree.
 448     *
 449     * This miptree contains the "multisample control surface", which stores
 450     * the necessary information to implement compressed MSAA
 451     * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
 452     *
 453     * NULL if no MCS miptree is in use for this surface.
 454     */
 455    struct intel_mipmap_tree *mcs_mt;
 456
 457    /**
 458     * Fast clear state for this buffer.
 459     */
 460    enum intel_fast_clear_state fast_clear_state;
 461
 462    /**
 463     * The SURFACE_STATE bits associated with the last fast color clear to this
 464     * color mipmap tree, if any.
 465     *
 466     * This value will only ever contain ones in bits 28-31, so it is safe to
 467     * OR into dword 7 of SURFACE_STATE.
 468     */
 469    uint32_t fast_clear_color_value;
 470
 471    /* These are also refcounted:
 472     */
 473    GLuint refcount;
 474 };
 475
 476 enum intel_miptree_tiling_mode {
 477    INTEL_MIPTREE_TILING_ANY,
 478    INTEL_MIPTREE_TILING_Y,
 479    INTEL_MIPTREE_TILING_NONE,
 480 };
 481
 482 bool
 483 intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
 484                                        struct intel_mipmap_tree *mt);
 485
 486 void
 487 intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
 488                                  struct intel_mipmap_tree *mt,
 489                                  unsigned *width_px, unsigned *height);
 490
 491 bool
 492 intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
 493                                  struct intel_mipmap_tree *mt);
 494
 495 struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
 496                                                GLenum target,
 497                                                gl_format format,
 498                                                GLuint first_level,
 499                                                GLuint last_level,
 500                                                GLuint width0,
 501                                                GLuint height0,
 502                                                GLuint depth0,
 503                                                bool expect_accelerated_upload,
 504                                                GLuint num_samples,
 505                                                enum intel_miptree_tiling_mode);
 506
 507 struct intel_mipmap_tree *
 508 intel_miptree_create_layout(struct brw_context *brw,
 509                             GLenum target,
 510                             gl_format format,
 511                             GLuint first_level,
 512                             GLuint last_level,
 513                             GLuint width0,
 514                             GLuint height0,
 515                             GLuint depth0,
 516                             bool for_bo,
 517                             GLuint num_samples);
 518
 519 struct intel_mipmap_tree *
 520 intel_miptree_create_for_bo(struct brw_context *brw,
 521                             drm_intel_bo *bo,
 522                             gl_format format,
 523                             uint32_t offset,
 524                             uint32_t width,
 525                             uint32_t height,
 526                             int pitch,
 527                             uint32_t tiling);
 528
 529 struct intel_mipmap_tree*
 530 intel_miptree_create_for_dri2_buffer(struct brw_context *brw,
 531                                      unsigned dri_attachment,
 532                                      gl_format format,
 533                                      uint32_t num_samples,
 534                                      struct intel_region *region);
 535
 536 struct intel_mipmap_tree*
 537 intel_miptree_create_for_image_buffer(struct brw_context *intel,
 538                                      enum __DRIimageBufferMask buffer_type,
 539                                      gl_format format,
 540                                      uint32_t num_samples,
 541                                      struct intel_region *region);
 542
 543 /**
 544  * Create a miptree appropriate as the storage for a non-texture renderbuffer.
 545  * The miptree has the following properties:
 546  *     - The target is GL_TEXTURE_2D.
 547  *     - There are no levels other than the base level 0.
 548  *     - Depth is 1.
 549  */
 550 struct intel_mipmap_tree*
 551 intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 552                                       gl_format format,
 553                                       uint32_t width,
 554                                       uint32_t height,
 555                                       uint32_t num_samples);
 556
 557 /** \brief Assert that the level and layer are valid for the miptree. */
 558 static inline void
 559 intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
 560                                 uint32_t level,
 561                                 uint32_t layer)
 562 {
 563    assert(level >= mt->first_level);
 564    assert(level <= mt->last_level);
 565    assert(layer < mt->level[level].depth);
 566 }
 567
 568 void intel_miptree_reference(struct intel_mipmap_tree **dst,
 569                              struct intel_mipmap_tree *src);
 570
 571 void intel_miptree_release(struct intel_mipmap_tree **mt);
 572
 573 /* Check if an image fits an existing mipmap tree layout
 574  */
 575 bool intel_miptree_match_image(struct intel_mipmap_tree *mt,
 576                                     struct gl_texture_image *image);
 577
 578 void
 579 intel_miptree_get_image_offset(struct intel_mipmap_tree *mt,
 580                                GLuint level, GLuint slice,
 581                                GLuint *x, GLuint *y);
 582
 583 void
 584 intel_miptree_get_dimensions_for_image(struct gl_texture_image *image,
 585                                        int *width, int *height, int *depth);
 586
 587 uint32_t
 588 intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
 589                                GLuint level, GLuint slice,
 590                                uint32_t *tile_x,
 591                                uint32_t *tile_y);
 592
 593 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 594                                   GLuint level,
 595                                   GLuint x, GLuint y,
 596                                   GLuint w, GLuint h, GLuint d);
 597
 598 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
 599                                     GLuint level,
 600                                     GLuint img, GLuint x, GLuint y);
 601
 602 void
 603 intel_miptree_copy_teximage(struct brw_context *brw,
 604                             struct intel_texture_image *intelImage,
 605                             struct intel_mipmap_tree *dst_mt, bool invalidate);
 606
 607 bool
 608 intel_miptree_alloc_mcs(struct brw_context *brw,
 609                         struct intel_mipmap_tree *mt,
 610                         GLuint num_samples);
 611
 612 /**
 613  * \name Miptree HiZ functions
 614  * \{
 615  *
 616  * It is safe to call the "slice_set_need_resolve" and "slice_resolve"
 617  * functions on a miptree without HiZ. In that case, each function is a no-op.
 618  */
 619
 620 /**
 621  * \brief Allocate the miptree's embedded HiZ miptree.
 622  * \see intel_mipmap_tree:hiz_mt
 623  * \return false if allocation failed
 624  */
 625
 626 bool
 627 intel_miptree_alloc_hiz(struct brw_context *brw,
 628                         struct intel_mipmap_tree *mt);
 629
 630 bool
 631 intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,
 632                             uint32_t level,
 633                             uint32_t layer);
 634
 635 void
 636 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt,
 637                                           uint32_t level,
 638                                           uint32_t depth);
 639 void
 640 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt,
 641                                             uint32_t level,
 642                                             uint32_t depth);
 643
 644 void
 645 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree *mt,
 646                                                 uint32_t level);
 647
 648 /**
 649  * \return false if no resolve was needed
 650  */
 651 bool
 652 intel_miptree_slice_resolve_hiz(struct brw_context *brw,
 653                                 struct intel_mipmap_tree *mt,
 654                                 unsigned int level,
 655                                 unsigned int depth);
 656
 657 /**
 658  * \return false if no resolve was needed
 659  */
 660 bool
 661 intel_miptree_slice_resolve_depth(struct brw_context *brw,
 662                                   struct intel_mipmap_tree *mt,
 663                                   unsigned int level,
 664                                   unsigned int depth);
 665
 666 /**
 667  * \return false if no resolve was needed
 668  */
 669 bool
 670 intel_miptree_all_slices_resolve_hiz(struct brw_context *brw,
 671                                      struct intel_mipmap_tree *mt);
 672
 673 /**
 674  * \return false if no resolve was needed
 675  */
 676 bool
 677 intel_miptree_all_slices_resolve_depth(struct brw_context *brw,
 678                                        struct intel_mipmap_tree *mt);
 679
 680 /**\}*/
 681
 682 /**
 683  * Update the fast clear state for a miptree to indicate that it has been used
 684  * for rendering.
 685  */
 686 static inline void
 687 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 688 {
 689    /* If the buffer was previously in fast clear state, change it to
 690     * unresolved state, since it won't be guaranteed to be clear after
 691     * rendering occurs.
 692     */
 693    if (mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_CLEAR)
 694       mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
 695 }
 696
 697 void
 698 intel_miptree_resolve_color(struct brw_context *brw,
 699                             struct intel_mipmap_tree *mt);
 700
 701 void
 702 intel_miptree_make_shareable(struct brw_context *brw,
 703                              struct intel_mipmap_tree *mt);
 704
 705 void
 706 intel_miptree_downsample(struct brw_context *brw,
 707                          struct intel_mipmap_tree *mt);
 708
 709 void
 710 intel_miptree_upsample(struct brw_context *brw,
 711                        struct intel_mipmap_tree *mt);
 712
 713 void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
 714
 715 void *intel_miptree_map_raw(struct brw_context *brw,
 716                             struct intel_mipmap_tree *mt);
 717
 718 void intel_miptree_unmap_raw(struct brw_context *brw,
 719                              struct intel_mipmap_tree *mt);
 720
 721 void
 722 intel_miptree_map(struct brw_context *brw,
 723                   struct intel_mipmap_tree *mt,
 724                   unsigned int level,
 725                   unsigned int slice,
 726                   unsigned int x,
 727                   unsigned int y,
 728                   unsigned int w,
 729                   unsigned int h,
 730                   GLbitfield mode,
 731                   void **out_ptr,
 732                   int *out_stride);
 733
 734 void
 735 intel_miptree_unmap(struct brw_context *brw,
 736                     struct intel_mipmap_tree *mt,
 737                     unsigned int level,
 738                     unsigned int slice);
 739
 740 void
 741 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 742                unsigned int level, unsigned int layer, enum gen6_hiz_op op);
 743
 744 #ifdef __cplusplus
 745 }
 746 #endif
 747
 748 #endif