2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
44 #include "util/xmlpool.h"
46 static const __DRIconfigOptionsExtension brw_config_options
= {
47 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
50 DRI_CONF_SECTION_PERFORMANCE
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_MESA_NO_ERROR("false")
63 DRI_CONF_SECTION_QUALITY
64 DRI_CONF_PRECISE_TRIG("false")
66 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
67 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
68 "given integer. If negative, then do not clamp.")
72 DRI_CONF_SECTION_DEBUG
73 DRI_CONF_NO_RAST("false")
74 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
75 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
76 DRI_CONF_DISABLE_THROTTLING("false")
77 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
78 DRI_CONF_FORCE_GLSL_VERSION(0)
79 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
80 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
81 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
82 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
83 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
84 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
85 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
86 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
88 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
89 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
93 DRI_CONF_SECTION_MISCELLANEOUS
94 DRI_CONF_GLSL_ZERO_INIT("false")
95 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
100 #include "intel_batchbuffer.h"
101 #include "intel_buffers.h"
102 #include "brw_bufmgr.h"
103 #include "intel_fbo.h"
104 #include "intel_mipmap_tree.h"
105 #include "intel_screen.h"
106 #include "intel_tex.h"
107 #include "intel_image.h"
109 #include "brw_context.h"
111 #include "i915_drm.h"
114 * For debugging purposes, this returns a time in seconds.
121 clock_gettime(CLOCK_MONOTONIC
, &tp
);
123 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
126 static const __DRItexBufferExtension intelTexBufferExtension
= {
127 .base
= { __DRI_TEX_BUFFER
, 3 },
129 .setTexBuffer
= intelSetTexBuffer
,
130 .setTexBuffer2
= intelSetTexBuffer2
,
131 .releaseTexBuffer
= NULL
,
135 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
136 __DRIdrawable
*dPriv
,
138 enum __DRI2throttleReason reason
)
140 struct brw_context
*brw
= cPriv
->driverPrivate
;
145 struct gl_context
*ctx
= &brw
->ctx
;
147 FLUSH_VERTICES(ctx
, 0);
149 if (flags
& __DRI2_FLUSH_DRAWABLE
)
150 intel_resolve_for_dri2_flush(brw
, dPriv
);
152 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
153 brw
->need_swap_throttle
= true;
154 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
155 brw
->need_flush_throttle
= true;
157 intel_batchbuffer_flush(brw
);
161 * Provides compatibility with loaders that only support the older (version
162 * 1-3) flush interface.
164 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
167 intel_dri2_flush(__DRIdrawable
*drawable
)
169 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
170 __DRI2_FLUSH_DRAWABLE
,
171 __DRI2_THROTTLE_SWAPBUFFER
);
174 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
175 .base
= { __DRI2_FLUSH
, 4 },
177 .flush
= intel_dri2_flush
,
178 .invalidate
= dri2InvalidateDrawable
,
179 .flush_with_flags
= intel_dri2_flush_with_flags
,
182 static const struct intel_image_format intel_image_formats
[] = {
183 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
184 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
186 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
187 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
189 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
192 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
195 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
198 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
201 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
204 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
207 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
210 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
213 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
216 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
219 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
222 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
225 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
227 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
230 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
232 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
237 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
242 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
276 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
280 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
281 * and treat them as planar buffers in the compositors.
282 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
283 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
284 * clusters and places pairs and places U into the G component and
285 * V into A. This lets the texture sampler interpolate the Y
286 * components correctly when sampling from plane 0, and interpolate
287 * U and V correctly when sampling from plane 1. */
288 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
289 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
290 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
291 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
292 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
293 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
296 static const struct {
299 } supported_modifiers
[] = {
300 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
301 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
302 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
303 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
307 modifier_is_supported(const struct gen_device_info
*devinfo
,
308 const struct intel_image_format
*fmt
, int dri_format
,
311 const struct isl_drm_modifier_info
*modinfo
=
312 isl_drm_modifier_get_info(modifier
);
315 /* ISL had better know about the modifier */
319 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
320 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
321 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
324 /* CCS_E is not supported for planar images */
325 if (fmt
&& fmt
->nplanes
> 1)
329 assert(dri_format
== 0);
330 dri_format
= fmt
->planes
[0].dri_format
;
333 mesa_format format
= driImageFormatToGLFormat(dri_format
);
334 format
= _mesa_get_srgb_format_linear(format
);
335 if (!isl_format_supports_ccs_e(devinfo
,
336 brw_isl_format_for_mesa_format(format
)))
340 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
341 if (supported_modifiers
[i
].modifier
!= modifier
)
344 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
351 tiling_to_modifier(uint32_t tiling
)
353 static const uint64_t map
[] = {
354 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
355 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
356 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
359 assert(tiling
< ARRAY_SIZE(map
));
365 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
367 uint32_t tiling
, swizzle
;
368 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
370 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
371 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
372 func
, image
->offset
);
376 static const struct intel_image_format
*
377 intel_image_format_lookup(int fourcc
)
379 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
380 if (intel_image_formats
[i
].fourcc
== fourcc
)
381 return &intel_image_formats
[i
];
387 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
389 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
390 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
391 *fourcc
= intel_image_formats
[i
].fourcc
;
399 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
404 image
= calloc(1, sizeof *image
);
408 image
->screen
= screen
;
409 image
->dri_format
= dri_format
;
412 image
->format
= driImageFormatToGLFormat(dri_format
);
413 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
414 image
->format
== MESA_FORMAT_NONE
) {
419 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
420 image
->data
= loaderPrivate
;
426 * Sets up a DRIImage structure to point to a slice out of a miptree.
429 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
430 struct intel_mipmap_tree
*mt
, GLuint level
,
433 intel_miptree_make_shareable(brw
, mt
);
435 intel_miptree_check_level_layer(mt
, level
, zoffset
);
437 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
438 level
- mt
->first_level
);
439 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
440 level
- mt
->first_level
);
441 image
->pitch
= mt
->surf
.row_pitch
;
443 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
447 brw_bo_unreference(image
->bo
);
449 brw_bo_reference(mt
->bo
);
453 intel_create_image_from_name(__DRIscreen
*dri_screen
,
454 int width
, int height
, int format
,
455 int name
, int pitch
, void *loaderPrivate
)
457 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
461 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
465 if (image
->format
== MESA_FORMAT_NONE
)
468 cpp
= _mesa_get_format_bytes(image
->format
);
470 image
->width
= width
;
471 image
->height
= height
;
472 image
->pitch
= pitch
* cpp
;
473 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
479 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
485 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
486 int renderbuffer
, void *loaderPrivate
)
489 struct brw_context
*brw
= context
->driverPrivate
;
490 struct gl_context
*ctx
= &brw
->ctx
;
491 struct gl_renderbuffer
*rb
;
492 struct intel_renderbuffer
*irb
;
494 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
496 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
500 irb
= intel_renderbuffer(rb
);
501 intel_miptree_make_shareable(brw
, irb
->mt
);
502 image
= calloc(1, sizeof *image
);
506 image
->internal_format
= rb
->InternalFormat
;
507 image
->format
= rb
->Format
;
508 image
->modifier
= tiling_to_modifier(
509 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
511 image
->data
= loaderPrivate
;
512 brw_bo_unreference(image
->bo
);
513 image
->bo
= irb
->mt
->bo
;
514 brw_bo_reference(irb
->mt
->bo
);
515 image
->width
= rb
->Width
;
516 image
->height
= rb
->Height
;
517 image
->pitch
= irb
->mt
->surf
.row_pitch
;
518 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
519 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
521 rb
->NeedsFinishRenderTexture
= true;
526 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
527 unsigned texture
, int zoffset
,
533 struct brw_context
*brw
= context
->driverPrivate
;
534 struct gl_texture_object
*obj
;
535 struct intel_texture_object
*iobj
;
538 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
539 if (!obj
|| obj
->Target
!= target
) {
540 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
544 if (target
== GL_TEXTURE_CUBE_MAP
)
547 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
548 iobj
= intel_texture_object(obj
);
549 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
550 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
554 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
555 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
559 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
560 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
563 image
= calloc(1, sizeof *image
);
565 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
569 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
570 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
571 image
->modifier
= tiling_to_modifier(
572 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
573 image
->data
= loaderPrivate
;
574 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
575 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
576 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
577 if (image
->dri_format
== MESA_FORMAT_NONE
) {
578 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
583 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
588 intel_destroy_image(__DRIimage
*image
)
590 brw_bo_unreference(image
->bo
);
594 enum modifier_priority
{
595 MODIFIER_PRIORITY_INVALID
= 0,
596 MODIFIER_PRIORITY_LINEAR
,
599 MODIFIER_PRIORITY_Y_CCS
,
602 const uint64_t priority_to_modifier
[] = {
603 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
604 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
605 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
606 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
607 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
611 select_best_modifier(struct gen_device_info
*devinfo
,
613 const uint64_t *modifiers
,
614 const unsigned count
)
616 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
618 for (int i
= 0; i
< count
; i
++) {
619 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
622 switch (modifiers
[i
]) {
623 case I915_FORMAT_MOD_Y_TILED_CCS
:
624 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
626 case I915_FORMAT_MOD_Y_TILED
:
627 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
629 case I915_FORMAT_MOD_X_TILED
:
630 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
632 case DRM_FORMAT_MOD_LINEAR
:
633 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
635 case DRM_FORMAT_MOD_INVALID
:
641 return priority_to_modifier
[prio
];
645 intel_create_image_common(__DRIscreen
*dri_screen
,
646 int width
, int height
, int format
,
648 const uint64_t *modifiers
,
653 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
654 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
657 /* Callers of this may specify a modifier, or a dri usage, but not both. The
658 * newer modifier interface deprecates the older usage flags newer modifier
659 * interface deprecates the older usage flags.
661 assert(!(use
&& count
));
663 if (use
& __DRI_IMAGE_USE_CURSOR
) {
664 if (width
!= 64 || height
!= 64)
666 modifier
= DRM_FORMAT_MOD_LINEAR
;
669 if (use
& __DRI_IMAGE_USE_LINEAR
)
670 modifier
= DRM_FORMAT_MOD_LINEAR
;
672 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
674 /* User requested specific modifiers */
675 modifier
= select_best_modifier(&screen
->devinfo
, format
,
677 if (modifier
== DRM_FORMAT_MOD_INVALID
)
680 /* Historically, X-tiled was the default, and so lack of modifier means
683 modifier
= I915_FORMAT_MOD_X_TILED
;
687 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
691 const struct isl_drm_modifier_info
*mod_info
=
692 isl_drm_modifier_get_info(modifier
);
694 struct isl_surf surf
;
695 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
696 .dim
= ISL_SURF_DIM_2D
,
697 .format
= brw_isl_format_for_mesa_format(image
->format
),
704 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
705 ISL_SURF_USAGE_TEXTURE_BIT
|
706 ISL_SURF_USAGE_STORAGE_BIT
,
707 .tiling_flags
= (1 << mod_info
->tiling
));
714 struct isl_surf aux_surf
;
715 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
716 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
722 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
726 /* We request that the bufmgr zero the buffer for us for two reasons:
728 * 1) If a buffer gets re-used from the pool, we don't want to leak random
729 * garbage from our process to some other.
731 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
732 * a valid state. A CCS value of 0 indicates that the given block is
733 * in the pass-through state which is what we want.
735 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
736 surf
.size
+ aux_surf
.size
,
737 isl_tiling_to_i915_tiling(mod_info
->tiling
),
738 surf
.row_pitch
, BO_ALLOC_ZEROED
);
739 if (image
->bo
== NULL
) {
743 image
->width
= width
;
744 image
->height
= height
;
745 image
->pitch
= surf
.row_pitch
;
746 image
->modifier
= modifier
;
749 image
->aux_offset
= surf
.size
;
750 image
->aux_pitch
= aux_surf
.row_pitch
;
757 intel_create_image(__DRIscreen
*dri_screen
,
758 int width
, int height
, int format
,
762 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
767 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
768 int x0
, int y0
, int width
, int height
,
769 unsigned int flags
, int *stride
, void **map_info
)
771 struct brw_context
*brw
= NULL
;
772 struct brw_bo
*bo
= NULL
;
773 void *raw_data
= NULL
;
778 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
781 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
784 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
787 if (flags
& MAP_INTERNAL_MASK
)
790 brw
= context
->driverPrivate
;
796 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
797 raw_data
= brw_bo_map(brw
, bo
, flags
);
801 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
802 pix_bytes
= _mesa_get_format_bytes(image
->format
);
806 assert(pix_bytes
> 0);
808 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
810 brw_bo_reference(bo
);
812 *stride
= image
->pitch
;
819 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
821 struct brw_bo
*bo
= map_info
;
824 brw_bo_unreference(bo
);
828 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
829 int width
, int height
, int format
,
830 const uint64_t *modifiers
,
831 const unsigned count
,
834 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
835 modifiers
, count
, loaderPrivate
);
839 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
842 case __DRI_IMAGE_ATTRIB_STRIDE
:
843 *value
= image
->pitch
;
845 case __DRI_IMAGE_ATTRIB_HANDLE
:
846 *value
= brw_bo_export_gem_handle(image
->bo
);
848 case __DRI_IMAGE_ATTRIB_NAME
:
849 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
850 case __DRI_IMAGE_ATTRIB_FORMAT
:
851 *value
= image
->dri_format
;
853 case __DRI_IMAGE_ATTRIB_WIDTH
:
854 *value
= image
->width
;
856 case __DRI_IMAGE_ATTRIB_HEIGHT
:
857 *value
= image
->height
;
859 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
860 if (image
->planar_format
== NULL
)
862 *value
= image
->planar_format
->components
;
864 case __DRI_IMAGE_ATTRIB_FD
:
865 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
866 case __DRI_IMAGE_ATTRIB_FOURCC
:
867 return intel_lookup_fourcc(image
->dri_format
, value
);
868 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
869 if (isl_drm_modifier_has_aux(image
->modifier
)) {
870 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
872 } else if (image
->planar_format
) {
873 *value
= image
->planar_format
->nplanes
;
878 case __DRI_IMAGE_ATTRIB_OFFSET
:
879 *value
= image
->offset
;
881 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
882 *value
= (image
->modifier
& 0xffffffff);
884 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
885 *value
= ((image
->modifier
>> 32) & 0xffffffff);
894 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
895 uint32_t fourcc
, uint64_t modifier
,
896 int attrib
, uint64_t *value
)
898 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
899 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
901 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
905 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
906 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
915 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
919 image
= calloc(1, sizeof *image
);
923 brw_bo_reference(orig_image
->bo
);
924 image
->bo
= orig_image
->bo
;
925 image
->internal_format
= orig_image
->internal_format
;
926 image
->planar_format
= orig_image
->planar_format
;
927 image
->dri_format
= orig_image
->dri_format
;
928 image
->format
= orig_image
->format
;
929 image
->modifier
= orig_image
->modifier
;
930 image
->offset
= orig_image
->offset
;
931 image
->width
= orig_image
->width
;
932 image
->height
= orig_image
->height
;
933 image
->pitch
= orig_image
->pitch
;
934 image
->tile_x
= orig_image
->tile_x
;
935 image
->tile_y
= orig_image
->tile_y
;
936 image
->has_depthstencil
= orig_image
->has_depthstencil
;
937 image
->data
= loaderPrivate
;
938 image
->dma_buf_imported
= orig_image
->dma_buf_imported
;
939 image
->aux_offset
= orig_image
->aux_offset
;
940 image
->aux_pitch
= orig_image
->aux_pitch
;
942 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
943 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
949 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
951 if (use
& __DRI_IMAGE_USE_CURSOR
) {
952 if (image
->width
!= 64 || image
->height
!= 64)
960 intel_create_image_from_names(__DRIscreen
*dri_screen
,
961 int width
, int height
, int fourcc
,
962 int *names
, int num_names
,
963 int *strides
, int *offsets
,
966 const struct intel_image_format
*f
= NULL
;
970 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
973 f
= intel_image_format_lookup(fourcc
);
977 image
= intel_create_image_from_name(dri_screen
, width
, height
,
978 __DRI_IMAGE_FORMAT_NONE
,
979 names
[0], strides
[0],
985 image
->planar_format
= f
;
986 for (i
= 0; i
< f
->nplanes
; i
++) {
987 index
= f
->planes
[i
].buffer_index
;
988 image
->offsets
[index
] = offsets
[index
];
989 image
->strides
[index
] = strides
[index
];
996 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
997 int width
, int height
, int fourcc
,
998 uint64_t modifier
, int *fds
, int num_fds
,
999 int *strides
, int *offsets
,
1000 void *loaderPrivate
)
1002 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1003 const struct intel_image_format
*f
;
1008 if (fds
== NULL
|| num_fds
< 1)
1011 f
= intel_image_format_lookup(fourcc
);
1015 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1016 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1019 if (f
->nplanes
== 1)
1020 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1023 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1029 image
->width
= width
;
1030 image
->height
= height
;
1031 image
->pitch
= strides
[0];
1033 image
->planar_format
= f
;
1035 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1036 if (image
->bo
== NULL
) {
1041 /* We only support all planes from the same bo.
1042 * brw_bo_gem_create_from_prime() should return the same pointer for all
1043 * fds received here */
1044 for (i
= 1; i
< num_fds
; i
++) {
1045 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1046 brw_bo_unreference(aux
);
1047 if (aux
!= image
->bo
) {
1048 brw_bo_unreference(image
->bo
);
1054 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1055 image
->modifier
= modifier
;
1057 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1059 const struct isl_drm_modifier_info
*mod_info
=
1060 isl_drm_modifier_get_info(image
->modifier
);
1063 struct isl_surf surf
;
1064 for (i
= 0; i
< f
->nplanes
; i
++) {
1065 index
= f
->planes
[i
].buffer_index
;
1066 image
->offsets
[index
] = offsets
[index
];
1067 image
->strides
[index
] = strides
[index
];
1069 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1071 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1072 .dim
= ISL_SURF_DIM_2D
,
1073 .format
= brw_isl_format_for_mesa_format(format
),
1074 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1075 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1080 .row_pitch
= strides
[index
],
1081 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1082 ISL_SURF_USAGE_TEXTURE_BIT
|
1083 ISL_SURF_USAGE_STORAGE_BIT
,
1084 .tiling_flags
= (1 << mod_info
->tiling
));
1086 brw_bo_unreference(image
->bo
);
1091 const int end
= offsets
[index
] + surf
.size
;
1096 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1097 /* Even though we initialize surf in the loop above, we know that
1098 * anything with CCS_E will have exactly one plane so surf is properly
1099 * initialized when we get here.
1101 assert(f
->nplanes
== 1);
1103 image
->aux_offset
= offsets
[1];
1104 image
->aux_pitch
= strides
[1];
1106 /* Scanout hardware requires that the CCS be placed after the main
1107 * surface in memory. We consider any CCS that is placed any earlier in
1108 * memory to be invalid and reject it.
1110 * At some point in the future, this restriction may be relaxed if the
1111 * hardware becomes less strict but we may need a new modifier for that.
1114 if (image
->aux_offset
< size
) {
1115 brw_bo_unreference(image
->bo
);
1120 struct isl_surf aux_surf
;
1121 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1124 brw_bo_unreference(image
->bo
);
1129 const int end
= image
->aux_offset
+ aux_surf
.size
;
1133 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1136 /* Check that the requested image actually fits within the BO. 'size'
1137 * is already relative to the offsets, so we don't need to add that. */
1138 if (image
->bo
->size
== 0) {
1139 image
->bo
->size
= size
;
1140 } else if (size
> image
->bo
->size
) {
1141 brw_bo_unreference(image
->bo
);
1146 if (f
->nplanes
== 1) {
1147 image
->offset
= image
->offsets
[0];
1148 intel_image_warn_if_unaligned(image
, __func__
);
1155 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1156 int width
, int height
, int fourcc
,
1157 int *fds
, int num_fds
, int *strides
, int *offsets
,
1158 void *loaderPrivate
)
1160 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1161 DRM_FORMAT_MOD_INVALID
,
1162 fds
, num_fds
, strides
, offsets
,
1167 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1168 int width
, int height
,
1169 int fourcc
, uint64_t modifier
,
1170 int *fds
, int num_fds
,
1171 int *strides
, int *offsets
,
1172 enum __DRIYUVColorSpace yuv_color_space
,
1173 enum __DRISampleRange sample_range
,
1174 enum __DRIChromaSiting horizontal_siting
,
1175 enum __DRIChromaSiting vertical_siting
,
1177 void *loaderPrivate
)
1180 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1183 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1187 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1189 fds
, num_fds
, strides
, offsets
,
1193 * Invalid parameters and any inconsistencies between are assumed to be
1194 * checked by the caller. Therefore besides unsupported formats one can fail
1195 * only in allocation.
1198 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1202 image
->dma_buf_imported
= true;
1203 image
->yuv_color_space
= yuv_color_space
;
1204 image
->sample_range
= sample_range
;
1205 image
->horizontal_siting
= horizontal_siting
;
1206 image
->vertical_siting
= vertical_siting
;
1208 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1213 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1214 int width
, int height
, int fourcc
,
1215 int *fds
, int num_fds
,
1216 int *strides
, int *offsets
,
1217 enum __DRIYUVColorSpace yuv_color_space
,
1218 enum __DRISampleRange sample_range
,
1219 enum __DRIChromaSiting horizontal_siting
,
1220 enum __DRIChromaSiting vertical_siting
,
1222 void *loaderPrivate
)
1224 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1225 fourcc
, DRM_FORMAT_MOD_INVALID
,
1226 fds
, num_fds
, strides
, offsets
,
1236 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1237 int *formats
, int *count
)
1242 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1246 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1247 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1249 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1257 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1258 uint64_t *modifiers
,
1259 unsigned int *external_only
,
1262 struct intel_screen
*screen
= _screen
->driverPrivate
;
1263 const struct intel_image_format
*f
;
1264 int num_mods
= 0, i
;
1266 f
= intel_image_format_lookup(fourcc
);
1270 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1271 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1272 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1279 modifiers
[num_mods
- 1] = modifier
;
1280 if (num_mods
>= max
)
1284 if (external_only
!= NULL
) {
1285 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1286 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1287 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1288 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1289 external_only
[i
] = GL_TRUE
;
1292 external_only
[i
] = GL_FALSE
;
1302 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1304 int width
, height
, offset
, stride
, dri_format
, index
;
1305 const struct intel_image_format
*f
;
1308 if (parent
== NULL
) {
1310 } else if (parent
->planar_format
== NULL
) {
1312 isl_drm_modifier_has_aux(parent
->modifier
) && plane
== 1;
1316 width
= parent
->width
;
1317 height
= parent
->height
;
1318 dri_format
= parent
->dri_format
;
1319 offset
= parent
->aux_offset
;
1320 stride
= parent
->aux_pitch
;
1322 /* Planar formats don't support aux buffers/images */
1323 assert(!isl_drm_modifier_has_aux(parent
->modifier
));
1324 f
= parent
->planar_format
;
1326 if (plane
>= f
->nplanes
)
1329 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1330 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1331 dri_format
= f
->planes
[plane
].dri_format
;
1332 index
= f
->planes
[plane
].buffer_index
;
1333 offset
= parent
->offsets
[index
];
1334 stride
= parent
->strides
[index
];
1336 if (offset
+ height
* stride
> parent
->bo
->size
) {
1337 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1342 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1346 image
->bo
= parent
->bo
;
1347 brw_bo_reference(parent
->bo
);
1348 image
->modifier
= parent
->modifier
;
1350 image
->width
= width
;
1351 image
->height
= height
;
1352 image
->pitch
= stride
;
1353 image
->offset
= offset
;
1355 intel_image_warn_if_unaligned(image
, __func__
);
1360 static const __DRIimageExtension intelImageExtension
= {
1361 .base
= { __DRI_IMAGE
, 16 },
1363 .createImageFromName
= intel_create_image_from_name
,
1364 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1365 .destroyImage
= intel_destroy_image
,
1366 .createImage
= intel_create_image
,
1367 .queryImage
= intel_query_image
,
1368 .dupImage
= intel_dup_image
,
1369 .validateUsage
= intel_validate_usage
,
1370 .createImageFromNames
= intel_create_image_from_names
,
1371 .fromPlanar
= intel_from_planar
,
1372 .createImageFromTexture
= intel_create_image_from_texture
,
1373 .createImageFromFds
= intel_create_image_from_fds
,
1374 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1376 .getCapabilities
= NULL
,
1377 .mapImage
= intel_map_image
,
1378 .unmapImage
= intel_unmap_image
,
1379 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1380 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1381 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1382 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1383 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1387 get_aperture_size(int fd
)
1389 struct drm_i915_gem_get_aperture aperture
;
1391 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1394 return aperture
.aper_size
;
1398 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1399 int param
, unsigned int *value
)
1401 const struct intel_screen
*const screen
=
1402 (struct intel_screen
*) dri_screen
->driverPrivate
;
1405 case __DRI2_RENDERER_VENDOR_ID
:
1408 case __DRI2_RENDERER_DEVICE_ID
:
1409 value
[0] = screen
->deviceID
;
1411 case __DRI2_RENDERER_ACCELERATED
:
1414 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1415 /* Once a batch uses more than 75% of the maximum mappable size, we
1416 * assume that there's some fragmentation, and we start doing extra
1417 * flushing, etc. That's the big cliff apps will care about.
1419 const unsigned gpu_mappable_megabytes
=
1420 screen
->aperture_threshold
/ (1024 * 1024);
1422 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1423 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1425 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1428 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1429 * (uint64_t) system_page_size
;
1431 const unsigned system_memory_megabytes
=
1432 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1434 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1437 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1440 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1443 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1445 if (brw_hw_context_set_priority(screen
->bufmgr
,
1446 0, BRW_CONTEXT_HIGH_PRIORITY
) == 0)
1447 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1448 if (brw_hw_context_set_priority(screen
->bufmgr
,
1449 0, BRW_CONTEXT_LOW_PRIORITY
) == 0)
1450 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1451 /* reset to default last, just in case */
1452 if (brw_hw_context_set_priority(screen
->bufmgr
,
1453 0, BRW_CONTEXT_MEDIUM_PRIORITY
) == 0)
1454 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1456 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1460 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1467 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1468 int param
, const char **value
)
1470 const struct intel_screen
*screen
=
1471 (struct intel_screen
*) dri_screen
->driverPrivate
;
1474 case __DRI2_RENDERER_VENDOR_ID
:
1475 value
[0] = brw_vendor_string
;
1477 case __DRI2_RENDERER_DEVICE_ID
:
1478 value
[0] = brw_get_renderer_string(screen
);
1487 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1488 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1490 .queryInteger
= brw_query_renderer_integer
,
1491 .queryString
= brw_query_renderer_string
1494 static const __DRIrobustnessExtension dri2Robustness
= {
1495 .base
= { __DRI2_ROBUSTNESS
, 1 }
1498 static const __DRIextension
*screenExtensions
[] = {
1499 &intelTexBufferExtension
.base
,
1500 &intelFenceExtension
.base
,
1501 &intelFlushExtension
.base
,
1502 &intelImageExtension
.base
,
1503 &intelRendererQueryExtension
.base
,
1504 &dri2ConfigQueryExtension
.base
,
1505 &dri2NoErrorExtension
.base
,
1509 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1510 &intelTexBufferExtension
.base
,
1511 &intelFenceExtension
.base
,
1512 &intelFlushExtension
.base
,
1513 &intelImageExtension
.base
,
1514 &intelRendererQueryExtension
.base
,
1515 &dri2ConfigQueryExtension
.base
,
1516 &dri2Robustness
.base
,
1517 &dri2NoErrorExtension
.base
,
1522 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1525 struct drm_i915_getparam gp
;
1527 memset(&gp
, 0, sizeof(gp
));
1531 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1534 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1541 intel_get_boolean(struct intel_screen
*screen
, int param
)
1544 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1548 intel_get_integer(struct intel_screen
*screen
, int param
)
1552 if (intel_get_param(screen
, param
, &value
) == 0)
1559 intelDestroyScreen(__DRIscreen
* sPriv
)
1561 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1563 brw_bufmgr_destroy(screen
->bufmgr
);
1564 driDestroyOptionInfo(&screen
->optionCache
);
1566 ralloc_free(screen
);
1567 sPriv
->driverPrivate
= NULL
;
1572 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1574 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1575 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1576 * this does not allocate GPU memory.
1579 intelCreateBuffer(__DRIscreen
*dri_screen
,
1580 __DRIdrawable
* driDrawPriv
,
1581 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1583 struct intel_renderbuffer
*rb
;
1584 struct intel_screen
*screen
= (struct intel_screen
*)
1585 dri_screen
->driverPrivate
;
1586 mesa_format rgbFormat
;
1587 unsigned num_samples
=
1588 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1593 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1597 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1599 if (screen
->winsys_msaa_samples_override
!= -1) {
1600 num_samples
= screen
->winsys_msaa_samples_override
;
1601 fb
->Visual
.samples
= num_samples
;
1604 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1605 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1606 : MESA_FORMAT_R10G10B10A2_UNORM
;
1607 } else if (mesaVis
->redBits
== 10) {
1608 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1609 : MESA_FORMAT_R10G10B10X2_UNORM
;
1610 } else if (mesaVis
->redBits
== 5) {
1611 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1612 : MESA_FORMAT_B5G6R5_UNORM
;
1613 } else if (mesaVis
->sRGBCapable
) {
1614 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1615 : MESA_FORMAT_B8G8R8A8_SRGB
;
1616 } else if (mesaVis
->alphaBits
== 0) {
1617 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1618 : MESA_FORMAT_B8G8R8X8_UNORM
;
1620 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1621 : MESA_FORMAT_B8G8R8A8_SRGB
;
1622 fb
->Visual
.sRGBCapable
= true;
1625 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1626 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1628 /* setup the hardware-based renderbuffers */
1629 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1630 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1631 rb
->need_srgb
= srgb_cap_set
;
1633 if (mesaVis
->doubleBufferMode
) {
1634 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1635 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1636 rb
->need_srgb
= srgb_cap_set
;
1640 * Assert here that the gl_config has an expected depth/stencil bit
1641 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1642 * which constructs the advertised configs.)
1644 if (mesaVis
->depthBits
== 24) {
1645 assert(mesaVis
->stencilBits
== 8);
1647 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1648 rb
= intel_create_private_renderbuffer(screen
,
1649 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1651 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1652 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1654 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1657 * Use combined depth/stencil. Note that the renderbuffer is
1658 * attached to two attachment points.
1660 rb
= intel_create_private_renderbuffer(screen
,
1661 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1663 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1664 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1667 else if (mesaVis
->depthBits
== 16) {
1668 assert(mesaVis
->stencilBits
== 0);
1669 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1671 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1674 assert(mesaVis
->depthBits
== 0);
1675 assert(mesaVis
->stencilBits
== 0);
1678 /* now add any/all software-based renderbuffers we may need */
1679 _swrast_add_soft_renderbuffers(fb
,
1680 false, /* never sw color */
1681 false, /* never sw depth */
1682 false, /* never sw stencil */
1683 mesaVis
->accumRedBits
> 0,
1684 false, /* never sw alpha */
1685 false /* never sw aux */ );
1686 driDrawPriv
->driverPrivate
= fb
;
1692 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1694 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1696 _mesa_reference_framebuffer(&fb
, NULL
);
1700 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1702 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1703 * gen10, PCI-id is enough to figure it out.
1705 assert(screen
->devinfo
.gen
>= 10);
1709 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1713 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1717 screen
->devinfo
.timestamp_frequency
= freq
;
1721 intel_detect_sseu(struct intel_screen
*screen
)
1723 assert(screen
->devinfo
.gen
>= 8);
1726 screen
->subslice_total
= -1;
1727 screen
->eu_total
= -1;
1729 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1730 &screen
->subslice_total
);
1731 if (ret
< 0 && ret
!= -EINVAL
)
1734 ret
= intel_get_param(screen
,
1735 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1736 if (ret
< 0 && ret
!= -EINVAL
)
1739 /* Without this information, we cannot get the right Braswell brandstrings,
1740 * and we have to use conservative numbers for GPGPU on many platforms, but
1741 * otherwise, things will just work.
1743 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1745 "Kernel 4.1 required to properly query GPU properties.\n");
1750 screen
->subslice_total
= -1;
1751 screen
->eu_total
= -1;
1752 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1756 intel_init_bufmgr(struct intel_screen
*screen
)
1758 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1760 if (getenv("INTEL_NO_HW") != NULL
)
1761 screen
->no_hw
= true;
1763 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1764 if (screen
->bufmgr
== NULL
) {
1765 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1766 __func__
, __LINE__
);
1770 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1771 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1779 intel_detect_swizzling(struct intel_screen
*screen
)
1781 struct brw_bo
*buffer
;
1783 uint32_t aligned_pitch
;
1784 uint32_t tiling
= I915_TILING_X
;
1785 uint32_t swizzle_mode
= 0;
1787 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1788 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1792 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1793 brw_bo_unreference(buffer
);
1795 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1802 intel_detect_timestamp(struct intel_screen
*screen
)
1804 uint64_t dummy
= 0, last
= 0;
1805 int upper
, lower
, loops
;
1807 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1808 * TIMESTAMP register being shifted and the low 32bits always zero.
1810 * More recent kernels offer an interface to read the full 36bits
1813 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1816 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1817 * upper 32bits for a rapidly changing timestamp.
1819 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1823 for (loops
= 0; loops
< 10; loops
++) {
1824 /* The TIMESTAMP should change every 80ns, so several round trips
1825 * through the kernel should be enough to advance it.
1827 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1830 upper
+= (dummy
>> 32) != (last
>> 32);
1831 if (upper
> 1) /* beware 32bit counter overflow */
1832 return 2; /* upper dword holds the low 32bits of the timestamp */
1834 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1836 return 1; /* timestamp is unshifted */
1841 /* No advancement? No timestamp! */
1846 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1848 * Some combinations of hardware and kernel versions allow this feature,
1849 * while others don't. Instead of trying to enumerate every case, just
1850 * try and write a register and see if works.
1853 intel_detect_pipelined_register(struct intel_screen
*screen
,
1854 int reg
, uint32_t expected_value
, bool reset
)
1859 struct brw_bo
*results
, *bo
;
1861 uint32_t offset
= 0;
1863 bool success
= false;
1865 /* Create a zero'ed temporary buffer for reading our results */
1866 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1867 if (results
== NULL
)
1870 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1874 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1880 /* Write the register. */
1881 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1883 *batch
++ = expected_value
;
1885 /* Save the register's value back to the buffer. */
1886 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1888 struct drm_i915_gem_relocation_entry reloc
= {
1889 .offset
= (char *) batch
- (char *) map
,
1890 .delta
= offset
* sizeof(uint32_t),
1891 .target_handle
= results
->gem_handle
,
1892 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1893 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1895 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1897 /* And afterwards clear the register */
1899 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1904 *batch
++ = MI_BATCH_BUFFER_END
;
1906 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1908 .handle
= results
->gem_handle
,
1911 .handle
= bo
->gem_handle
,
1912 .relocation_count
= 1,
1913 .relocs_ptr
= (uintptr_t) &reloc
,
1917 struct drm_i915_gem_execbuffer2 execbuf
= {
1918 .buffers_ptr
= (uintptr_t) exec_objects
,
1920 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1921 .flags
= I915_EXEC_RENDER
,
1924 /* Don't bother with error checking - if the execbuf fails, the
1925 * value won't be written and we'll just report that there's no access.
1927 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1928 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1930 /* Check whether the value got written. */
1931 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1933 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1934 brw_bo_unmap(results
);
1938 brw_bo_unreference(bo
);
1940 brw_bo_unreference(results
);
1946 intel_detect_pipelined_so(struct intel_screen
*screen
)
1948 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1950 /* Supposedly, Broadwell just works. */
1951 if (devinfo
->gen
>= 8)
1954 if (devinfo
->gen
<= 6)
1957 /* See the big explanation about command parser versions below */
1958 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1961 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1962 * statistics registers), and we already reset it to zero before using it.
1964 return intel_detect_pipelined_register(screen
,
1965 GEN7_SO_WRITE_OFFSET(0),
1971 * Return array of MSAA modes supported by the hardware. The array is
1972 * zero-terminated and sorted in decreasing order.
1975 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1977 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1978 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1979 static const int gen7_modes
[] = {8, 4, 0, -1};
1980 static const int gen6_modes
[] = {4, 0, -1};
1981 static const int gen4_modes
[] = {0, -1};
1983 if (screen
->devinfo
.gen
>= 9) {
1985 } else if (screen
->devinfo
.gen
>= 8) {
1987 } else if (screen
->devinfo
.gen
>= 7) {
1989 } else if (screen
->devinfo
.gen
== 6) {
1997 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
1999 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2000 dri_screen
->dri2
.loader
->getCapability
)
2001 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2003 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2004 dri_screen
->image
.loader
->getCapability
)
2005 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2010 static __DRIconfig
**
2011 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2013 static const mesa_format formats
[] = {
2014 MESA_FORMAT_B5G6R5_UNORM
,
2015 MESA_FORMAT_B8G8R8A8_UNORM
,
2016 MESA_FORMAT_B8G8R8X8_UNORM
,
2018 MESA_FORMAT_B8G8R8A8_SRGB
,
2020 /* For 10 bpc, 30 bit depth framebuffers. */
2021 MESA_FORMAT_B10G10R10A2_UNORM
,
2022 MESA_FORMAT_B10G10R10X2_UNORM
,
2024 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2025 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2026 * server may disagree on which format the GLXFBConfig represents,
2027 * resulting in swapped color channels.
2029 * The problem, as of 2017-05-30:
2030 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2031 * order and chooses the first __DRIconfig with the expected channel
2032 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2033 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2035 * EGL does not suffer from this problem. It correctly compares the
2036 * channel masks when matching EGLConfig to __DRIconfig.
2039 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2040 MESA_FORMAT_R8G8B8A8_UNORM
,
2042 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2043 MESA_FORMAT_R8G8B8X8_UNORM
,
2046 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
2047 static const GLenum back_buffer_modes
[] = {
2048 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2051 static const uint8_t singlesample_samples
[1] = {0};
2053 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2054 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2055 uint8_t depth_bits
[4], stencil_bits
[4];
2056 __DRIconfig
**configs
= NULL
;
2058 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2059 unsigned num_formats
;
2060 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2061 num_formats
= ARRAY_SIZE(formats
);
2063 num_formats
= ARRAY_SIZE(formats
) - 2; /* all - RGBA_ORDERING formats */
2065 /* Shall we expose 10 bpc formats? */
2066 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2067 "allow_rgb10_configs");
2069 /* Generate singlesample configs without accumulation buffer. */
2070 for (unsigned i
= 0; i
< num_formats
; i
++) {
2071 __DRIconfig
**new_configs
;
2072 int num_depth_stencil_bits
= 2;
2074 if (!allow_rgb10_configs
&&
2075 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2076 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2079 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2080 * buffer that has a different number of bits per pixel than the color
2081 * buffer, gen >= 6 supports this.
2084 stencil_bits
[0] = 0;
2086 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2088 stencil_bits
[1] = 0;
2089 if (devinfo
->gen
>= 6) {
2091 stencil_bits
[2] = 8;
2092 num_depth_stencil_bits
= 3;
2096 stencil_bits
[1] = 8;
2099 new_configs
= driCreateConfigs(formats
[i
],
2102 num_depth_stencil_bits
,
2103 back_buffer_modes
, 2,
2104 singlesample_samples
, 1,
2106 configs
= driConcatConfigs(configs
, new_configs
);
2109 /* Generate the minimum possible set of configs that include an
2110 * accumulation buffer.
2112 for (unsigned i
= 0; i
< num_formats
; i
++) {
2113 __DRIconfig
**new_configs
;
2115 if (!allow_rgb10_configs
&&
2116 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2117 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2120 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2122 stencil_bits
[0] = 0;
2125 stencil_bits
[0] = 8;
2128 new_configs
= driCreateConfigs(formats
[i
],
2129 depth_bits
, stencil_bits
, 1,
2130 back_buffer_modes
, 1,
2131 singlesample_samples
, 1,
2133 configs
= driConcatConfigs(configs
, new_configs
);
2136 /* Generate multisample configs.
2138 * This loop breaks early, and hence is a no-op, on gen < 6.
2140 * Multisample configs must follow the singlesample configs in order to
2141 * work around an X server bug present in 1.12. The X server chooses to
2142 * associate the first listed RGBA888-Z24S8 config, regardless of its
2143 * sample count, with the 32-bit depth visual used for compositing.
2145 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2146 * supported. Singlebuffer configs are not supported because no one wants
2149 for (unsigned i
= 0; i
< num_formats
; i
++) {
2150 if (devinfo
->gen
< 6)
2153 if (!allow_rgb10_configs
&&
2154 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2155 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2158 __DRIconfig
**new_configs
;
2159 const int num_depth_stencil_bits
= 2;
2160 int num_msaa_modes
= 0;
2161 const uint8_t *multisample_samples
= NULL
;
2164 stencil_bits
[0] = 0;
2166 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2168 stencil_bits
[1] = 0;
2171 stencil_bits
[1] = 8;
2174 if (devinfo
->gen
>= 9) {
2175 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2176 multisample_samples
= multisample_samples_gen9
;
2177 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2178 } else if (devinfo
->gen
== 8) {
2179 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2180 multisample_samples
= multisample_samples_gen8
;
2181 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2182 } else if (devinfo
->gen
== 7) {
2183 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2184 multisample_samples
= multisample_samples_gen7
;
2185 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2186 } else if (devinfo
->gen
== 6) {
2187 static const uint8_t multisample_samples_gen6
[] = {4};
2188 multisample_samples
= multisample_samples_gen6
;
2189 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2192 new_configs
= driCreateConfigs(formats
[i
],
2195 num_depth_stencil_bits
,
2196 back_buffer_modes
, 1,
2197 multisample_samples
,
2200 configs
= driConcatConfigs(configs
, new_configs
);
2203 if (configs
== NULL
) {
2204 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2213 set_max_gl_versions(struct intel_screen
*screen
)
2215 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2216 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2218 switch (screen
->devinfo
.gen
) {
2222 dri_screen
->max_gl_core_version
= 45;
2223 dri_screen
->max_gl_compat_version
= 30;
2224 dri_screen
->max_gl_es1_version
= 11;
2225 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2228 dri_screen
->max_gl_core_version
= 33;
2229 if (can_do_pipelined_register_writes(screen
)) {
2230 dri_screen
->max_gl_core_version
= 42;
2231 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2232 dri_screen
->max_gl_core_version
= 43;
2233 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2234 dri_screen
->max_gl_core_version
= 45;
2236 dri_screen
->max_gl_compat_version
= 30;
2237 dri_screen
->max_gl_es1_version
= 11;
2238 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2241 dri_screen
->max_gl_core_version
= 33;
2242 dri_screen
->max_gl_compat_version
= 30;
2243 dri_screen
->max_gl_es1_version
= 11;
2244 dri_screen
->max_gl_es2_version
= 30;
2248 dri_screen
->max_gl_core_version
= 0;
2249 dri_screen
->max_gl_compat_version
= 21;
2250 dri_screen
->max_gl_es1_version
= 11;
2251 dri_screen
->max_gl_es2_version
= 20;
2254 unreachable("unrecognized intel_screen::gen");
2259 * Return the revision (generally the revid field of the PCI header) of the
2263 intel_device_get_revision(int fd
)
2265 struct drm_i915_getparam gp
;
2269 memset(&gp
, 0, sizeof(gp
));
2270 gp
.param
= I915_PARAM_REVISION
;
2271 gp
.value
= &revision
;
2273 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2281 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2283 struct brw_context
*brw
= (struct brw_context
*)data
;
2286 va_start(args
, fmt
);
2288 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2289 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2290 MESA_DEBUG_TYPE_OTHER
,
2291 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2296 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2298 struct brw_context
*brw
= (struct brw_context
*)data
;
2301 va_start(args
, fmt
);
2303 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2305 va_copy(args_copy
, args
);
2306 vfprintf(stderr
, fmt
, args_copy
);
2310 if (brw
->perf_debug
) {
2312 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2313 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2314 MESA_DEBUG_TYPE_PERFORMANCE
,
2315 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2321 parse_devid_override(const char *devid_override
)
2323 static const struct {
2343 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2344 if (!strcmp(name_map
[i
].name
, devid_override
))
2345 return name_map
[i
].pci_id
;
2348 return strtol(devid_override
, NULL
, 0);
2352 * Get the PCI ID for the device. This can be overridden by setting the
2353 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2355 * Returns -1 on ioctl failure.
2358 get_pci_device_id(struct intel_screen
*screen
)
2360 if (geteuid() == getuid()) {
2361 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2362 if (devid_override
) {
2363 screen
->no_hw
= true;
2364 return parse_devid_override(devid_override
);
2368 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2372 * This is the driver specific part of the createNewScreen entry point.
2373 * Called when using DRI2.
2375 * \return the struct gl_config supported by this driver
2378 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2380 struct intel_screen
*screen
;
2382 if (dri_screen
->image
.loader
) {
2383 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2384 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2386 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2387 "support required\n");
2391 /* Allocate the private area */
2392 screen
= rzalloc(NULL
, struct intel_screen
);
2394 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2397 /* parse information in __driConfigOptions */
2398 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
2400 screen
->driScrnPriv
= dri_screen
;
2401 dri_screen
->driverPrivate
= (void *) screen
;
2403 screen
->deviceID
= get_pci_device_id(screen
);
2405 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2408 if (!intel_init_bufmgr(screen
))
2411 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2413 brw_process_intel_debug_variable();
2415 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2417 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2418 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2421 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2422 /* Theorectically unlimited! At least for individual objects...
2424 * Currently the entire (global) address space for all GTT maps is
2425 * limited to 64bits. That is all objects on the system that are
2426 * setup for GTT mmapping must fit within 64bits. An attempt to use
2427 * one that exceeds the limit with fail in brw_bo_map_gtt().
2429 * Long before we hit that limit, we will be practically limited by
2430 * that any single object must fit in physical memory (RAM). The upper
2431 * limit on the CPU's address space is currently 48bits (Skylake), of
2432 * which only 39bits can be physical memory. (The GPU itself also has
2433 * a 48bit addressable virtual space.) We can fit over 32 million
2434 * objects of the current maximum allocable size before running out
2437 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2439 /* Estimate the size of the mappable aperture into the GTT. There's an
2440 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2441 * It turns out it's basically always 256MB, though some ancient hardware
2444 uint32_t gtt_size
= 256 * 1024 * 1024;
2446 /* We don't want to map two objects such that a memcpy between them would
2447 * just fault one mapping in and then the other over and over forever. So
2448 * we would need to divide the GTT size by 2. Additionally, some GTT is
2449 * taken up by things like the framebuffer and the ringbuffer and such, so
2450 * be more conservative.
2452 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2455 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2457 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2458 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2460 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2461 screen
->hw_has_swizzling
);
2463 if (devinfo
->gen
>= 10)
2464 intel_cs_timestamp_frequency(screen
);
2466 /* GENs prior to 8 do not support EU/Subslice info */
2467 if (devinfo
->gen
>= 8) {
2468 intel_detect_sseu(screen
);
2469 } else if (devinfo
->gen
== 7) {
2470 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2473 /* Gen7-7.5 kernel requirements / command parser saga:
2476 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2478 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2479 * all batches secure, allowing them to use any feature with no checking.
2480 * This is effectively equivalent to a command parser version of
2481 * \infinity - everything is possible.
2483 * The command parser does not exist, and querying the version will
2487 * The kernel enables the command parser by default, for systems with
2488 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2489 * hardware checker is still enabled, so Haswell and Baytrail cannot
2492 * Ivybridge goes from "everything is possible" to "only what the
2493 * command parser allows" (if the user boots with i915.cmd_parser=0,
2494 * then everything is possible again). We can only safely use features
2495 * allowed by the supported command parser version.
2497 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2498 * implemented by the kernel, even if it's turned off. So, checking
2499 * for version > 0 does not mean that you can write registers. We have
2500 * to try it and see. The version does, however, indicate the age of
2503 * Instead of matching the hardware checker's behavior of converting
2504 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2505 * -EINVAL, making it dangerous to try and use privileged features.
2507 * Effective command parser versions:
2508 * - Haswell: 0 (reporting 1, writes don't work)
2509 * - Baytrail: 0 (reporting 1, writes don't work)
2510 * - Ivybridge: 1 (enabled) or infinite (disabled)
2513 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2514 * effectively version 1 (enabled) or infinite (disabled).
2516 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2517 * Command parser v2 supports predicate writes.
2519 * - Haswell: 0 (reporting 1, writes don't work)
2520 * - Baytrail: 2 (enabled) or infinite (disabled)
2521 * - Ivybridge: 2 (enabled) or infinite (disabled)
2523 * So version >= 2 is enough to know that Ivybridge and Baytrail
2524 * will work. Haswell still can't do anything.
2526 * - v4.0: Version 3 happened. Largely not relevant.
2528 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2529 * L3 config registers are properly saved and restored as part
2530 * of the hardware context. We can approximately detect this point
2531 * in time by checking if I915_PARAM_REVISION is recognized - it
2532 * landed in a later commit, but in the same release cycle.
2534 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2535 * Command parser finally gains secure batch promotion. On Haswell,
2536 * the hardware checker gets disabled, which finally allows it to do
2537 * privileged commands.
2539 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2540 * - Haswell: 3 (enabled) or 0 (disabled)
2541 * - Baytrail: 3 (enabled) or infinite (disabled)
2542 * - Ivybridge: 3 (enabled) or infinite (disabled)
2544 * Unfortunately, detecting this point in time is tricky, because
2545 * no version bump happened when this important change occurred.
2546 * On Haswell, if we can write any register, then the kernel is at
2547 * least this new, and we can start trusting the version number.
2549 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2550 * Command parser reaches version 4, allowing access to Haswell
2551 * atomic scratch and chicken3 registers. If version >= 4, we know
2552 * the kernel is new enough to support privileged features on all
2553 * hardware. However, the user might have disabled it...and the
2554 * kernel will still report version 4. So we still have to guess
2557 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2558 * Command parser v5 whitelists indirect compute shader dispatch
2559 * registers, needed for OpenGL 4.3 and later.
2562 * Command parser v7 lets us use MI_MATH on Haswell.
2564 * Additionally, the kernel begins reporting version 0 when
2565 * the command parser is disabled, allowing us to skip the
2566 * guess-and-check step on Haswell. Unfortunately, this also
2567 * means that we can no longer use it as an indicator of the
2568 * age of the kernel.
2570 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2571 &screen
->cmd_parser_version
) < 0) {
2572 /* Command parser does not exist - getparam is unrecognized */
2573 screen
->cmd_parser_version
= 0;
2576 /* Kernel 4.13 retuired for exec object capture */
2577 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2578 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2581 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2582 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2585 if (!intel_detect_pipelined_so(screen
)) {
2586 /* We can't do anything, so the effective version is 0. */
2587 screen
->cmd_parser_version
= 0;
2589 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2592 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2593 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2595 /* Haswell requires command parser version 4 in order to have L3
2596 * atomic scratch1 and chicken3 bits
2598 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2599 screen
->kernel_features
|=
2600 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2603 /* Haswell requires command parser version 6 in order to write to the
2604 * MI_MATH GPR registers, and version 7 in order to use
2605 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2607 if (devinfo
->gen
>= 8 ||
2608 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2609 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2612 /* Gen7 needs at least command parser version 5 to support compute */
2613 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2614 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2616 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2618 screen
->winsys_msaa_samples_override
=
2619 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2620 printf("Forcing winsys sample count to %d\n",
2621 screen
->winsys_msaa_samples_override
);
2623 screen
->winsys_msaa_samples_override
= -1;
2626 set_max_gl_versions(screen
);
2628 /* Notification of GPU resets requires hardware contexts and a kernel new
2629 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2630 * supported, calling it with a context of 0 will either generate EPERM or
2631 * no error. If the ioctl is not supported, it always generate EINVAL.
2632 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2633 * extension to the loader.
2635 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2637 if (devinfo
->gen
>= 6) {
2638 struct drm_i915_reset_stats stats
;
2639 memset(&stats
, 0, sizeof(stats
));
2641 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2643 screen
->has_context_reset_notification
=
2644 (ret
!= -1 || errno
!= EINVAL
);
2647 dri_screen
->extensions
= !screen
->has_context_reset_notification
2648 ? screenExtensions
: intelRobustScreenExtensions
;
2650 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2651 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2652 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2653 screen
->compiler
->constant_buffer_0_is_relative
= true;
2654 screen
->compiler
->supports_pull_constants
= true;
2656 screen
->has_exec_fence
=
2657 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2659 intel_screen_init_surface_formats(screen
);
2661 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2662 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2664 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2665 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2666 fprintf(stderr
, " - User priority sorting enabled\n");
2667 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2668 fprintf(stderr
, " - Preemption enabled\n");
2672 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2675 struct intel_buffer
{
2680 static __DRIbuffer
*
2681 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2682 unsigned attachment
, unsigned format
,
2683 int width
, int height
)
2685 struct intel_buffer
*intelBuffer
;
2686 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2688 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2689 attachment
== __DRI_BUFFER_BACK_LEFT
);
2691 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2692 if (intelBuffer
== NULL
)
2695 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2696 * supports Y tiled and compressed buffers, but there is no way to plumb that
2697 * through to here. */
2699 int cpp
= format
/ 8;
2700 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2701 "intelAllocateBuffer",
2705 I915_TILING_X
, &pitch
,
2708 if (intelBuffer
->bo
== NULL
) {
2713 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2715 intelBuffer
->base
.attachment
= attachment
;
2716 intelBuffer
->base
.cpp
= cpp
;
2717 intelBuffer
->base
.pitch
= pitch
;
2719 return &intelBuffer
->base
;
2723 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2725 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2727 brw_bo_unreference(intelBuffer
->bo
);
2731 static const struct __DriverAPIRec brw_driver_api
= {
2732 .InitScreen
= intelInitScreen2
,
2733 .DestroyScreen
= intelDestroyScreen
,
2734 .CreateContext
= brwCreateContext
,
2735 .DestroyContext
= intelDestroyContext
,
2736 .CreateBuffer
= intelCreateBuffer
,
2737 .DestroyBuffer
= intelDestroyBuffer
,
2738 .MakeCurrent
= intelMakeCurrent
,
2739 .UnbindContext
= intelUnbindContext
,
2740 .AllocateBuffer
= intelAllocateBuffer
,
2741 .ReleaseBuffer
= intelReleaseBuffer
2744 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2745 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2746 .vtable
= &brw_driver_api
,
2749 static const __DRIextension
*brw_driver_extensions
[] = {
2750 &driCoreExtension
.base
,
2751 &driImageDriverExtension
.base
,
2752 &driDRI2Extension
.base
,
2754 &brw_config_options
.base
,
2758 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2760 globalDriverAPI
= &brw_driver_api
;
2762 return brw_driver_extensions
;