2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "compiler/nir/nir.h"
45 #ifndef DRM_FORMAT_MOD_INVALID
46 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
49 #ifndef DRM_FORMAT_MOD_LINEAR
50 #define DRM_FORMAT_MOD_LINEAR 0
53 static const __DRIconfigOptionsExtension brw_config_options
= {
54 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
57 DRI_CONF_SECTION_PERFORMANCE
58 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
59 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
60 * DRI_CONF_BO_REUSE_ALL
62 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
63 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
64 DRI_CONF_ENUM(0, "Disable buffer object reuse")
65 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_PRECISE_TRIG("false")
75 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
76 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
77 "given integer. If negative, then do not clamp.")
81 DRI_CONF_SECTION_DEBUG
82 DRI_CONF_NO_RAST("false")
83 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
84 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
85 DRI_CONF_DISABLE_THROTTLING("false")
86 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
87 DRI_CONF_FORCE_GLSL_VERSION(0)
88 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
89 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
90 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
91 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
92 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
95 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
96 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
100 DRI_CONF_SECTION_MISCELLANEOUS
101 DRI_CONF_GLSL_ZERO_INIT("false")
106 #include "intel_batchbuffer.h"
107 #include "intel_buffers.h"
108 #include "brw_bufmgr.h"
109 #include "intel_fbo.h"
110 #include "intel_mipmap_tree.h"
111 #include "intel_screen.h"
112 #include "intel_tex.h"
113 #include "intel_image.h"
115 #include "brw_context.h"
117 #include "i915_drm.h"
120 * For debugging purposes, this returns a time in seconds.
127 clock_gettime(CLOCK_MONOTONIC
, &tp
);
129 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
132 static const __DRItexBufferExtension intelTexBufferExtension
= {
133 .base
= { __DRI_TEX_BUFFER
, 3 },
135 .setTexBuffer
= intelSetTexBuffer
,
136 .setTexBuffer2
= intelSetTexBuffer2
,
137 .releaseTexBuffer
= NULL
,
141 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
142 __DRIdrawable
*dPriv
,
144 enum __DRI2throttleReason reason
)
146 struct brw_context
*brw
= cPriv
->driverPrivate
;
151 struct gl_context
*ctx
= &brw
->ctx
;
153 FLUSH_VERTICES(ctx
, 0);
155 if (flags
& __DRI2_FLUSH_DRAWABLE
)
156 intel_resolve_for_dri2_flush(brw
, dPriv
);
158 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
159 brw
->need_swap_throttle
= true;
160 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
161 brw
->need_flush_throttle
= true;
163 intel_batchbuffer_flush(brw
);
167 * Provides compatibility with loaders that only support the older (version
168 * 1-3) flush interface.
170 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
173 intel_dri2_flush(__DRIdrawable
*drawable
)
175 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
176 __DRI2_FLUSH_DRAWABLE
,
177 __DRI2_THROTTLE_SWAPBUFFER
);
180 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
181 .base
= { __DRI2_FLUSH
, 4 },
183 .flush
= intel_dri2_flush
,
184 .invalidate
= dri2InvalidateDrawable
,
185 .flush_with_flags
= intel_dri2_flush_with_flags
,
188 static struct intel_image_format intel_image_formats
[] = {
189 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
192 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
195 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
198 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
201 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
204 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
207 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
210 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
213 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
216 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
219 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
222 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
225 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
227 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
230 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
232 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
237 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
242 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
276 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
280 /* For YUYV buffers, we set up two overlapping DRI images and treat
281 * them as planar buffers in the compositors. Plane 0 is GR88 and
282 * samples YU or YV pairs and places Y into the R component, while
283 * plane 1 is ARGB and samples YUYV clusters and places pairs and
284 * places U into the G component and V into A. This lets the
285 * texture sampler interpolate the Y components correctly when
286 * sampling from plane 0, and interpolate U and V correctly when
287 * sampling from plane 1. */
288 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
289 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
290 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
293 static const struct {
296 } tiling_modifier_map
[] = {
297 { .tiling
= I915_TILING_NONE
, .modifier
= DRM_FORMAT_MOD_LINEAR
},
298 { .tiling
= I915_TILING_X
, .modifier
= I915_FORMAT_MOD_X_TILED
},
299 { .tiling
= I915_TILING_Y
, .modifier
= I915_FORMAT_MOD_Y_TILED
},
303 modifier_to_tiling(uint64_t modifier
)
307 for (i
= 0; i
< ARRAY_SIZE(tiling_modifier_map
); i
++) {
308 if (tiling_modifier_map
[i
].modifier
== modifier
)
309 return tiling_modifier_map
[i
].tiling
;
312 assert(0 && "modifier_to_tiling should only receive known modifiers");
317 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
319 uint32_t tiling
, swizzle
;
320 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
322 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
323 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
324 func
, image
->offset
);
328 static struct intel_image_format
*
329 intel_image_format_lookup(int fourcc
)
331 struct intel_image_format
*f
= NULL
;
333 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
334 if (intel_image_formats
[i
].fourcc
== fourcc
) {
335 f
= &intel_image_formats
[i
];
343 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
345 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
346 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
347 *fourcc
= intel_image_formats
[i
].fourcc
;
355 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
360 image
= calloc(1, sizeof *image
);
364 image
->screen
= screen
;
365 image
->dri_format
= dri_format
;
368 image
->format
= driImageFormatToGLFormat(dri_format
);
369 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
370 image
->format
== MESA_FORMAT_NONE
) {
375 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
376 image
->data
= loaderPrivate
;
382 * Sets up a DRIImage structure to point to a slice out of a miptree.
385 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
386 struct intel_mipmap_tree
*mt
, GLuint level
,
389 intel_miptree_make_shareable(brw
, mt
);
391 intel_miptree_check_level_layer(mt
, level
, zoffset
);
393 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
394 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
395 image
->pitch
= mt
->pitch
;
397 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
401 brw_bo_unreference(image
->bo
);
403 brw_bo_reference(mt
->bo
);
407 intel_create_image_from_name(__DRIscreen
*dri_screen
,
408 int width
, int height
, int format
,
409 int name
, int pitch
, void *loaderPrivate
)
411 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
415 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
419 if (image
->format
== MESA_FORMAT_NONE
)
422 cpp
= _mesa_get_format_bytes(image
->format
);
424 image
->width
= width
;
425 image
->height
= height
;
426 image
->pitch
= pitch
* cpp
;
427 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
438 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
439 int renderbuffer
, void *loaderPrivate
)
442 struct brw_context
*brw
= context
->driverPrivate
;
443 struct gl_context
*ctx
= &brw
->ctx
;
444 struct gl_renderbuffer
*rb
;
445 struct intel_renderbuffer
*irb
;
447 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
449 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
453 irb
= intel_renderbuffer(rb
);
454 intel_miptree_make_shareable(brw
, irb
->mt
);
455 image
= calloc(1, sizeof *image
);
459 image
->internal_format
= rb
->InternalFormat
;
460 image
->format
= rb
->Format
;
462 image
->data
= loaderPrivate
;
463 brw_bo_unreference(image
->bo
);
464 image
->bo
= irb
->mt
->bo
;
465 brw_bo_reference(irb
->mt
->bo
);
466 image
->width
= rb
->Width
;
467 image
->height
= rb
->Height
;
468 image
->pitch
= irb
->mt
->pitch
;
469 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
470 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
472 rb
->NeedsFinishRenderTexture
= true;
477 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
478 unsigned texture
, int zoffset
,
484 struct brw_context
*brw
= context
->driverPrivate
;
485 struct gl_texture_object
*obj
;
486 struct intel_texture_object
*iobj
;
489 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
490 if (!obj
|| obj
->Target
!= target
) {
491 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
495 if (target
== GL_TEXTURE_CUBE_MAP
)
498 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
499 iobj
= intel_texture_object(obj
);
500 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
501 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
505 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
506 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
510 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
511 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
514 image
= calloc(1, sizeof *image
);
516 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
520 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
521 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
522 image
->data
= loaderPrivate
;
523 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
524 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
525 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
526 if (image
->dri_format
== MESA_FORMAT_NONE
) {
527 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
532 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
537 intel_destroy_image(__DRIimage
*image
)
539 brw_bo_unreference(image
->bo
);
543 enum modifier_priority
{
544 MODIFIER_PRIORITY_INVALID
= 0,
545 MODIFIER_PRIORITY_LINEAR
,
550 const uint64_t priority_to_modifier
[] = {
551 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
552 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
553 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
554 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
558 select_best_modifier(struct gen_device_info
*devinfo
,
559 const uint64_t *modifiers
,
560 const unsigned count
)
562 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
564 for (int i
= 0; i
< count
; i
++) {
565 switch (modifiers
[i
]) {
566 case I915_FORMAT_MOD_Y_TILED
:
567 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
569 case I915_FORMAT_MOD_X_TILED
:
570 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
572 case DRM_FORMAT_MOD_LINEAR
:
573 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
575 case DRM_FORMAT_MOD_INVALID
:
581 return priority_to_modifier
[prio
];
585 intel_create_image_common(__DRIscreen
*dri_screen
,
586 int width
, int height
, int format
,
588 const uint64_t *modifiers
,
593 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
597 /* Callers of this may specify a modifier, or a dri usage, but not both. The
598 * newer modifier interface deprecates the older usage flags newer modifier
599 * interface deprecates the older usage flags.
601 assert(!(use
&& count
));
603 uint64_t modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
604 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
605 /* User requested specific modifiers, none of which work */
609 /* Historically, X-tiled was the default, and so lack of modifier means
612 tiling
= I915_TILING_X
;
614 /* select_best_modifier has found a modifier we support */
615 tiling
= modifier_to_tiling(modifier
);
618 if (use
& __DRI_IMAGE_USE_CURSOR
) {
619 if (width
!= 64 || height
!= 64)
621 tiling
= I915_TILING_NONE
;
624 if (use
& __DRI_IMAGE_USE_LINEAR
)
625 tiling
= I915_TILING_NONE
;
627 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
631 cpp
= _mesa_get_format_bytes(image
->format
);
632 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
633 width
, height
, cpp
, tiling
,
635 if (image
->bo
== NULL
) {
639 image
->width
= width
;
640 image
->height
= height
;
641 image
->modifier
= modifier
;
647 intel_create_image(__DRIscreen
*dri_screen
,
648 int width
, int height
, int format
,
652 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
657 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
658 int width
, int height
, int format
,
659 const uint64_t *modifiers
,
660 const unsigned count
,
663 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
664 modifiers
, count
, loaderPrivate
);
668 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
671 case __DRI_IMAGE_ATTRIB_STRIDE
:
672 *value
= image
->pitch
;
674 case __DRI_IMAGE_ATTRIB_HANDLE
:
675 *value
= image
->bo
->gem_handle
;
677 case __DRI_IMAGE_ATTRIB_NAME
:
678 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
679 case __DRI_IMAGE_ATTRIB_FORMAT
:
680 *value
= image
->dri_format
;
682 case __DRI_IMAGE_ATTRIB_WIDTH
:
683 *value
= image
->width
;
685 case __DRI_IMAGE_ATTRIB_HEIGHT
:
686 *value
= image
->height
;
688 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
689 if (image
->planar_format
== NULL
)
691 *value
= image
->planar_format
->components
;
693 case __DRI_IMAGE_ATTRIB_FD
:
694 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
695 case __DRI_IMAGE_ATTRIB_FOURCC
:
696 return intel_lookup_fourcc(image
->dri_format
, value
);
697 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
700 case __DRI_IMAGE_ATTRIB_OFFSET
:
701 *value
= image
->offset
;
703 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
704 *value
= (image
->modifier
& 0xffffffff);
706 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
707 *value
= ((image
->modifier
>> 32) & 0xffffffff);
716 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
720 image
= calloc(1, sizeof *image
);
724 brw_bo_reference(orig_image
->bo
);
725 image
->bo
= orig_image
->bo
;
726 image
->internal_format
= orig_image
->internal_format
;
727 image
->planar_format
= orig_image
->planar_format
;
728 image
->dri_format
= orig_image
->dri_format
;
729 image
->format
= orig_image
->format
;
730 image
->offset
= orig_image
->offset
;
731 image
->width
= orig_image
->width
;
732 image
->height
= orig_image
->height
;
733 image
->pitch
= orig_image
->pitch
;
734 image
->tile_x
= orig_image
->tile_x
;
735 image
->tile_y
= orig_image
->tile_y
;
736 image
->has_depthstencil
= orig_image
->has_depthstencil
;
737 image
->data
= loaderPrivate
;
739 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
740 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
746 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
748 if (use
& __DRI_IMAGE_USE_CURSOR
) {
749 if (image
->width
!= 64 || image
->height
!= 64)
757 intel_create_image_from_names(__DRIscreen
*dri_screen
,
758 int width
, int height
, int fourcc
,
759 int *names
, int num_names
,
760 int *strides
, int *offsets
,
763 struct intel_image_format
*f
= NULL
;
767 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
770 f
= intel_image_format_lookup(fourcc
);
774 image
= intel_create_image_from_name(dri_screen
, width
, height
,
775 __DRI_IMAGE_FORMAT_NONE
,
776 names
[0], strides
[0],
782 image
->planar_format
= f
;
783 for (i
= 0; i
< f
->nplanes
; i
++) {
784 index
= f
->planes
[i
].buffer_index
;
785 image
->offsets
[index
] = offsets
[index
];
786 image
->strides
[index
] = strides
[index
];
793 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
794 int width
, int height
, int fourcc
,
795 int *fds
, int num_fds
, int *strides
, int *offsets
,
798 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
799 struct intel_image_format
*f
;
803 if (fds
== NULL
|| num_fds
< 1)
806 /* We only support all planes from the same bo */
807 for (i
= 0; i
< num_fds
; i
++)
808 if (fds
[0] != fds
[i
])
811 f
= intel_image_format_lookup(fourcc
);
816 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
819 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
825 image
->width
= width
;
826 image
->height
= height
;
827 image
->pitch
= strides
[0];
829 image
->planar_format
= f
;
831 for (i
= 0; i
< f
->nplanes
; i
++) {
832 index
= f
->planes
[i
].buffer_index
;
833 image
->offsets
[index
] = offsets
[index
];
834 image
->strides
[index
] = strides
[index
];
836 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
837 const int end
= offsets
[index
] + plane_height
* strides
[index
];
842 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
,
844 if (image
->bo
== NULL
) {
849 if (f
->nplanes
== 1) {
850 image
->offset
= image
->offsets
[0];
851 intel_image_warn_if_unaligned(image
, __func__
);
858 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
859 int width
, int height
, int fourcc
,
860 int *fds
, int num_fds
,
861 int *strides
, int *offsets
,
862 enum __DRIYUVColorSpace yuv_color_space
,
863 enum __DRISampleRange sample_range
,
864 enum __DRIChromaSiting horizontal_siting
,
865 enum __DRIChromaSiting vertical_siting
,
870 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
873 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
877 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
878 num_fds
, strides
, offsets
,
882 * Invalid parameters and any inconsistencies between are assumed to be
883 * checked by the caller. Therefore besides unsupported formats one can fail
884 * only in allocation.
887 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
891 image
->dma_buf_imported
= true;
892 image
->yuv_color_space
= yuv_color_space
;
893 image
->sample_range
= sample_range
;
894 image
->horizontal_siting
= horizontal_siting
;
895 image
->vertical_siting
= vertical_siting
;
897 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
902 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
904 int width
, height
, offset
, stride
, dri_format
, index
;
905 struct intel_image_format
*f
;
908 if (parent
== NULL
|| parent
->planar_format
== NULL
)
911 f
= parent
->planar_format
;
913 if (plane
>= f
->nplanes
)
916 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
917 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
918 dri_format
= f
->planes
[plane
].dri_format
;
919 index
= f
->planes
[plane
].buffer_index
;
920 offset
= parent
->offsets
[index
];
921 stride
= parent
->strides
[index
];
923 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
927 if (offset
+ height
* stride
> parent
->bo
->size
) {
928 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
933 image
->bo
= parent
->bo
;
934 brw_bo_reference(parent
->bo
);
936 image
->width
= width
;
937 image
->height
= height
;
938 image
->pitch
= stride
;
939 image
->offset
= offset
;
941 intel_image_warn_if_unaligned(image
, __func__
);
946 static const __DRIimageExtension intelImageExtension
= {
947 .base
= { __DRI_IMAGE
, 14 },
949 .createImageFromName
= intel_create_image_from_name
,
950 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
951 .destroyImage
= intel_destroy_image
,
952 .createImage
= intel_create_image
,
953 .queryImage
= intel_query_image
,
954 .dupImage
= intel_dup_image
,
955 .validateUsage
= intel_validate_usage
,
956 .createImageFromNames
= intel_create_image_from_names
,
957 .fromPlanar
= intel_from_planar
,
958 .createImageFromTexture
= intel_create_image_from_texture
,
959 .createImageFromFds
= intel_create_image_from_fds
,
960 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
962 .getCapabilities
= NULL
,
965 .createImageWithModifiers
= intel_create_image_with_modifiers
,
969 get_aperture_size(int fd
)
971 struct drm_i915_gem_get_aperture aperture
;
973 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
976 return aperture
.aper_size
;
980 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
981 int param
, unsigned int *value
)
983 const struct intel_screen
*const screen
=
984 (struct intel_screen
*) dri_screen
->driverPrivate
;
987 case __DRI2_RENDERER_VENDOR_ID
:
990 case __DRI2_RENDERER_DEVICE_ID
:
991 value
[0] = screen
->deviceID
;
993 case __DRI2_RENDERER_ACCELERATED
:
996 case __DRI2_RENDERER_VIDEO_MEMORY
: {
997 /* Once a batch uses more than 75% of the maximum mappable size, we
998 * assume that there's some fragmentation, and we start doing extra
999 * flushing, etc. That's the big cliff apps will care about.
1001 const unsigned gpu_mappable_megabytes
=
1002 screen
->aperture_threshold
/ (1024 * 1024);
1004 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1005 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1007 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1010 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1011 * (uint64_t) system_page_size
;
1013 const unsigned system_memory_megabytes
=
1014 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1016 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1019 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1022 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1026 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1033 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1034 int param
, const char **value
)
1036 const struct intel_screen
*screen
=
1037 (struct intel_screen
*) dri_screen
->driverPrivate
;
1040 case __DRI2_RENDERER_VENDOR_ID
:
1041 value
[0] = brw_vendor_string
;
1043 case __DRI2_RENDERER_DEVICE_ID
:
1044 value
[0] = brw_get_renderer_string(screen
);
1053 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1054 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1056 .queryInteger
= brw_query_renderer_integer
,
1057 .queryString
= brw_query_renderer_string
1060 static const __DRIrobustnessExtension dri2Robustness
= {
1061 .base
= { __DRI2_ROBUSTNESS
, 1 }
1064 static const __DRIextension
*screenExtensions
[] = {
1065 &intelTexBufferExtension
.base
,
1066 &intelFenceExtension
.base
,
1067 &intelFlushExtension
.base
,
1068 &intelImageExtension
.base
,
1069 &intelRendererQueryExtension
.base
,
1070 &dri2ConfigQueryExtension
.base
,
1074 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1075 &intelTexBufferExtension
.base
,
1076 &intelFenceExtension
.base
,
1077 &intelFlushExtension
.base
,
1078 &intelImageExtension
.base
,
1079 &intelRendererQueryExtension
.base
,
1080 &dri2ConfigQueryExtension
.base
,
1081 &dri2Robustness
.base
,
1086 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1089 struct drm_i915_getparam gp
;
1091 memset(&gp
, 0, sizeof(gp
));
1095 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1098 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1105 intel_get_boolean(struct intel_screen
*screen
, int param
)
1108 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1112 intel_get_integer(struct intel_screen
*screen
, int param
)
1116 if (intel_get_param(screen
, param
, &value
) == 0)
1123 intelDestroyScreen(__DRIscreen
* sPriv
)
1125 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1127 brw_bufmgr_destroy(screen
->bufmgr
);
1128 driDestroyOptionInfo(&screen
->optionCache
);
1130 ralloc_free(screen
);
1131 sPriv
->driverPrivate
= NULL
;
1136 * This is called when we need to set up GL rendering to a new X window.
1139 intelCreateBuffer(__DRIscreen
*dri_screen
,
1140 __DRIdrawable
* driDrawPriv
,
1141 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1143 struct intel_renderbuffer
*rb
;
1144 struct intel_screen
*screen
= (struct intel_screen
*)
1145 dri_screen
->driverPrivate
;
1146 mesa_format rgbFormat
;
1147 unsigned num_samples
=
1148 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1149 struct gl_framebuffer
*fb
;
1154 fb
= CALLOC_STRUCT(gl_framebuffer
);
1158 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1160 if (screen
->winsys_msaa_samples_override
!= -1) {
1161 num_samples
= screen
->winsys_msaa_samples_override
;
1162 fb
->Visual
.samples
= num_samples
;
1165 if (mesaVis
->redBits
== 5) {
1166 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1167 : MESA_FORMAT_B5G6R5_UNORM
;
1168 } else if (mesaVis
->sRGBCapable
) {
1169 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1170 : MESA_FORMAT_B8G8R8A8_SRGB
;
1171 } else if (mesaVis
->alphaBits
== 0) {
1172 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1173 : MESA_FORMAT_B8G8R8X8_UNORM
;
1175 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1176 : MESA_FORMAT_B8G8R8A8_SRGB
;
1177 fb
->Visual
.sRGBCapable
= true;
1180 /* setup the hardware-based renderbuffers */
1181 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1182 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1184 if (mesaVis
->doubleBufferMode
) {
1185 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1186 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1190 * Assert here that the gl_config has an expected depth/stencil bit
1191 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1192 * which constructs the advertised configs.)
1194 if (mesaVis
->depthBits
== 24) {
1195 assert(mesaVis
->stencilBits
== 8);
1197 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1198 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1200 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1201 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1203 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1206 * Use combined depth/stencil. Note that the renderbuffer is
1207 * attached to two attachment points.
1209 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1211 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1212 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1215 else if (mesaVis
->depthBits
== 16) {
1216 assert(mesaVis
->stencilBits
== 0);
1217 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1219 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1222 assert(mesaVis
->depthBits
== 0);
1223 assert(mesaVis
->stencilBits
== 0);
1226 /* now add any/all software-based renderbuffers we may need */
1227 _swrast_add_soft_renderbuffers(fb
,
1228 false, /* never sw color */
1229 false, /* never sw depth */
1230 false, /* never sw stencil */
1231 mesaVis
->accumRedBits
> 0,
1232 false, /* never sw alpha */
1233 false /* never sw aux */ );
1234 driDrawPriv
->driverPrivate
= fb
;
1240 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1242 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1244 _mesa_reference_framebuffer(&fb
, NULL
);
1248 intel_detect_sseu(struct intel_screen
*screen
)
1250 assert(screen
->devinfo
.gen
>= 8);
1253 screen
->subslice_total
= -1;
1254 screen
->eu_total
= -1;
1256 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1257 &screen
->subslice_total
);
1258 if (ret
< 0 && ret
!= -EINVAL
)
1261 ret
= intel_get_param(screen
,
1262 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1263 if (ret
< 0 && ret
!= -EINVAL
)
1266 /* Without this information, we cannot get the right Braswell brandstrings,
1267 * and we have to use conservative numbers for GPGPU on many platforms, but
1268 * otherwise, things will just work.
1270 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1272 "Kernel 4.1 required to properly query GPU properties.\n");
1277 screen
->subslice_total
= -1;
1278 screen
->eu_total
= -1;
1279 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1283 intel_init_bufmgr(struct intel_screen
*screen
)
1285 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1287 if (getenv("INTEL_NO_HW") != NULL
)
1288 screen
->no_hw
= true;
1290 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
, BATCH_SZ
);
1291 if (screen
->bufmgr
== NULL
) {
1292 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1293 __func__
, __LINE__
);
1297 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1298 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1306 intel_detect_swizzling(struct intel_screen
*screen
)
1308 struct brw_bo
*buffer
;
1310 uint32_t aligned_pitch
;
1311 uint32_t tiling
= I915_TILING_X
;
1312 uint32_t swizzle_mode
= 0;
1314 buffer
= brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1315 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1319 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1320 brw_bo_unreference(buffer
);
1322 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1329 intel_detect_timestamp(struct intel_screen
*screen
)
1331 uint64_t dummy
= 0, last
= 0;
1332 int upper
, lower
, loops
;
1334 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1335 * TIMESTAMP register being shifted and the low 32bits always zero.
1337 * More recent kernels offer an interface to read the full 36bits
1340 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1343 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1344 * upper 32bits for a rapidly changing timestamp.
1346 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1350 for (loops
= 0; loops
< 10; loops
++) {
1351 /* The TIMESTAMP should change every 80ns, so several round trips
1352 * through the kernel should be enough to advance it.
1354 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1357 upper
+= (dummy
>> 32) != (last
>> 32);
1358 if (upper
> 1) /* beware 32bit counter overflow */
1359 return 2; /* upper dword holds the low 32bits of the timestamp */
1361 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1363 return 1; /* timestamp is unshifted */
1368 /* No advancement? No timestamp! */
1373 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1375 * Some combinations of hardware and kernel versions allow this feature,
1376 * while others don't. Instead of trying to enumerate every case, just
1377 * try and write a register and see if works.
1380 intel_detect_pipelined_register(struct intel_screen
*screen
,
1381 int reg
, uint32_t expected_value
, bool reset
)
1386 struct brw_bo
*results
, *bo
;
1388 uint32_t offset
= 0;
1389 bool success
= false;
1391 /* Create a zero'ed temporary buffer for reading our results */
1392 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1393 if (results
== NULL
)
1396 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1400 if (brw_bo_map(NULL
, bo
, 1))
1403 batch
= bo
->virtual;
1405 /* Write the register. */
1406 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1408 *batch
++ = expected_value
;
1410 /* Save the register's value back to the buffer. */
1411 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1413 struct drm_i915_gem_relocation_entry reloc
= {
1414 .offset
= (char *) batch
- (char *) bo
->virtual,
1415 .delta
= offset
* sizeof(uint32_t),
1416 .target_handle
= results
->gem_handle
,
1417 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1418 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1420 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1422 /* And afterwards clear the register */
1424 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1429 *batch
++ = MI_BATCH_BUFFER_END
;
1431 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1433 .handle
= results
->gem_handle
,
1436 .handle
= bo
->gem_handle
,
1437 .relocation_count
= 1,
1438 .relocs_ptr
= (uintptr_t) &reloc
,
1442 struct drm_i915_gem_execbuffer2 execbuf
= {
1443 .buffers_ptr
= (uintptr_t) exec_objects
,
1445 .batch_len
= ALIGN((char *) batch
- (char *) bo
->virtual, 8),
1446 .flags
= I915_EXEC_RENDER
,
1449 /* Don't bother with error checking - if the execbuf fails, the
1450 * value won't be written and we'll just report that there's no access.
1452 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1453 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1455 /* Check whether the value got written. */
1456 if (brw_bo_map(NULL
, results
, false) == 0) {
1457 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1458 brw_bo_unmap(results
);
1462 brw_bo_unreference(bo
);
1464 brw_bo_unreference(results
);
1470 intel_detect_pipelined_so(struct intel_screen
*screen
)
1472 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1474 /* Supposedly, Broadwell just works. */
1475 if (devinfo
->gen
>= 8)
1478 if (devinfo
->gen
<= 6)
1481 /* See the big explanation about command parser versions below */
1482 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1485 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1486 * statistics registers), and we already reset it to zero before using it.
1488 return intel_detect_pipelined_register(screen
,
1489 GEN7_SO_WRITE_OFFSET(0),
1495 * Return array of MSAA modes supported by the hardware. The array is
1496 * zero-terminated and sorted in decreasing order.
1499 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1501 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1502 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1503 static const int gen7_modes
[] = {8, 4, 0, -1};
1504 static const int gen6_modes
[] = {4, 0, -1};
1505 static const int gen4_modes
[] = {0, -1};
1507 if (screen
->devinfo
.gen
>= 9) {
1509 } else if (screen
->devinfo
.gen
>= 8) {
1511 } else if (screen
->devinfo
.gen
>= 7) {
1513 } else if (screen
->devinfo
.gen
== 6) {
1520 static __DRIconfig
**
1521 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1523 static const mesa_format formats
[] = {
1524 MESA_FORMAT_B5G6R5_UNORM
,
1525 MESA_FORMAT_B8G8R8A8_UNORM
,
1526 MESA_FORMAT_B8G8R8X8_UNORM
1529 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1530 static const GLenum back_buffer_modes
[] = {
1531 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1534 static const uint8_t singlesample_samples
[1] = {0};
1535 static const uint8_t multisample_samples
[2] = {4, 8};
1537 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1538 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1539 uint8_t depth_bits
[4], stencil_bits
[4];
1540 __DRIconfig
**configs
= NULL
;
1542 /* Generate singlesample configs without accumulation buffer. */
1543 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1544 __DRIconfig
**new_configs
;
1545 int num_depth_stencil_bits
= 2;
1547 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1548 * buffer that has a different number of bits per pixel than the color
1549 * buffer, gen >= 6 supports this.
1552 stencil_bits
[0] = 0;
1554 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1556 stencil_bits
[1] = 0;
1557 if (devinfo
->gen
>= 6) {
1559 stencil_bits
[2] = 8;
1560 num_depth_stencil_bits
= 3;
1564 stencil_bits
[1] = 8;
1567 new_configs
= driCreateConfigs(formats
[i
],
1570 num_depth_stencil_bits
,
1571 back_buffer_modes
, 2,
1572 singlesample_samples
, 1,
1574 configs
= driConcatConfigs(configs
, new_configs
);
1577 /* Generate the minimum possible set of configs that include an
1578 * accumulation buffer.
1580 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1581 __DRIconfig
**new_configs
;
1583 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1585 stencil_bits
[0] = 0;
1588 stencil_bits
[0] = 8;
1591 new_configs
= driCreateConfigs(formats
[i
],
1592 depth_bits
, stencil_bits
, 1,
1593 back_buffer_modes
, 1,
1594 singlesample_samples
, 1,
1596 configs
= driConcatConfigs(configs
, new_configs
);
1599 /* Generate multisample configs.
1601 * This loop breaks early, and hence is a no-op, on gen < 6.
1603 * Multisample configs must follow the singlesample configs in order to
1604 * work around an X server bug present in 1.12. The X server chooses to
1605 * associate the first listed RGBA888-Z24S8 config, regardless of its
1606 * sample count, with the 32-bit depth visual used for compositing.
1608 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1609 * supported. Singlebuffer configs are not supported because no one wants
1612 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1613 if (devinfo
->gen
< 6)
1616 __DRIconfig
**new_configs
;
1617 const int num_depth_stencil_bits
= 2;
1618 int num_msaa_modes
= 0;
1621 stencil_bits
[0] = 0;
1623 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1625 stencil_bits
[1] = 0;
1628 stencil_bits
[1] = 8;
1631 if (devinfo
->gen
>= 7)
1633 else if (devinfo
->gen
== 6)
1636 new_configs
= driCreateConfigs(formats
[i
],
1639 num_depth_stencil_bits
,
1640 back_buffer_modes
, 1,
1641 multisample_samples
,
1644 configs
= driConcatConfigs(configs
, new_configs
);
1647 if (configs
== NULL
) {
1648 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1657 set_max_gl_versions(struct intel_screen
*screen
)
1659 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1660 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1662 switch (screen
->devinfo
.gen
) {
1665 dri_screen
->max_gl_core_version
= 45;
1666 dri_screen
->max_gl_compat_version
= 30;
1667 dri_screen
->max_gl_es1_version
= 11;
1668 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1671 dri_screen
->max_gl_core_version
= 33;
1672 if (can_do_pipelined_register_writes(screen
)) {
1673 dri_screen
->max_gl_core_version
= 42;
1674 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
1675 dri_screen
->max_gl_core_version
= 43;
1676 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
1677 dri_screen
->max_gl_core_version
= 45;
1679 dri_screen
->max_gl_compat_version
= 30;
1680 dri_screen
->max_gl_es1_version
= 11;
1681 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1684 dri_screen
->max_gl_core_version
= 33;
1685 dri_screen
->max_gl_compat_version
= 30;
1686 dri_screen
->max_gl_es1_version
= 11;
1687 dri_screen
->max_gl_es2_version
= 30;
1691 dri_screen
->max_gl_core_version
= 0;
1692 dri_screen
->max_gl_compat_version
= 21;
1693 dri_screen
->max_gl_es1_version
= 11;
1694 dri_screen
->max_gl_es2_version
= 20;
1697 unreachable("unrecognized intel_screen::gen");
1702 * Return the revision (generally the revid field of the PCI header) of the
1705 * XXX: This function is useful to keep around even if it is not currently in
1706 * use. It is necessary for new platforms and revision specific workarounds or
1707 * features. Please don't remove it so that we know it at least continues to
1710 static __attribute__((__unused__
)) int
1711 brw_get_revision(int fd
)
1713 struct drm_i915_getparam gp
;
1717 memset(&gp
, 0, sizeof(gp
));
1718 gp
.param
= I915_PARAM_REVISION
;
1719 gp
.value
= &revision
;
1721 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1729 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1731 struct brw_context
*brw
= (struct brw_context
*)data
;
1734 va_start(args
, fmt
);
1736 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1737 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1738 MESA_DEBUG_TYPE_OTHER
,
1739 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1744 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1746 struct brw_context
*brw
= (struct brw_context
*)data
;
1749 va_start(args
, fmt
);
1751 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1753 va_copy(args_copy
, args
);
1754 vfprintf(stderr
, fmt
, args_copy
);
1758 if (brw
->perf_debug
) {
1760 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1761 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1762 MESA_DEBUG_TYPE_PERFORMANCE
,
1763 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1769 parse_devid_override(const char *devid_override
)
1771 static const struct {
1787 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
1788 if (!strcmp(name_map
[i
].name
, devid_override
))
1789 return name_map
[i
].pci_id
;
1792 return strtod(devid_override
, NULL
);
1796 * Get the PCI ID for the device. This can be overridden by setting the
1797 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
1799 * Returns -1 on ioctl failure.
1802 get_pci_device_id(struct intel_screen
*screen
)
1804 if (geteuid() == getuid()) {
1805 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
1806 if (devid_override
) {
1807 screen
->no_hw
= true;
1808 return parse_devid_override(devid_override
);
1812 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
1816 * This is the driver specific part of the createNewScreen entry point.
1817 * Called when using DRI2.
1819 * \return the struct gl_config supported by this driver
1822 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1824 struct intel_screen
*screen
;
1826 if (dri_screen
->image
.loader
) {
1827 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1828 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1830 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1831 "support required\n");
1835 /* Allocate the private area */
1836 screen
= rzalloc(NULL
, struct intel_screen
);
1838 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1841 /* parse information in __driConfigOptions */
1842 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1844 screen
->driScrnPriv
= dri_screen
;
1845 dri_screen
->driverPrivate
= (void *) screen
;
1847 screen
->deviceID
= get_pci_device_id(screen
);
1849 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1852 if (!intel_init_bufmgr(screen
))
1855 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1857 brw_process_intel_debug_variable();
1859 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
1861 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1862 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1865 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1866 /* Theorectically unlimited! At least for individual objects...
1868 * Currently the entire (global) address space for all GTT maps is
1869 * limited to 64bits. That is all objects on the system that are
1870 * setup for GTT mmapping must fit within 64bits. An attempt to use
1871 * one that exceeds the limit with fail in brw_bo_map_gtt().
1873 * Long before we hit that limit, we will be practically limited by
1874 * that any single object must fit in physical memory (RAM). The upper
1875 * limit on the CPU's address space is currently 48bits (Skylake), of
1876 * which only 39bits can be physical memory. (The GPU itself also has
1877 * a 48bit addressable virtual space.) We can fit over 32 million
1878 * objects of the current maximum allocable size before running out
1881 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1883 /* Estimate the size of the mappable aperture into the GTT. There's an
1884 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1885 * It turns out it's basically always 256MB, though some ancient hardware
1888 uint32_t gtt_size
= 256 * 1024 * 1024;
1890 /* We don't want to map two objects such that a memcpy between them would
1891 * just fault one mapping in and then the other over and over forever. So
1892 * we would need to divide the GTT size by 2. Additionally, some GTT is
1893 * taken up by things like the framebuffer and the ringbuffer and such, so
1894 * be more conservative.
1896 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1899 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
1901 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1902 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1904 /* GENs prior to 8 do not support EU/Subslice info */
1905 if (devinfo
->gen
>= 8) {
1906 intel_detect_sseu(screen
);
1907 } else if (devinfo
->gen
== 7) {
1908 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
1911 /* Gen7-7.5 kernel requirements / command parser saga:
1914 * Haswell and Baytrail cannot use any privileged batchbuffer features.
1916 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
1917 * all batches secure, allowing them to use any feature with no checking.
1918 * This is effectively equivalent to a command parser version of
1919 * \infinity - everything is possible.
1921 * The command parser does not exist, and querying the version will
1925 * The kernel enables the command parser by default, for systems with
1926 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
1927 * hardware checker is still enabled, so Haswell and Baytrail cannot
1930 * Ivybridge goes from "everything is possible" to "only what the
1931 * command parser allows" (if the user boots with i915.cmd_parser=0,
1932 * then everything is possible again). We can only safely use features
1933 * allowed by the supported command parser version.
1935 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
1936 * implemented by the kernel, even if it's turned off. So, checking
1937 * for version > 0 does not mean that you can write registers. We have
1938 * to try it and see. The version does, however, indicate the age of
1941 * Instead of matching the hardware checker's behavior of converting
1942 * privileged commands to MI_NOOP, it makes execbuf2 start returning
1943 * -EINVAL, making it dangerous to try and use privileged features.
1945 * Effective command parser versions:
1946 * - Haswell: 0 (reporting 1, writes don't work)
1947 * - Baytrail: 0 (reporting 1, writes don't work)
1948 * - Ivybridge: 1 (enabled) or infinite (disabled)
1951 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
1952 * effectively version 1 (enabled) or infinite (disabled).
1954 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
1955 * Command parser v2 supports predicate writes.
1957 * - Haswell: 0 (reporting 1, writes don't work)
1958 * - Baytrail: 2 (enabled) or infinite (disabled)
1959 * - Ivybridge: 2 (enabled) or infinite (disabled)
1961 * So version >= 2 is enough to know that Ivybridge and Baytrail
1962 * will work. Haswell still can't do anything.
1964 * - v4.0: Version 3 happened. Largely not relevant.
1966 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
1967 * L3 config registers are properly saved and restored as part
1968 * of the hardware context. We can approximately detect this point
1969 * in time by checking if I915_PARAM_REVISION is recognized - it
1970 * landed in a later commit, but in the same release cycle.
1972 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
1973 * Command parser finally gains secure batch promotion. On Haswell,
1974 * the hardware checker gets disabled, which finally allows it to do
1975 * privileged commands.
1977 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
1978 * - Haswell: 3 (enabled) or 0 (disabled)
1979 * - Baytrail: 3 (enabled) or infinite (disabled)
1980 * - Ivybridge: 3 (enabled) or infinite (disabled)
1982 * Unfortunately, detecting this point in time is tricky, because
1983 * no version bump happened when this important change occurred.
1984 * On Haswell, if we can write any register, then the kernel is at
1985 * least this new, and we can start trusting the version number.
1987 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
1988 * Command parser reaches version 4, allowing access to Haswell
1989 * atomic scratch and chicken3 registers. If version >= 4, we know
1990 * the kernel is new enough to support privileged features on all
1991 * hardware. However, the user might have disabled it...and the
1992 * kernel will still report version 4. So we still have to guess
1995 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
1996 * Command parser v5 whitelists indirect compute shader dispatch
1997 * registers, needed for OpenGL 4.3 and later.
2000 * Command parser v7 lets us use MI_MATH on Haswell.
2002 * Additionally, the kernel begins reporting version 0 when
2003 * the command parser is disabled, allowing us to skip the
2004 * guess-and-check step on Haswell. Unfortunately, this also
2005 * means that we can no longer use it as an indicator of the
2006 * age of the kernel.
2008 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2009 &screen
->cmd_parser_version
) < 0) {
2010 /* Command parser does not exist - getparam is unrecognized */
2011 screen
->cmd_parser_version
= 0;
2014 if (!intel_detect_pipelined_so(screen
)) {
2015 /* We can't do anything, so the effective version is 0. */
2016 screen
->cmd_parser_version
= 0;
2018 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2021 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2022 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2024 /* Haswell requires command parser version 4 in order to have L3
2025 * atomic scratch1 and chicken3 bits
2027 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2028 screen
->kernel_features
|=
2029 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2032 /* Haswell requires command parser version 6 in order to write to the
2033 * MI_MATH GPR registers, and version 7 in order to use
2034 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2036 if (devinfo
->gen
>= 8 ||
2037 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2038 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2041 /* Gen7 needs at least command parser version 5 to support compute */
2042 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2043 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2045 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2047 screen
->winsys_msaa_samples_override
=
2048 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2049 printf("Forcing winsys sample count to %d\n",
2050 screen
->winsys_msaa_samples_override
);
2052 screen
->winsys_msaa_samples_override
= -1;
2055 set_max_gl_versions(screen
);
2057 /* Notification of GPU resets requires hardware contexts and a kernel new
2058 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2059 * supported, calling it with a context of 0 will either generate EPERM or
2060 * no error. If the ioctl is not supported, it always generate EINVAL.
2061 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2062 * extension to the loader.
2064 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2066 if (devinfo
->gen
>= 6) {
2067 struct drm_i915_reset_stats stats
;
2068 memset(&stats
, 0, sizeof(stats
));
2070 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2072 screen
->has_context_reset_notification
=
2073 (ret
!= -1 || errno
!= EINVAL
);
2076 dri_screen
->extensions
= !screen
->has_context_reset_notification
2077 ? screenExtensions
: intelRobustScreenExtensions
;
2079 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2080 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2081 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2082 screen
->program_id
= 1;
2084 screen
->has_exec_fence
=
2085 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2087 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2090 struct intel_buffer
{
2095 static __DRIbuffer
*
2096 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2097 unsigned attachment
, unsigned format
,
2098 int width
, int height
)
2100 struct intel_buffer
*intelBuffer
;
2101 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2103 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2104 attachment
== __DRI_BUFFER_BACK_LEFT
);
2106 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2107 if (intelBuffer
== NULL
)
2110 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2111 * supports Y tiled and compressed buffers, but there is no way to plumb that
2112 * through to here. */
2114 int cpp
= format
/ 8;
2115 intelBuffer
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
,
2116 "intelAllocateBuffer",
2120 I915_TILING_X
, &pitch
,
2121 BO_ALLOC_FOR_RENDER
);
2123 if (intelBuffer
->bo
== NULL
) {
2128 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2130 intelBuffer
->base
.attachment
= attachment
;
2131 intelBuffer
->base
.cpp
= cpp
;
2132 intelBuffer
->base
.pitch
= pitch
;
2134 return &intelBuffer
->base
;
2138 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2140 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2142 brw_bo_unreference(intelBuffer
->bo
);
2146 static const struct __DriverAPIRec brw_driver_api
= {
2147 .InitScreen
= intelInitScreen2
,
2148 .DestroyScreen
= intelDestroyScreen
,
2149 .CreateContext
= brwCreateContext
,
2150 .DestroyContext
= intelDestroyContext
,
2151 .CreateBuffer
= intelCreateBuffer
,
2152 .DestroyBuffer
= intelDestroyBuffer
,
2153 .MakeCurrent
= intelMakeCurrent
,
2154 .UnbindContext
= intelUnbindContext
,
2155 .AllocateBuffer
= intelAllocateBuffer
,
2156 .ReleaseBuffer
= intelReleaseBuffer
2159 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2160 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2161 .vtable
= &brw_driver_api
,
2164 static const __DRIextension
*brw_driver_extensions
[] = {
2165 &driCoreExtension
.base
,
2166 &driImageDriverExtension
.base
,
2167 &driDRI2Extension
.base
,
2169 &brw_config_options
.base
,
2173 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2175 globalDriverAPI
= &brw_driver_api
;
2177 return brw_driver_extensions
;