2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
83 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
84 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
85 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
88 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 DRI_CONF_SECTION_MISCELLANEOUS
93 DRI_CONF_GLSL_ZERO_INIT("false")
98 #include "intel_batchbuffer.h"
99 #include "intel_buffers.h"
100 #include "intel_bufmgr.h"
101 #include "intel_fbo.h"
102 #include "intel_mipmap_tree.h"
103 #include "intel_screen.h"
104 #include "intel_tex.h"
105 #include "intel_image.h"
107 #include "brw_context.h"
109 #include "i915_drm.h"
112 * For debugging purposes, this returns a time in seconds.
119 clock_gettime(CLOCK_MONOTONIC
, &tp
);
121 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
125 aub_dump_bmp(struct gl_context
*ctx
)
127 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
129 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
130 struct intel_renderbuffer
*irb
=
131 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
133 if (irb
&& irb
->mt
) {
134 enum aub_dump_bmp_format format
;
136 switch (irb
->Base
.Base
.Format
) {
137 case MESA_FORMAT_B8G8R8A8_UNORM
:
138 case MESA_FORMAT_B8G8R8X8_UNORM
:
139 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
145 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
148 irb
->Base
.Base
.Width
,
149 irb
->Base
.Base
.Height
,
157 static const __DRItexBufferExtension intelTexBufferExtension
= {
158 .base
= { __DRI_TEX_BUFFER
, 3 },
160 .setTexBuffer
= intelSetTexBuffer
,
161 .setTexBuffer2
= intelSetTexBuffer2
,
162 .releaseTexBuffer
= NULL
,
166 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
167 __DRIdrawable
*dPriv
,
169 enum __DRI2throttleReason reason
)
171 struct brw_context
*brw
= cPriv
->driverPrivate
;
176 struct gl_context
*ctx
= &brw
->ctx
;
178 FLUSH_VERTICES(ctx
, 0);
180 if (flags
& __DRI2_FLUSH_DRAWABLE
)
181 intel_resolve_for_dri2_flush(brw
, dPriv
);
183 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
184 brw
->need_swap_throttle
= true;
185 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
186 brw
->need_flush_throttle
= true;
188 intel_batchbuffer_flush(brw
);
190 if (INTEL_DEBUG
& DEBUG_AUB
) {
196 * Provides compatibility with loaders that only support the older (version
197 * 1-3) flush interface.
199 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
202 intel_dri2_flush(__DRIdrawable
*drawable
)
204 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
205 __DRI2_FLUSH_DRAWABLE
,
206 __DRI2_THROTTLE_SWAPBUFFER
);
209 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
210 .base
= { __DRI2_FLUSH
, 4 },
212 .flush
= intel_dri2_flush
,
213 .invalidate
= dri2InvalidateDrawable
,
214 .flush_with_flags
= intel_dri2_flush_with_flags
,
217 static struct intel_image_format intel_image_formats
[] = {
218 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
221 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
224 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
227 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
230 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
233 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
236 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
239 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
240 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
242 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
245 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
246 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
247 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
250 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
251 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
252 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
255 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
256 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
257 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
260 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
261 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
262 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
265 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
270 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
275 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
276 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
277 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
280 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
281 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
282 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
283 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
285 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
286 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
287 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
288 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
290 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
291 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
292 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
293 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
295 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
296 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
297 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
299 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
301 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
303 /* For YUYV buffers, we set up two overlapping DRI images and treat
304 * them as planar buffers in the compositors. Plane 0 is GR88 and
305 * samples YU or YV pairs and places Y into the R component, while
306 * plane 1 is ARGB and samples YUYV clusters and places pairs and
307 * places U into the G component and V into A. This lets the
308 * texture sampler interpolate the Y components correctly when
309 * sampling from plane 0, and interpolate U and V correctly when
310 * sampling from plane 1. */
311 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
312 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
313 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
317 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
319 uint32_t tiling
, swizzle
;
320 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
322 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
323 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
324 func
, image
->offset
);
328 static struct intel_image_format
*
329 intel_image_format_lookup(int fourcc
)
331 struct intel_image_format
*f
= NULL
;
333 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
334 if (intel_image_formats
[i
].fourcc
== fourcc
) {
335 f
= &intel_image_formats
[i
];
343 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
345 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
346 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
347 *fourcc
= intel_image_formats
[i
].fourcc
;
355 intel_allocate_image(int dri_format
, void *loaderPrivate
)
359 image
= calloc(1, sizeof *image
);
363 image
->dri_format
= dri_format
;
366 image
->format
= driImageFormatToGLFormat(dri_format
);
367 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
368 image
->format
== MESA_FORMAT_NONE
) {
373 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
374 image
->data
= loaderPrivate
;
380 * Sets up a DRIImage structure to point to a slice out of a miptree.
383 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
384 struct intel_mipmap_tree
*mt
, GLuint level
,
387 intel_miptree_make_shareable(brw
, mt
);
389 intel_miptree_check_level_layer(mt
, level
, zoffset
);
391 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
392 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
393 image
->pitch
= mt
->pitch
;
395 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
399 drm_intel_bo_unreference(image
->bo
);
401 drm_intel_bo_reference(mt
->bo
);
405 intel_create_image_from_name(__DRIscreen
*dri_screen
,
406 int width
, int height
, int format
,
407 int name
, int pitch
, void *loaderPrivate
)
409 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
413 image
= intel_allocate_image(format
, loaderPrivate
);
417 if (image
->format
== MESA_FORMAT_NONE
)
420 cpp
= _mesa_get_format_bytes(image
->format
);
422 image
->width
= width
;
423 image
->height
= height
;
424 image
->pitch
= pitch
* cpp
;
425 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
436 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
437 int renderbuffer
, void *loaderPrivate
)
440 struct brw_context
*brw
= context
->driverPrivate
;
441 struct gl_context
*ctx
= &brw
->ctx
;
442 struct gl_renderbuffer
*rb
;
443 struct intel_renderbuffer
*irb
;
445 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
447 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
451 irb
= intel_renderbuffer(rb
);
452 intel_miptree_make_shareable(brw
, irb
->mt
);
453 image
= calloc(1, sizeof *image
);
457 image
->internal_format
= rb
->InternalFormat
;
458 image
->format
= rb
->Format
;
460 image
->data
= loaderPrivate
;
461 drm_intel_bo_unreference(image
->bo
);
462 image
->bo
= irb
->mt
->bo
;
463 drm_intel_bo_reference(irb
->mt
->bo
);
464 image
->width
= rb
->Width
;
465 image
->height
= rb
->Height
;
466 image
->pitch
= irb
->mt
->pitch
;
467 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
468 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
470 rb
->NeedsFinishRenderTexture
= true;
475 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
476 unsigned texture
, int zoffset
,
482 struct brw_context
*brw
= context
->driverPrivate
;
483 struct gl_texture_object
*obj
;
484 struct intel_texture_object
*iobj
;
487 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
488 if (!obj
|| obj
->Target
!= target
) {
489 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
493 if (target
== GL_TEXTURE_CUBE_MAP
)
496 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
497 iobj
= intel_texture_object(obj
);
498 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
499 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
503 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
504 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
508 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
509 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
512 image
= calloc(1, sizeof *image
);
514 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
518 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
519 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
520 image
->data
= loaderPrivate
;
521 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
522 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
523 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
524 if (image
->dri_format
== MESA_FORMAT_NONE
) {
525 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
530 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
535 intel_destroy_image(__DRIimage
*image
)
537 drm_intel_bo_unreference(image
->bo
);
542 intel_create_image(__DRIscreen
*dri_screen
,
543 int width
, int height
, int format
,
548 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
553 tiling
= I915_TILING_X
;
554 if (use
& __DRI_IMAGE_USE_CURSOR
) {
555 if (width
!= 64 || height
!= 64)
557 tiling
= I915_TILING_NONE
;
560 if (use
& __DRI_IMAGE_USE_LINEAR
)
561 tiling
= I915_TILING_NONE
;
563 image
= intel_allocate_image(format
, loaderPrivate
);
567 cpp
= _mesa_get_format_bytes(image
->format
);
568 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
569 width
, height
, cpp
, &tiling
,
571 if (image
->bo
== NULL
) {
575 image
->width
= width
;
576 image
->height
= height
;
577 image
->pitch
= pitch
;
583 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
586 case __DRI_IMAGE_ATTRIB_STRIDE
:
587 *value
= image
->pitch
;
589 case __DRI_IMAGE_ATTRIB_HANDLE
:
590 *value
= image
->bo
->handle
;
592 case __DRI_IMAGE_ATTRIB_NAME
:
593 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
594 case __DRI_IMAGE_ATTRIB_FORMAT
:
595 *value
= image
->dri_format
;
597 case __DRI_IMAGE_ATTRIB_WIDTH
:
598 *value
= image
->width
;
600 case __DRI_IMAGE_ATTRIB_HEIGHT
:
601 *value
= image
->height
;
603 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
604 if (image
->planar_format
== NULL
)
606 *value
= image
->planar_format
->components
;
608 case __DRI_IMAGE_ATTRIB_FD
:
609 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
610 case __DRI_IMAGE_ATTRIB_FOURCC
:
611 return intel_lookup_fourcc(image
->dri_format
, value
);
612 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
615 case __DRI_IMAGE_ATTRIB_OFFSET
:
616 *value
= image
->offset
;
625 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
629 image
= calloc(1, sizeof *image
);
633 drm_intel_bo_reference(orig_image
->bo
);
634 image
->bo
= orig_image
->bo
;
635 image
->internal_format
= orig_image
->internal_format
;
636 image
->planar_format
= orig_image
->planar_format
;
637 image
->dri_format
= orig_image
->dri_format
;
638 image
->format
= orig_image
->format
;
639 image
->offset
= orig_image
->offset
;
640 image
->width
= orig_image
->width
;
641 image
->height
= orig_image
->height
;
642 image
->pitch
= orig_image
->pitch
;
643 image
->tile_x
= orig_image
->tile_x
;
644 image
->tile_y
= orig_image
->tile_y
;
645 image
->has_depthstencil
= orig_image
->has_depthstencil
;
646 image
->data
= loaderPrivate
;
648 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
649 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
655 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
657 if (use
& __DRI_IMAGE_USE_CURSOR
) {
658 if (image
->width
!= 64 || image
->height
!= 64)
666 intel_create_image_from_names(__DRIscreen
*dri_screen
,
667 int width
, int height
, int fourcc
,
668 int *names
, int num_names
,
669 int *strides
, int *offsets
,
672 struct intel_image_format
*f
= NULL
;
676 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
679 f
= intel_image_format_lookup(fourcc
);
683 image
= intel_create_image_from_name(dri_screen
, width
, height
,
684 __DRI_IMAGE_FORMAT_NONE
,
685 names
[0], strides
[0],
691 image
->planar_format
= f
;
692 for (i
= 0; i
< f
->nplanes
; i
++) {
693 index
= f
->planes
[i
].buffer_index
;
694 image
->offsets
[index
] = offsets
[index
];
695 image
->strides
[index
] = strides
[index
];
702 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
703 int width
, int height
, int fourcc
,
704 int *fds
, int num_fds
, int *strides
, int *offsets
,
707 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
708 struct intel_image_format
*f
;
712 if (fds
== NULL
|| num_fds
< 1)
715 /* We only support all planes from the same bo */
716 for (i
= 0; i
< num_fds
; i
++)
717 if (fds
[0] != fds
[i
])
720 f
= intel_image_format_lookup(fourcc
);
725 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
727 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
732 image
->width
= width
;
733 image
->height
= height
;
734 image
->pitch
= strides
[0];
736 image
->planar_format
= f
;
738 for (i
= 0; i
< f
->nplanes
; i
++) {
739 index
= f
->planes
[i
].buffer_index
;
740 image
->offsets
[index
] = offsets
[index
];
741 image
->strides
[index
] = strides
[index
];
743 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
744 const int end
= offsets
[index
] + plane_height
* strides
[index
];
749 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
751 if (image
->bo
== NULL
) {
756 if (f
->nplanes
== 1) {
757 image
->offset
= image
->offsets
[0];
758 intel_image_warn_if_unaligned(image
, __func__
);
765 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
766 int width
, int height
, int fourcc
,
767 int *fds
, int num_fds
,
768 int *strides
, int *offsets
,
769 enum __DRIYUVColorSpace yuv_color_space
,
770 enum __DRISampleRange sample_range
,
771 enum __DRIChromaSiting horizontal_siting
,
772 enum __DRIChromaSiting vertical_siting
,
777 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
780 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
784 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
785 num_fds
, strides
, offsets
,
789 * Invalid parameters and any inconsistencies between are assumed to be
790 * checked by the caller. Therefore besides unsupported formats one can fail
791 * only in allocation.
794 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
798 image
->dma_buf_imported
= true;
799 image
->yuv_color_space
= yuv_color_space
;
800 image
->sample_range
= sample_range
;
801 image
->horizontal_siting
= horizontal_siting
;
802 image
->vertical_siting
= vertical_siting
;
804 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
809 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
811 int width
, height
, offset
, stride
, dri_format
, index
;
812 struct intel_image_format
*f
;
815 if (parent
== NULL
|| parent
->planar_format
== NULL
)
818 f
= parent
->planar_format
;
820 if (plane
>= f
->nplanes
)
823 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
824 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
825 dri_format
= f
->planes
[plane
].dri_format
;
826 index
= f
->planes
[plane
].buffer_index
;
827 offset
= parent
->offsets
[index
];
828 stride
= parent
->strides
[index
];
830 image
= intel_allocate_image(dri_format
, loaderPrivate
);
834 if (offset
+ height
* stride
> parent
->bo
->size
) {
835 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
840 image
->bo
= parent
->bo
;
841 drm_intel_bo_reference(parent
->bo
);
843 image
->width
= width
;
844 image
->height
= height
;
845 image
->pitch
= stride
;
846 image
->offset
= offset
;
848 intel_image_warn_if_unaligned(image
, __func__
);
853 static const __DRIimageExtension intelImageExtension
= {
854 .base
= { __DRI_IMAGE
, 13 },
856 .createImageFromName
= intel_create_image_from_name
,
857 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
858 .destroyImage
= intel_destroy_image
,
859 .createImage
= intel_create_image
,
860 .queryImage
= intel_query_image
,
861 .dupImage
= intel_dup_image
,
862 .validateUsage
= intel_validate_usage
,
863 .createImageFromNames
= intel_create_image_from_names
,
864 .fromPlanar
= intel_from_planar
,
865 .createImageFromTexture
= intel_create_image_from_texture
,
866 .createImageFromFds
= intel_create_image_from_fds
,
867 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
869 .getCapabilities
= NULL
,
875 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
876 int param
, unsigned int *value
)
878 const struct intel_screen
*const screen
=
879 (struct intel_screen
*) dri_screen
->driverPrivate
;
882 case __DRI2_RENDERER_VENDOR_ID
:
885 case __DRI2_RENDERER_DEVICE_ID
:
886 value
[0] = screen
->deviceID
;
888 case __DRI2_RENDERER_ACCELERATED
:
891 case __DRI2_RENDERER_VIDEO_MEMORY
: {
892 /* Once a batch uses more than 75% of the maximum mappable size, we
893 * assume that there's some fragmentation, and we start doing extra
894 * flushing, etc. That's the big cliff apps will care about.
897 size_t mappable_size
;
899 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
901 const unsigned gpu_mappable_megabytes
=
902 (aper_size
/ (1024 * 1024)) * 3 / 4;
904 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
905 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
907 if (system_memory_pages
<= 0 || system_page_size
<= 0)
910 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
911 * (uint64_t) system_page_size
;
913 const unsigned system_memory_megabytes
=
914 (unsigned) (system_memory_bytes
/ (1024 * 1024));
916 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
919 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
922 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
926 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
933 brw_query_renderer_string(__DRIscreen
*dri_screen
,
934 int param
, const char **value
)
936 const struct intel_screen
*screen
=
937 (struct intel_screen
*) dri_screen
->driverPrivate
;
940 case __DRI2_RENDERER_VENDOR_ID
:
941 value
[0] = brw_vendor_string
;
943 case __DRI2_RENDERER_DEVICE_ID
:
944 value
[0] = brw_get_renderer_string(screen
);
953 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
954 .base
= { __DRI2_RENDERER_QUERY
, 1 },
956 .queryInteger
= brw_query_renderer_integer
,
957 .queryString
= brw_query_renderer_string
960 static const __DRIrobustnessExtension dri2Robustness
= {
961 .base
= { __DRI2_ROBUSTNESS
, 1 }
964 static const __DRIextension
*screenExtensions
[] = {
965 &intelTexBufferExtension
.base
,
966 &intelFenceExtension
.base
,
967 &intelFlushExtension
.base
,
968 &intelImageExtension
.base
,
969 &intelRendererQueryExtension
.base
,
970 &dri2ConfigQueryExtension
.base
,
974 static const __DRIextension
*intelRobustScreenExtensions
[] = {
975 &intelTexBufferExtension
.base
,
976 &intelFenceExtension
.base
,
977 &intelFlushExtension
.base
,
978 &intelImageExtension
.base
,
979 &intelRendererQueryExtension
.base
,
980 &dri2ConfigQueryExtension
.base
,
981 &dri2Robustness
.base
,
986 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
989 struct drm_i915_getparam gp
;
991 memset(&gp
, 0, sizeof(gp
));
995 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
998 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1005 intel_get_boolean(struct intel_screen
*screen
, int param
)
1008 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1012 intel_get_integer(struct intel_screen
*screen
, int param
)
1016 if (intel_get_param(screen
, param
, &value
) == 0)
1023 intelDestroyScreen(__DRIscreen
* sPriv
)
1025 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1027 dri_bufmgr_destroy(screen
->bufmgr
);
1028 driDestroyOptionInfo(&screen
->optionCache
);
1030 ralloc_free(screen
);
1031 sPriv
->driverPrivate
= NULL
;
1036 * This is called when we need to set up GL rendering to a new X window.
1039 intelCreateBuffer(__DRIscreen
*dri_screen
,
1040 __DRIdrawable
* driDrawPriv
,
1041 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1043 struct intel_renderbuffer
*rb
;
1044 struct intel_screen
*screen
= (struct intel_screen
*)
1045 dri_screen
->driverPrivate
;
1046 mesa_format rgbFormat
;
1047 unsigned num_samples
=
1048 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1049 struct gl_framebuffer
*fb
;
1054 fb
= CALLOC_STRUCT(gl_framebuffer
);
1058 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1060 if (screen
->winsys_msaa_samples_override
!= -1) {
1061 num_samples
= screen
->winsys_msaa_samples_override
;
1062 fb
->Visual
.samples
= num_samples
;
1065 if (mesaVis
->redBits
== 5) {
1066 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1067 : MESA_FORMAT_B5G6R5_UNORM
;
1068 } else if (mesaVis
->sRGBCapable
) {
1069 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1070 : MESA_FORMAT_B8G8R8A8_SRGB
;
1071 } else if (mesaVis
->alphaBits
== 0) {
1072 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1073 : MESA_FORMAT_B8G8R8X8_UNORM
;
1075 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1076 : MESA_FORMAT_B8G8R8A8_SRGB
;
1077 fb
->Visual
.sRGBCapable
= true;
1080 /* setup the hardware-based renderbuffers */
1081 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1082 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1084 if (mesaVis
->doubleBufferMode
) {
1085 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1086 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1090 * Assert here that the gl_config has an expected depth/stencil bit
1091 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1092 * which constructs the advertised configs.)
1094 if (mesaVis
->depthBits
== 24) {
1095 assert(mesaVis
->stencilBits
== 8);
1097 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1098 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1100 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1101 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1103 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1106 * Use combined depth/stencil. Note that the renderbuffer is
1107 * attached to two attachment points.
1109 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1111 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1112 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1115 else if (mesaVis
->depthBits
== 16) {
1116 assert(mesaVis
->stencilBits
== 0);
1117 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1119 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1122 assert(mesaVis
->depthBits
== 0);
1123 assert(mesaVis
->stencilBits
== 0);
1126 /* now add any/all software-based renderbuffers we may need */
1127 _swrast_add_soft_renderbuffers(fb
,
1128 false, /* never sw color */
1129 false, /* never sw depth */
1130 false, /* never sw stencil */
1131 mesaVis
->accumRedBits
> 0,
1132 false, /* never sw alpha */
1133 false /* never sw aux */ );
1134 driDrawPriv
->driverPrivate
= fb
;
1140 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1142 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1144 _mesa_reference_framebuffer(&fb
, NULL
);
1148 intel_detect_sseu(struct intel_screen
*screen
)
1150 assert(screen
->devinfo
.gen
>= 8);
1153 screen
->subslice_total
= -1;
1154 screen
->eu_total
= -1;
1156 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1157 &screen
->subslice_total
);
1158 if (ret
< 0 && ret
!= -EINVAL
)
1161 ret
= intel_get_param(screen
,
1162 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1163 if (ret
< 0 && ret
!= -EINVAL
)
1166 /* Without this information, we cannot get the right Braswell brandstrings,
1167 * and we have to use conservative numbers for GPGPU on many platforms, but
1168 * otherwise, things will just work.
1170 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1172 "Kernel 4.1 required to properly query GPU properties.\n");
1177 screen
->subslice_total
= -1;
1178 screen
->eu_total
= -1;
1179 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1183 intel_init_bufmgr(struct intel_screen
*screen
)
1185 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1187 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1189 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1190 if (screen
->bufmgr
== NULL
) {
1191 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1192 __func__
, __LINE__
);
1196 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1198 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1199 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1207 intel_detect_swizzling(struct intel_screen
*screen
)
1209 drm_intel_bo
*buffer
;
1210 unsigned long flags
= 0;
1211 unsigned long aligned_pitch
;
1212 uint32_t tiling
= I915_TILING_X
;
1213 uint32_t swizzle_mode
= 0;
1215 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1217 &tiling
, &aligned_pitch
, flags
);
1221 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1222 drm_intel_bo_unreference(buffer
);
1224 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1231 intel_detect_timestamp(struct intel_screen
*screen
)
1233 uint64_t dummy
= 0, last
= 0;
1234 int upper
, lower
, loops
;
1236 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1237 * TIMESTAMP register being shifted and the low 32bits always zero.
1239 * More recent kernels offer an interface to read the full 36bits
1242 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1245 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1246 * upper 32bits for a rapidly changing timestamp.
1248 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1252 for (loops
= 0; loops
< 10; loops
++) {
1253 /* The TIMESTAMP should change every 80ns, so several round trips
1254 * through the kernel should be enough to advance it.
1256 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1259 upper
+= (dummy
>> 32) != (last
>> 32);
1260 if (upper
> 1) /* beware 32bit counter overflow */
1261 return 2; /* upper dword holds the low 32bits of the timestamp */
1263 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1265 return 1; /* timestamp is unshifted */
1270 /* No advancement? No timestamp! */
1275 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1277 * Some combinations of hardware and kernel versions allow this feature,
1278 * while others don't. Instead of trying to enumerate every case, just
1279 * try and write a register and see if works.
1282 intel_detect_pipelined_register(struct intel_screen
*screen
,
1283 int reg
, uint32_t expected_value
, bool reset
)
1285 drm_intel_bo
*results
, *bo
;
1287 uint32_t offset
= 0;
1288 bool success
= false;
1290 /* Create a zero'ed temporary buffer for reading our results */
1291 results
= drm_intel_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1292 if (results
== NULL
)
1295 bo
= drm_intel_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1299 if (drm_intel_bo_map(bo
, 1))
1302 batch
= bo
->virtual;
1304 /* Write the register. */
1305 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1307 *batch
++ = expected_value
;
1309 /* Save the register's value back to the buffer. */
1310 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1312 drm_intel_bo_emit_reloc(bo
, (char *)batch
-(char *)bo
->virtual,
1313 results
, offset
*sizeof(uint32_t),
1314 I915_GEM_DOMAIN_INSTRUCTION
,
1315 I915_GEM_DOMAIN_INSTRUCTION
);
1316 *batch
++ = results
->offset
+ offset
*sizeof(uint32_t);
1318 /* And afterwards clear the register */
1320 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1325 *batch
++ = MI_BATCH_BUFFER_END
;
1327 drm_intel_bo_mrb_exec(bo
, ALIGN((char *)batch
- (char *)bo
->virtual, 8),
1331 /* Check whether the value got written. */
1332 if (drm_intel_bo_map(results
, false) == 0) {
1333 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1334 drm_intel_bo_unmap(results
);
1338 drm_intel_bo_unreference(bo
);
1340 drm_intel_bo_unreference(results
);
1346 intel_detect_pipelined_so(struct intel_screen
*screen
)
1348 /* Supposedly, Broadwell just works. */
1349 if (screen
->devinfo
.gen
>= 8)
1352 if (screen
->devinfo
.gen
<= 6)
1355 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1356 * statistics registers), and we already reset it to zero before using it.
1358 return intel_detect_pipelined_register(screen
,
1359 GEN7_SO_WRITE_OFFSET(0),
1365 * Return array of MSAA modes supported by the hardware. The array is
1366 * zero-terminated and sorted in decreasing order.
1369 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1371 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1372 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1373 static const int gen7_modes
[] = {8, 4, 0, -1};
1374 static const int gen6_modes
[] = {4, 0, -1};
1375 static const int gen4_modes
[] = {0, -1};
1377 if (screen
->devinfo
.gen
>= 9) {
1379 } else if (screen
->devinfo
.gen
>= 8) {
1381 } else if (screen
->devinfo
.gen
>= 7) {
1383 } else if (screen
->devinfo
.gen
== 6) {
1390 static __DRIconfig
**
1391 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1393 static const mesa_format formats
[] = {
1394 MESA_FORMAT_B5G6R5_UNORM
,
1395 MESA_FORMAT_B8G8R8A8_UNORM
,
1396 MESA_FORMAT_B8G8R8X8_UNORM
1399 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1400 static const GLenum back_buffer_modes
[] = {
1401 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1404 static const uint8_t singlesample_samples
[1] = {0};
1405 static const uint8_t multisample_samples
[2] = {4, 8};
1407 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1408 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1409 uint8_t depth_bits
[4], stencil_bits
[4];
1410 __DRIconfig
**configs
= NULL
;
1412 /* Generate singlesample configs without accumulation buffer. */
1413 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1414 __DRIconfig
**new_configs
;
1415 int num_depth_stencil_bits
= 2;
1417 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1418 * buffer that has a different number of bits per pixel than the color
1419 * buffer, gen >= 6 supports this.
1422 stencil_bits
[0] = 0;
1424 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1426 stencil_bits
[1] = 0;
1427 if (devinfo
->gen
>= 6) {
1429 stencil_bits
[2] = 8;
1430 num_depth_stencil_bits
= 3;
1434 stencil_bits
[1] = 8;
1437 new_configs
= driCreateConfigs(formats
[i
],
1440 num_depth_stencil_bits
,
1441 back_buffer_modes
, 2,
1442 singlesample_samples
, 1,
1444 configs
= driConcatConfigs(configs
, new_configs
);
1447 /* Generate the minimum possible set of configs that include an
1448 * accumulation buffer.
1450 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1451 __DRIconfig
**new_configs
;
1453 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1455 stencil_bits
[0] = 0;
1458 stencil_bits
[0] = 8;
1461 new_configs
= driCreateConfigs(formats
[i
],
1462 depth_bits
, stencil_bits
, 1,
1463 back_buffer_modes
, 1,
1464 singlesample_samples
, 1,
1466 configs
= driConcatConfigs(configs
, new_configs
);
1469 /* Generate multisample configs.
1471 * This loop breaks early, and hence is a no-op, on gen < 6.
1473 * Multisample configs must follow the singlesample configs in order to
1474 * work around an X server bug present in 1.12. The X server chooses to
1475 * associate the first listed RGBA888-Z24S8 config, regardless of its
1476 * sample count, with the 32-bit depth visual used for compositing.
1478 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1479 * supported. Singlebuffer configs are not supported because no one wants
1482 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1483 if (devinfo
->gen
< 6)
1486 __DRIconfig
**new_configs
;
1487 const int num_depth_stencil_bits
= 2;
1488 int num_msaa_modes
= 0;
1491 stencil_bits
[0] = 0;
1493 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1495 stencil_bits
[1] = 0;
1498 stencil_bits
[1] = 8;
1501 if (devinfo
->gen
>= 7)
1503 else if (devinfo
->gen
== 6)
1506 new_configs
= driCreateConfigs(formats
[i
],
1509 num_depth_stencil_bits
,
1510 back_buffer_modes
, 1,
1511 multisample_samples
,
1514 configs
= driConcatConfigs(configs
, new_configs
);
1517 if (configs
== NULL
) {
1518 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1527 set_max_gl_versions(struct intel_screen
*screen
)
1529 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1530 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1532 switch (screen
->devinfo
.gen
) {
1535 dri_screen
->max_gl_core_version
= 45;
1536 dri_screen
->max_gl_compat_version
= 30;
1537 dri_screen
->max_gl_es1_version
= 11;
1538 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1541 dri_screen
->max_gl_core_version
= screen
->devinfo
.is_haswell
&&
1542 can_do_pipelined_register_writes(screen
) ? 45 : 33;
1543 dri_screen
->max_gl_compat_version
= 30;
1544 dri_screen
->max_gl_es1_version
= 11;
1545 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1548 dri_screen
->max_gl_core_version
= 33;
1549 dri_screen
->max_gl_compat_version
= 30;
1550 dri_screen
->max_gl_es1_version
= 11;
1551 dri_screen
->max_gl_es2_version
= 30;
1555 dri_screen
->max_gl_core_version
= 0;
1556 dri_screen
->max_gl_compat_version
= 21;
1557 dri_screen
->max_gl_es1_version
= 11;
1558 dri_screen
->max_gl_es2_version
= 20;
1561 unreachable("unrecognized intel_screen::gen");
1566 * Return the revision (generally the revid field of the PCI header) of the
1569 * XXX: This function is useful to keep around even if it is not currently in
1570 * use. It is necessary for new platforms and revision specific workarounds or
1571 * features. Please don't remove it so that we know it at least continues to
1574 static __attribute__((__unused__
)) int
1575 brw_get_revision(int fd
)
1577 struct drm_i915_getparam gp
;
1581 memset(&gp
, 0, sizeof(gp
));
1582 gp
.param
= I915_PARAM_REVISION
;
1583 gp
.value
= &revision
;
1585 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1592 /* Drop when RS headers get pulled to libdrm */
1593 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1594 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1598 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1600 struct brw_context
*brw
= (struct brw_context
*)data
;
1603 va_start(args
, fmt
);
1605 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1606 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1607 MESA_DEBUG_TYPE_OTHER
,
1608 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1613 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1615 struct brw_context
*brw
= (struct brw_context
*)data
;
1618 va_start(args
, fmt
);
1620 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1622 va_copy(args_copy
, args
);
1623 vfprintf(stderr
, fmt
, args_copy
);
1627 if (brw
->perf_debug
) {
1629 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1630 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1631 MESA_DEBUG_TYPE_PERFORMANCE
,
1632 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1638 * This is the driver specific part of the createNewScreen entry point.
1639 * Called when using DRI2.
1641 * \return the struct gl_config supported by this driver
1644 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1646 struct intel_screen
*screen
;
1648 if (dri_screen
->image
.loader
) {
1649 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1650 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1652 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1653 "support required\n");
1657 /* Allocate the private area */
1658 screen
= rzalloc(NULL
, struct intel_screen
);
1660 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1663 /* parse information in __driConfigOptions */
1664 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1666 screen
->driScrnPriv
= dri_screen
;
1667 dri_screen
->driverPrivate
= (void *) screen
;
1669 if (!intel_init_bufmgr(screen
))
1672 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1673 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1676 brw_process_intel_debug_variable();
1678 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1679 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1681 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && screen
->devinfo
.gen
< 7) {
1683 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1684 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1687 if (INTEL_DEBUG
& DEBUG_AUB
)
1688 drm_intel_bufmgr_gem_set_aub_dump(screen
->bufmgr
, true);
1690 #ifndef I915_PARAM_MMAP_GTT_VERSION
1691 #define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
1693 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1694 /* Theorectically unlimited! At least for individual objects...
1696 * Currently the entire (global) address space for all GTT maps is
1697 * limited to 64bits. That is all objects on the system that are
1698 * setup for GTT mmapping must fit within 64bits. An attempt to use
1699 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1701 * Long before we hit that limit, we will be practically limited by
1702 * that any single object must fit in physical memory (RAM). The upper
1703 * limit on the CPU's address space is currently 48bits (Skylake), of
1704 * which only 39bits can be physical memory. (The GPU itself also has
1705 * a 48bit addressable virtual space.) We can fit over 32 million
1706 * objects of the current maximum allocable size before running out
1709 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1711 /* Estimate the size of the mappable aperture into the GTT. There's an
1712 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1713 * It turns out it's basically always 256MB, though some ancient hardware
1716 uint32_t gtt_size
= 256 * 1024 * 1024;
1718 /* We don't want to map two objects such that a memcpy between them would
1719 * just fault one mapping in and then the other over and over forever. So
1720 * we would need to divide the GTT size by 2. Additionally, some GTT is
1721 * taken up by things like the framebuffer and the ringbuffer and such, so
1722 * be more conservative.
1724 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1727 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1728 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1730 /* GENs prior to 8 do not support EU/Subslice info */
1731 if (screen
->devinfo
.gen
>= 8) {
1732 intel_detect_sseu(screen
);
1733 } else if (screen
->devinfo
.gen
== 7) {
1734 screen
->subslice_total
= 1 << (screen
->devinfo
.gt
- 1);
1737 if (intel_detect_pipelined_so(screen
))
1738 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
1740 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1742 screen
->winsys_msaa_samples_override
=
1743 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1744 printf("Forcing winsys sample count to %d\n",
1745 screen
->winsys_msaa_samples_override
);
1747 screen
->winsys_msaa_samples_override
= -1;
1750 set_max_gl_versions(screen
);
1752 /* Notification of GPU resets requires hardware contexts and a kernel new
1753 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1754 * supported, calling it with a context of 0 will either generate EPERM or
1755 * no error. If the ioctl is not supported, it always generate EINVAL.
1756 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1757 * extension to the loader.
1759 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1761 if (screen
->devinfo
.gen
>= 6) {
1762 struct drm_i915_reset_stats stats
;
1763 memset(&stats
, 0, sizeof(stats
));
1765 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1767 screen
->has_context_reset_notification
=
1768 (ret
!= -1 || errno
!= EINVAL
);
1771 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1772 &screen
->cmd_parser_version
) < 0) {
1773 screen
->cmd_parser_version
= 0;
1776 if (screen
->devinfo
.gen
>= 8 || screen
->cmd_parser_version
>= 2)
1777 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
1779 /* Haswell requires command parser version 4 in order to have L3
1780 * atomic scratch1 and chicken3 bits
1782 if (screen
->devinfo
.is_haswell
&& screen
->cmd_parser_version
>= 4) {
1783 screen
->kernel_features
|=
1784 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
1787 /* Haswell requires command parser version 6 in order to write to the
1788 * MI_MATH GPR registers, and version 7 in order to use
1789 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1791 if (screen
->devinfo
.gen
>= 8 ||
1792 (screen
->devinfo
.is_haswell
&& screen
->cmd_parser_version
>= 7)) {
1793 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
1796 /* Gen7 needs at least command parser version 5 to support compute */
1797 if (screen
->devinfo
.gen
>= 8 || screen
->cmd_parser_version
>= 5)
1798 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
1800 dri_screen
->extensions
= !screen
->has_context_reset_notification
1801 ? screenExtensions
: intelRobustScreenExtensions
;
1803 screen
->compiler
= brw_compiler_create(screen
,
1805 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1806 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1807 screen
->program_id
= 1;
1809 if (screen
->devinfo
.has_resource_streamer
) {
1810 screen
->has_resource_streamer
=
1811 intel_get_boolean(screen
, I915_PARAM_HAS_RESOURCE_STREAMER
);
1814 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1817 struct intel_buffer
{
1822 static __DRIbuffer
*
1823 intelAllocateBuffer(__DRIscreen
*dri_screen
,
1824 unsigned attachment
, unsigned format
,
1825 int width
, int height
)
1827 struct intel_buffer
*intelBuffer
;
1828 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1830 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1831 attachment
== __DRI_BUFFER_BACK_LEFT
);
1833 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1834 if (intelBuffer
== NULL
)
1837 /* The front and back buffers are color buffers, which are X tiled. */
1838 uint32_t tiling
= I915_TILING_X
;
1839 unsigned long pitch
;
1840 int cpp
= format
/ 8;
1841 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
1842 "intelAllocateBuffer",
1847 BO_ALLOC_FOR_RENDER
);
1849 if (intelBuffer
->bo
== NULL
) {
1854 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1856 intelBuffer
->base
.attachment
= attachment
;
1857 intelBuffer
->base
.cpp
= cpp
;
1858 intelBuffer
->base
.pitch
= pitch
;
1860 return &intelBuffer
->base
;
1864 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
1866 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1868 drm_intel_bo_unreference(intelBuffer
->bo
);
1872 static const struct __DriverAPIRec brw_driver_api
= {
1873 .InitScreen
= intelInitScreen2
,
1874 .DestroyScreen
= intelDestroyScreen
,
1875 .CreateContext
= brwCreateContext
,
1876 .DestroyContext
= intelDestroyContext
,
1877 .CreateBuffer
= intelCreateBuffer
,
1878 .DestroyBuffer
= intelDestroyBuffer
,
1879 .MakeCurrent
= intelMakeCurrent
,
1880 .UnbindContext
= intelUnbindContext
,
1881 .AllocateBuffer
= intelAllocateBuffer
,
1882 .ReleaseBuffer
= intelReleaseBuffer
1885 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1886 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1887 .vtable
= &brw_driver_api
,
1890 static const __DRIextension
*brw_driver_extensions
[] = {
1891 &driCoreExtension
.base
,
1892 &driImageDriverExtension
.base
,
1893 &driDRI2Extension
.base
,
1895 &brw_config_options
.base
,
1899 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1901 globalDriverAPI
= &brw_driver_api
;
1903 return brw_driver_extensions
;