2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/context.h"
30 #include "main/framebuffer.h"
31 #include "main/renderbuffer.h"
32 #include "main/texobj.h"
33 #include "main/hash.h"
34 #include "main/fbobject.h"
35 #include "main/version.h"
36 #include "swrast/s_renderbuffer.h"
37 #include "util/ralloc.h"
38 #include "brw_shader.h"
39 #include "compiler/nir/nir.h"
44 static const __DRIconfigOptionsExtension brw_config_options
= {
45 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
48 DRI_CONF_SECTION_PERFORMANCE
49 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
50 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
51 * DRI_CONF_BO_REUSE_ALL
53 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
54 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
55 DRI_CONF_ENUM(0, "Disable buffer object reuse")
56 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
61 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
65 DRI_CONF_SECTION_QUALITY
66 DRI_CONF_FORCE_S3TC_ENABLE("false")
68 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
69 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
70 "given integer. If negative, then do not clamp.")
74 DRI_CONF_SECTION_DEBUG
75 DRI_CONF_NO_RAST("false")
76 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
77 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
78 DRI_CONF_DISABLE_THROTTLING("false")
79 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
80 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
81 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
82 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
83 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
85 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
86 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 #include "intel_batchbuffer.h"
93 #include "intel_buffers.h"
94 #include "intel_bufmgr.h"
95 #include "intel_fbo.h"
96 #include "intel_mipmap_tree.h"
97 #include "intel_screen.h"
98 #include "intel_tex.h"
99 #include "intel_image.h"
101 #include "brw_context.h"
103 #include "i915_drm.h"
106 * For debugging purposes, this returns a time in seconds.
113 clock_gettime(CLOCK_MONOTONIC
, &tp
);
115 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
119 aub_dump_bmp(struct gl_context
*ctx
)
121 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
123 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
124 struct intel_renderbuffer
*irb
=
125 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
127 if (irb
&& irb
->mt
) {
128 enum aub_dump_bmp_format format
;
130 switch (irb
->Base
.Base
.Format
) {
131 case MESA_FORMAT_B8G8R8A8_UNORM
:
132 case MESA_FORMAT_B8G8R8X8_UNORM
:
133 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
139 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
142 irb
->Base
.Base
.Width
,
143 irb
->Base
.Base
.Height
,
151 static const __DRItexBufferExtension intelTexBufferExtension
= {
152 .base
= { __DRI_TEX_BUFFER
, 3 },
154 .setTexBuffer
= intelSetTexBuffer
,
155 .setTexBuffer2
= intelSetTexBuffer2
,
156 .releaseTexBuffer
= NULL
,
160 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
161 __DRIdrawable
*dPriv
,
163 enum __DRI2throttleReason reason
)
165 struct brw_context
*brw
= cPriv
->driverPrivate
;
170 struct gl_context
*ctx
= &brw
->ctx
;
172 FLUSH_VERTICES(ctx
, 0);
174 if (flags
& __DRI2_FLUSH_DRAWABLE
)
175 intel_resolve_for_dri2_flush(brw
, dPriv
);
177 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
178 brw
->need_swap_throttle
= true;
179 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
180 brw
->need_flush_throttle
= true;
182 intel_batchbuffer_flush(brw
);
184 if (INTEL_DEBUG
& DEBUG_AUB
) {
190 * Provides compatibility with loaders that only support the older (version
191 * 1-3) flush interface.
193 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
196 intel_dri2_flush(__DRIdrawable
*drawable
)
198 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
199 __DRI2_FLUSH_DRAWABLE
,
200 __DRI2_THROTTLE_SWAPBUFFER
);
203 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
204 .base
= { __DRI2_FLUSH
, 4 },
206 .flush
= intel_dri2_flush
,
207 .invalidate
= dri2InvalidateDrawable
,
208 .flush_with_flags
= intel_dri2_flush_with_flags
,
211 static struct intel_image_format intel_image_formats
[] = {
212 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
215 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
218 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
221 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
224 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
227 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
230 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
233 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
236 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
265 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
269 /* For YUYV buffers, we set up two overlapping DRI images and treat
270 * them as planar buffers in the compositors. Plane 0 is GR88 and
271 * samples YU or YV pairs and places Y into the R component, while
272 * plane 1 is ARGB and samples YUYV clusters and places pairs and
273 * places U into the G component and V into A. This lets the
274 * texture sampler interpolate the Y components correctly when
275 * sampling from plane 0, and interpolate U and V correctly when
276 * sampling from plane 1. */
277 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
279 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
283 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
285 uint32_t tiling
, swizzle
;
286 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
288 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
289 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
290 func
, image
->offset
);
294 static struct intel_image_format
*
295 intel_image_format_lookup(int fourcc
)
297 struct intel_image_format
*f
= NULL
;
299 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
300 if (intel_image_formats
[i
].fourcc
== fourcc
) {
301 f
= &intel_image_formats
[i
];
309 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
311 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
312 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
313 *fourcc
= intel_image_formats
[i
].fourcc
;
321 intel_allocate_image(int dri_format
, void *loaderPrivate
)
325 image
= calloc(1, sizeof *image
);
329 image
->dri_format
= dri_format
;
332 image
->format
= driImageFormatToGLFormat(dri_format
);
333 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
334 image
->format
== MESA_FORMAT_NONE
) {
339 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
340 image
->data
= loaderPrivate
;
346 * Sets up a DRIImage structure to point to a slice out of a miptree.
349 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
350 struct intel_mipmap_tree
*mt
, GLuint level
,
353 intel_miptree_make_shareable(brw
, mt
);
355 intel_miptree_check_level_layer(mt
, level
, zoffset
);
357 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
358 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
359 image
->pitch
= mt
->pitch
;
361 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
365 drm_intel_bo_unreference(image
->bo
);
367 drm_intel_bo_reference(mt
->bo
);
371 intel_create_image_from_name(__DRIscreen
*screen
,
372 int width
, int height
, int format
,
373 int name
, int pitch
, void *loaderPrivate
)
375 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
379 image
= intel_allocate_image(format
, loaderPrivate
);
383 if (image
->format
== MESA_FORMAT_NONE
)
386 cpp
= _mesa_get_format_bytes(image
->format
);
388 image
->width
= width
;
389 image
->height
= height
;
390 image
->pitch
= pitch
* cpp
;
391 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
402 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
403 int renderbuffer
, void *loaderPrivate
)
406 struct brw_context
*brw
= context
->driverPrivate
;
407 struct gl_context
*ctx
= &brw
->ctx
;
408 struct gl_renderbuffer
*rb
;
409 struct intel_renderbuffer
*irb
;
411 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
413 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
417 irb
= intel_renderbuffer(rb
);
418 intel_miptree_make_shareable(brw
, irb
->mt
);
419 image
= calloc(1, sizeof *image
);
423 image
->internal_format
= rb
->InternalFormat
;
424 image
->format
= rb
->Format
;
426 image
->data
= loaderPrivate
;
427 drm_intel_bo_unreference(image
->bo
);
428 image
->bo
= irb
->mt
->bo
;
429 drm_intel_bo_reference(irb
->mt
->bo
);
430 image
->width
= rb
->Width
;
431 image
->height
= rb
->Height
;
432 image
->pitch
= irb
->mt
->pitch
;
433 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
434 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
436 rb
->NeedsFinishRenderTexture
= true;
441 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
442 unsigned texture
, int zoffset
,
448 struct brw_context
*brw
= context
->driverPrivate
;
449 struct gl_texture_object
*obj
;
450 struct intel_texture_object
*iobj
;
453 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
454 if (!obj
|| obj
->Target
!= target
) {
455 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
459 if (target
== GL_TEXTURE_CUBE_MAP
)
462 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
463 iobj
= intel_texture_object(obj
);
464 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
465 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
469 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
470 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
474 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
475 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
478 image
= calloc(1, sizeof *image
);
480 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
484 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
485 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
486 image
->data
= loaderPrivate
;
487 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
488 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
489 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
490 if (image
->dri_format
== MESA_FORMAT_NONE
) {
491 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
496 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
501 intel_destroy_image(__DRIimage
*image
)
503 drm_intel_bo_unreference(image
->bo
);
508 intel_create_image(__DRIscreen
*screen
,
509 int width
, int height
, int format
,
514 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
519 if (intelScreen
->devinfo
->gen
>= 9) {
520 tiling
= I915_TILING_Y
;
522 tiling
= I915_TILING_X
;
524 if (use
& __DRI_IMAGE_USE_CURSOR
) {
525 if (width
!= 64 || height
!= 64)
527 tiling
= I915_TILING_NONE
;
530 if (use
& __DRI_IMAGE_USE_LINEAR
)
531 tiling
= I915_TILING_NONE
;
533 image
= intel_allocate_image(format
, loaderPrivate
);
537 cpp
= _mesa_get_format_bytes(image
->format
);
538 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
539 width
, height
, cpp
, &tiling
,
541 if (image
->bo
== NULL
) {
545 image
->width
= width
;
546 image
->height
= height
;
547 image
->pitch
= pitch
;
553 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
556 case __DRI_IMAGE_ATTRIB_STRIDE
:
557 *value
= image
->pitch
;
559 case __DRI_IMAGE_ATTRIB_HANDLE
:
560 *value
= image
->bo
->handle
;
562 case __DRI_IMAGE_ATTRIB_NAME
:
563 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
564 case __DRI_IMAGE_ATTRIB_FORMAT
:
565 *value
= image
->dri_format
;
567 case __DRI_IMAGE_ATTRIB_WIDTH
:
568 *value
= image
->width
;
570 case __DRI_IMAGE_ATTRIB_HEIGHT
:
571 *value
= image
->height
;
573 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
574 if (image
->planar_format
== NULL
)
576 *value
= image
->planar_format
->components
;
578 case __DRI_IMAGE_ATTRIB_FD
:
579 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
582 case __DRI_IMAGE_ATTRIB_FOURCC
:
583 if (intel_lookup_fourcc(image
->dri_format
, value
))
586 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
596 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
600 image
= calloc(1, sizeof *image
);
604 drm_intel_bo_reference(orig_image
->bo
);
605 image
->bo
= orig_image
->bo
;
606 image
->internal_format
= orig_image
->internal_format
;
607 image
->planar_format
= orig_image
->planar_format
;
608 image
->dri_format
= orig_image
->dri_format
;
609 image
->format
= orig_image
->format
;
610 image
->offset
= orig_image
->offset
;
611 image
->width
= orig_image
->width
;
612 image
->height
= orig_image
->height
;
613 image
->pitch
= orig_image
->pitch
;
614 image
->tile_x
= orig_image
->tile_x
;
615 image
->tile_y
= orig_image
->tile_y
;
616 image
->has_depthstencil
= orig_image
->has_depthstencil
;
617 image
->data
= loaderPrivate
;
619 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
620 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
626 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
628 if (use
& __DRI_IMAGE_USE_CURSOR
) {
629 if (image
->width
!= 64 || image
->height
!= 64)
637 intel_create_image_from_names(__DRIscreen
*screen
,
638 int width
, int height
, int fourcc
,
639 int *names
, int num_names
,
640 int *strides
, int *offsets
,
643 struct intel_image_format
*f
= NULL
;
647 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
650 f
= intel_image_format_lookup(fourcc
);
654 image
= intel_create_image_from_name(screen
, width
, height
,
655 __DRI_IMAGE_FORMAT_NONE
,
656 names
[0], strides
[0],
662 image
->planar_format
= f
;
663 for (i
= 0; i
< f
->nplanes
; i
++) {
664 index
= f
->planes
[i
].buffer_index
;
665 image
->offsets
[index
] = offsets
[index
];
666 image
->strides
[index
] = strides
[index
];
673 intel_create_image_from_fds(__DRIscreen
*screen
,
674 int width
, int height
, int fourcc
,
675 int *fds
, int num_fds
, int *strides
, int *offsets
,
678 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
679 struct intel_image_format
*f
;
683 if (fds
== NULL
|| num_fds
!= 1)
686 f
= intel_image_format_lookup(fourcc
);
691 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
693 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
698 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
700 height
* strides
[0]);
701 if (image
->bo
== NULL
) {
705 image
->width
= width
;
706 image
->height
= height
;
707 image
->pitch
= strides
[0];
709 image
->planar_format
= f
;
710 for (i
= 0; i
< f
->nplanes
; i
++) {
711 index
= f
->planes
[i
].buffer_index
;
712 image
->offsets
[index
] = offsets
[index
];
713 image
->strides
[index
] = strides
[index
];
716 if (f
->nplanes
== 1) {
717 image
->offset
= image
->offsets
[0];
718 intel_image_warn_if_unaligned(image
, __func__
);
725 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
726 int width
, int height
, int fourcc
,
727 int *fds
, int num_fds
,
728 int *strides
, int *offsets
,
729 enum __DRIYUVColorSpace yuv_color_space
,
730 enum __DRISampleRange sample_range
,
731 enum __DRIChromaSiting horizontal_siting
,
732 enum __DRIChromaSiting vertical_siting
,
737 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
739 /* For now only packed formats that have native sampling are supported. */
740 if (!f
|| f
->nplanes
!= 1) {
741 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
745 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
746 num_fds
, strides
, offsets
,
750 * Invalid parameters and any inconsistencies between are assumed to be
751 * checked by the caller. Therefore besides unsupported formats one can fail
752 * only in allocation.
755 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
759 image
->dma_buf_imported
= true;
760 image
->yuv_color_space
= yuv_color_space
;
761 image
->sample_range
= sample_range
;
762 image
->horizontal_siting
= horizontal_siting
;
763 image
->vertical_siting
= vertical_siting
;
765 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
770 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
772 int width
, height
, offset
, stride
, dri_format
, index
;
773 struct intel_image_format
*f
;
776 if (parent
== NULL
|| parent
->planar_format
== NULL
)
779 f
= parent
->planar_format
;
781 if (plane
>= f
->nplanes
)
784 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
785 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
786 dri_format
= f
->planes
[plane
].dri_format
;
787 index
= f
->planes
[plane
].buffer_index
;
788 offset
= parent
->offsets
[index
];
789 stride
= parent
->strides
[index
];
791 image
= intel_allocate_image(dri_format
, loaderPrivate
);
795 if (offset
+ height
* stride
> parent
->bo
->size
) {
796 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
801 image
->bo
= parent
->bo
;
802 drm_intel_bo_reference(parent
->bo
);
804 image
->width
= width
;
805 image
->height
= height
;
806 image
->pitch
= stride
;
807 image
->offset
= offset
;
809 intel_image_warn_if_unaligned(image
, __func__
);
814 static const __DRIimageExtension intelImageExtension
= {
815 .base
= { __DRI_IMAGE
, 11 },
817 .createImageFromName
= intel_create_image_from_name
,
818 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
819 .destroyImage
= intel_destroy_image
,
820 .createImage
= intel_create_image
,
821 .queryImage
= intel_query_image
,
822 .dupImage
= intel_dup_image
,
823 .validateUsage
= intel_validate_usage
,
824 .createImageFromNames
= intel_create_image_from_names
,
825 .fromPlanar
= intel_from_planar
,
826 .createImageFromTexture
= intel_create_image_from_texture
,
827 .createImageFromFds
= intel_create_image_from_fds
,
828 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
830 .getCapabilities
= NULL
834 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
836 const struct intel_screen
*const intelScreen
=
837 (struct intel_screen
*) psp
->driverPrivate
;
840 case __DRI2_RENDERER_VENDOR_ID
:
843 case __DRI2_RENDERER_DEVICE_ID
:
844 value
[0] = intelScreen
->deviceID
;
846 case __DRI2_RENDERER_ACCELERATED
:
849 case __DRI2_RENDERER_VIDEO_MEMORY
: {
850 /* Once a batch uses more than 75% of the maximum mappable size, we
851 * assume that there's some fragmentation, and we start doing extra
852 * flushing, etc. That's the big cliff apps will care about.
855 size_t mappable_size
;
857 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
859 const unsigned gpu_mappable_megabytes
=
860 (aper_size
/ (1024 * 1024)) * 3 / 4;
862 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
863 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
865 if (system_memory_pages
<= 0 || system_page_size
<= 0)
868 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
869 * (uint64_t) system_page_size
;
871 const unsigned system_memory_megabytes
=
872 (unsigned) (system_memory_bytes
/ (1024 * 1024));
874 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
877 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
881 return driQueryRendererIntegerCommon(psp
, param
, value
);
888 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
890 const struct intel_screen
*intelScreen
=
891 (struct intel_screen
*) psp
->driverPrivate
;
894 case __DRI2_RENDERER_VENDOR_ID
:
895 value
[0] = brw_vendor_string
;
897 case __DRI2_RENDERER_DEVICE_ID
:
898 value
[0] = brw_get_renderer_string(intelScreen
);
907 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
908 .base
= { __DRI2_RENDERER_QUERY
, 1 },
910 .queryInteger
= brw_query_renderer_integer
,
911 .queryString
= brw_query_renderer_string
914 static const __DRIrobustnessExtension dri2Robustness
= {
915 .base
= { __DRI2_ROBUSTNESS
, 1 }
918 static const __DRIextension
*intelScreenExtensions
[] = {
919 &intelTexBufferExtension
.base
,
920 &intelFenceExtension
.base
,
921 &intelFlushExtension
.base
,
922 &intelImageExtension
.base
,
923 &intelRendererQueryExtension
.base
,
924 &dri2ConfigQueryExtension
.base
,
928 static const __DRIextension
*intelRobustScreenExtensions
[] = {
929 &intelTexBufferExtension
.base
,
930 &intelFenceExtension
.base
,
931 &intelFlushExtension
.base
,
932 &intelImageExtension
.base
,
933 &intelRendererQueryExtension
.base
,
934 &dri2ConfigQueryExtension
.base
,
935 &dri2Robustness
.base
,
940 intel_get_param(__DRIscreen
*psp
, int param
, int *value
)
943 struct drm_i915_getparam gp
;
945 memset(&gp
, 0, sizeof(gp
));
949 ret
= drmCommandWriteRead(psp
->fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
950 if (ret
< 0 && ret
!= -EINVAL
)
951 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
957 intel_get_boolean(__DRIscreen
*psp
, int param
)
960 return (intel_get_param(psp
, param
, &value
) == 0) && value
;
964 intelDestroyScreen(__DRIscreen
* sPriv
)
966 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
968 dri_bufmgr_destroy(intelScreen
->bufmgr
);
969 driDestroyOptionInfo(&intelScreen
->optionCache
);
971 ralloc_free(intelScreen
);
972 sPriv
->driverPrivate
= NULL
;
977 * This is called when we need to set up GL rendering to a new X window.
980 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
981 __DRIdrawable
* driDrawPriv
,
982 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
984 struct intel_renderbuffer
*rb
;
985 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
986 mesa_format rgbFormat
;
987 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
988 struct gl_framebuffer
*fb
;
993 fb
= CALLOC_STRUCT(gl_framebuffer
);
997 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
999 if (screen
->winsys_msaa_samples_override
!= -1) {
1000 num_samples
= screen
->winsys_msaa_samples_override
;
1001 fb
->Visual
.samples
= num_samples
;
1004 if (mesaVis
->redBits
== 5) {
1005 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1006 : MESA_FORMAT_B5G6R5_UNORM
;
1007 } else if (mesaVis
->sRGBCapable
) {
1008 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1009 : MESA_FORMAT_B8G8R8A8_SRGB
;
1010 } else if (mesaVis
->alphaBits
== 0) {
1011 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1012 : MESA_FORMAT_B8G8R8X8_UNORM
;
1014 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1015 : MESA_FORMAT_B8G8R8A8_SRGB
;
1016 fb
->Visual
.sRGBCapable
= true;
1019 /* setup the hardware-based renderbuffers */
1020 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1021 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1023 if (mesaVis
->doubleBufferMode
) {
1024 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1025 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1029 * Assert here that the gl_config has an expected depth/stencil bit
1030 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1031 * which constructs the advertised configs.)
1033 if (mesaVis
->depthBits
== 24) {
1034 assert(mesaVis
->stencilBits
== 8);
1036 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1037 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1039 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1040 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1042 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1045 * Use combined depth/stencil. Note that the renderbuffer is
1046 * attached to two attachment points.
1048 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1050 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1051 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1054 else if (mesaVis
->depthBits
== 16) {
1055 assert(mesaVis
->stencilBits
== 0);
1056 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1058 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1061 assert(mesaVis
->depthBits
== 0);
1062 assert(mesaVis
->stencilBits
== 0);
1065 /* now add any/all software-based renderbuffers we may need */
1066 _swrast_add_soft_renderbuffers(fb
,
1067 false, /* never sw color */
1068 false, /* never sw depth */
1069 false, /* never sw stencil */
1070 mesaVis
->accumRedBits
> 0,
1071 false, /* never sw alpha */
1072 false /* never sw aux */ );
1073 driDrawPriv
->driverPrivate
= fb
;
1079 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1081 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1083 _mesa_reference_framebuffer(&fb
, NULL
);
1087 intel_detect_sseu(struct intel_screen
*intelScreen
)
1089 assert(intelScreen
->devinfo
->gen
>= 8);
1092 intelScreen
->subslice_total
= -1;
1093 intelScreen
->eu_total
= -1;
1095 ret
= intel_get_param(intelScreen
->driScrnPriv
, I915_PARAM_SUBSLICE_TOTAL
,
1096 &intelScreen
->subslice_total
);
1097 if (ret
< 0 && ret
!= -EINVAL
)
1100 ret
= intel_get_param(intelScreen
->driScrnPriv
,
1101 I915_PARAM_EU_TOTAL
, &intelScreen
->eu_total
);
1102 if (ret
< 0 && ret
!= -EINVAL
)
1105 /* Without this information, we cannot get the right Braswell brandstrings,
1106 * and we have to use conservative numbers for GPGPU on many platforms, but
1107 * otherwise, things will just work.
1109 if (intelScreen
->subslice_total
< 1 || intelScreen
->eu_total
< 1)
1111 "Kernel 4.1 required to properly query GPU properties.\n");
1116 intelScreen
->subslice_total
= -1;
1117 intelScreen
->eu_total
= -1;
1118 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(ret
));
1122 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1124 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1126 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1128 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1129 if (intelScreen
->bufmgr
== NULL
) {
1130 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1131 __func__
, __LINE__
);
1135 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1137 if (!intel_get_boolean(spriv
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1138 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1146 intel_detect_swizzling(struct intel_screen
*screen
)
1148 drm_intel_bo
*buffer
;
1149 unsigned long flags
= 0;
1150 unsigned long aligned_pitch
;
1151 uint32_t swizzle_mode
= 0;
1154 if (screen
->devinfo
->gen
>= 9) {
1155 tiling
= I915_TILING_Y
;
1157 tiling
= I915_TILING_X
;
1160 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1162 &tiling
, &aligned_pitch
, flags
);
1166 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1167 drm_intel_bo_unreference(buffer
);
1169 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1176 intel_detect_timestamp(struct intel_screen
*screen
)
1178 uint64_t dummy
= 0, last
= 0;
1179 int upper
, lower
, loops
;
1181 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1182 * TIMESTAMP register being shifted and the low 32bits always zero.
1184 * More recent kernels offer an interface to read the full 36bits
1187 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1190 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1191 * upper 32bits for a rapidly changing timestamp.
1193 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1197 for (loops
= 0; loops
< 10; loops
++) {
1198 /* The TIMESTAMP should change every 80ns, so several round trips
1199 * through the kernel should be enough to advance it.
1201 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1204 upper
+= (dummy
>> 32) != (last
>> 32);
1205 if (upper
> 1) /* beware 32bit counter overflow */
1206 return 2; /* upper dword holds the low 32bits of the timestamp */
1208 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1210 return 1; /* timestamp is unshifted */
1215 /* No advancement? No timestamp! */
1220 * Return array of MSAA modes supported by the hardware. The array is
1221 * zero-terminated and sorted in decreasing order.
1224 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1226 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1227 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1228 static const int gen7_modes
[] = {8, 4, 0, -1};
1229 static const int gen6_modes
[] = {4, 0, -1};
1230 static const int gen4_modes
[] = {0, -1};
1232 if (screen
->devinfo
->gen
>= 9) {
1234 } else if (screen
->devinfo
->gen
>= 8) {
1236 } else if (screen
->devinfo
->gen
>= 7) {
1238 } else if (screen
->devinfo
->gen
== 6) {
1245 static __DRIconfig
**
1246 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1248 static const mesa_format formats
[] = {
1249 MESA_FORMAT_B5G6R5_UNORM
,
1250 MESA_FORMAT_B8G8R8A8_UNORM
,
1251 MESA_FORMAT_B8G8R8X8_UNORM
1254 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1255 static const GLenum back_buffer_modes
[] = {
1256 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1259 static const uint8_t singlesample_samples
[1] = {0};
1260 static const uint8_t multisample_samples
[2] = {4, 8};
1262 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1263 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1264 uint8_t depth_bits
[4], stencil_bits
[4];
1265 __DRIconfig
**configs
= NULL
;
1267 /* Generate singlesample configs without accumulation buffer. */
1268 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1269 __DRIconfig
**new_configs
;
1270 int num_depth_stencil_bits
= 2;
1272 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1273 * buffer that has a different number of bits per pixel than the color
1274 * buffer, gen >= 6 supports this.
1277 stencil_bits
[0] = 0;
1279 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1281 stencil_bits
[1] = 0;
1282 if (devinfo
->gen
>= 6) {
1284 stencil_bits
[2] = 8;
1285 num_depth_stencil_bits
= 3;
1289 stencil_bits
[1] = 8;
1292 new_configs
= driCreateConfigs(formats
[i
],
1295 num_depth_stencil_bits
,
1296 back_buffer_modes
, 2,
1297 singlesample_samples
, 1,
1299 configs
= driConcatConfigs(configs
, new_configs
);
1302 /* Generate the minimum possible set of configs that include an
1303 * accumulation buffer.
1305 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1306 __DRIconfig
**new_configs
;
1308 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1310 stencil_bits
[0] = 0;
1313 stencil_bits
[0] = 8;
1316 new_configs
= driCreateConfigs(formats
[i
],
1317 depth_bits
, stencil_bits
, 1,
1318 back_buffer_modes
, 1,
1319 singlesample_samples
, 1,
1321 configs
= driConcatConfigs(configs
, new_configs
);
1324 /* Generate multisample configs.
1326 * This loop breaks early, and hence is a no-op, on gen < 6.
1328 * Multisample configs must follow the singlesample configs in order to
1329 * work around an X server bug present in 1.12. The X server chooses to
1330 * associate the first listed RGBA888-Z24S8 config, regardless of its
1331 * sample count, with the 32-bit depth visual used for compositing.
1333 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1334 * supported. Singlebuffer configs are not supported because no one wants
1337 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1338 if (devinfo
->gen
< 6)
1341 __DRIconfig
**new_configs
;
1342 const int num_depth_stencil_bits
= 2;
1343 int num_msaa_modes
= 0;
1346 stencil_bits
[0] = 0;
1348 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1350 stencil_bits
[1] = 0;
1353 stencil_bits
[1] = 8;
1356 if (devinfo
->gen
>= 7)
1358 else if (devinfo
->gen
== 6)
1361 new_configs
= driCreateConfigs(formats
[i
],
1364 num_depth_stencil_bits
,
1365 back_buffer_modes
, 1,
1366 multisample_samples
,
1369 configs
= driConcatConfigs(configs
, new_configs
);
1372 if (configs
== NULL
) {
1373 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1382 set_max_gl_versions(struct intel_screen
*screen
)
1384 __DRIscreen
*psp
= screen
->driScrnPriv
;
1386 switch (screen
->devinfo
->gen
) {
1389 psp
->max_gl_core_version
= 33;
1390 psp
->max_gl_compat_version
= 30;
1391 psp
->max_gl_es1_version
= 11;
1392 psp
->max_gl_es2_version
= 31;
1396 psp
->max_gl_core_version
= 33;
1397 psp
->max_gl_compat_version
= 30;
1398 psp
->max_gl_es1_version
= 11;
1399 psp
->max_gl_es2_version
= 30;
1403 psp
->max_gl_core_version
= 0;
1404 psp
->max_gl_compat_version
= 21;
1405 psp
->max_gl_es1_version
= 11;
1406 psp
->max_gl_es2_version
= 20;
1409 unreachable("unrecognized intel_screen::gen");
1414 * Return the revision (generally the revid field of the PCI header) of the
1417 * XXX: This function is useful to keep around even if it is not currently in
1418 * use. It is necessary for new platforms and revision specific workarounds or
1419 * features. Please don't remove it so that we know it at least continues to
1422 static __attribute__((__unused__
)) int
1423 brw_get_revision(int fd
)
1425 struct drm_i915_getparam gp
;
1429 memset(&gp
, 0, sizeof(gp
));
1430 gp
.param
= I915_PARAM_REVISION
;
1431 gp
.value
= &revision
;
1433 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1440 /* Drop when RS headers get pulled to libdrm */
1441 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1442 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1446 * This is the driver specific part of the createNewScreen entry point.
1447 * Called when using DRI2.
1449 * \return the struct gl_config supported by this driver
1452 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1454 struct intel_screen
*intelScreen
;
1456 if (psp
->image
.loader
) {
1457 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1458 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1460 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1461 "support required\n");
1465 /* Allocate the private area */
1466 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1468 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1471 /* parse information in __driConfigOptions */
1472 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1474 intelScreen
->driScrnPriv
= psp
;
1475 psp
->driverPrivate
= (void *) intelScreen
;
1477 if (!intel_init_bufmgr(intelScreen
))
1480 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1481 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
);
1482 if (!intelScreen
->devinfo
)
1485 brw_process_intel_debug_variable();
1487 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1488 dri_bufmgr_set_debug(intelScreen
->bufmgr
, true);
1490 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && intelScreen
->devinfo
->gen
< 7) {
1492 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1493 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1496 if (INTEL_DEBUG
& DEBUG_AUB
)
1497 drm_intel_bufmgr_gem_set_aub_dump(intelScreen
->bufmgr
, true);
1499 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1500 intelScreen
->hw_has_timestamp
= intel_detect_timestamp(intelScreen
);
1502 /* GENs prior to 8 do not support EU/Subslice info */
1503 if (intelScreen
->devinfo
->gen
>= 8)
1504 intel_detect_sseu(intelScreen
);
1506 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1508 intelScreen
->winsys_msaa_samples_override
=
1509 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1510 printf("Forcing winsys sample count to %d\n",
1511 intelScreen
->winsys_msaa_samples_override
);
1513 intelScreen
->winsys_msaa_samples_override
= -1;
1516 set_max_gl_versions(intelScreen
);
1518 /* Notification of GPU resets requires hardware contexts and a kernel new
1519 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1520 * supported, calling it with a context of 0 will either generate EPERM or
1521 * no error. If the ioctl is not supported, it always generate EINVAL.
1522 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1523 * extension to the loader.
1525 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1527 if (intelScreen
->devinfo
->gen
>= 6) {
1528 struct drm_i915_reset_stats stats
;
1529 memset(&stats
, 0, sizeof(stats
));
1531 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1533 intelScreen
->has_context_reset_notification
=
1534 (ret
!= -1 || errno
!= EINVAL
);
1537 struct drm_i915_getparam getparam
;
1538 getparam
.param
= I915_PARAM_CMD_PARSER_VERSION
;
1539 getparam
.value
= &intelScreen
->cmd_parser_version
;
1540 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GETPARAM
, &getparam
);
1542 intelScreen
->cmd_parser_version
= 0;
1544 psp
->extensions
= !intelScreen
->has_context_reset_notification
1545 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1547 intelScreen
->compiler
= brw_compiler_create(intelScreen
,
1548 intelScreen
->devinfo
);
1549 intelScreen
->program_id
= 1;
1551 if (intelScreen
->devinfo
->has_resource_streamer
) {
1553 getparam
.param
= I915_PARAM_HAS_RESOURCE_STREAMER
;
1554 getparam
.value
= &val
;
1556 drmIoctl(psp
->fd
, DRM_IOCTL_I915_GETPARAM
, &getparam
);
1557 intelScreen
->has_resource_streamer
= val
> 0;
1560 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1563 struct intel_buffer
{
1568 static __DRIbuffer
*
1569 intelAllocateBuffer(__DRIscreen
*screen
,
1570 unsigned attachment
, unsigned format
,
1571 int width
, int height
)
1573 struct intel_buffer
*intelBuffer
;
1574 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1576 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1577 attachment
== __DRI_BUFFER_BACK_LEFT
);
1579 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1580 if (intelBuffer
== NULL
)
1583 /* The front and back buffers are color buffers, which are X tiled. */
1585 if (intelScreen
->devinfo
->gen
>= 9) {
1586 tiling
= I915_TILING_Y
;
1588 tiling
= I915_TILING_X
;
1590 unsigned long pitch
;
1591 int cpp
= format
/ 8;
1592 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1593 "intelAllocateBuffer",
1598 BO_ALLOC_FOR_RENDER
);
1600 if (intelBuffer
->bo
== NULL
) {
1605 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1607 intelBuffer
->base
.attachment
= attachment
;
1608 intelBuffer
->base
.cpp
= cpp
;
1609 intelBuffer
->base
.pitch
= pitch
;
1611 return &intelBuffer
->base
;
1615 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1617 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1619 drm_intel_bo_unreference(intelBuffer
->bo
);
1623 static const struct __DriverAPIRec brw_driver_api
= {
1624 .InitScreen
= intelInitScreen2
,
1625 .DestroyScreen
= intelDestroyScreen
,
1626 .CreateContext
= brwCreateContext
,
1627 .DestroyContext
= intelDestroyContext
,
1628 .CreateBuffer
= intelCreateBuffer
,
1629 .DestroyBuffer
= intelDestroyBuffer
,
1630 .MakeCurrent
= intelMakeCurrent
,
1631 .UnbindContext
= intelUnbindContext
,
1632 .AllocateBuffer
= intelAllocateBuffer
,
1633 .ReleaseBuffer
= intelReleaseBuffer
1636 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1637 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1638 .vtable
= &brw_driver_api
,
1641 static const __DRIextension
*brw_driver_extensions
[] = {
1642 &driCoreExtension
.base
,
1643 &driImageDriverExtension
.base
,
1644 &driDRI2Extension
.base
,
1646 &brw_config_options
.base
,
1650 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1652 globalDriverAPI
= &brw_driver_api
;
1654 return brw_driver_extensions
;