2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "brw_state.h"
41 #include "compiler/nir/nir.h"
44 #include "util/xmlpool.h"
46 static const __DRIconfigOptionsExtension brw_config_options
= {
47 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
50 DRI_CONF_SECTION_PERFORMANCE
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
60 DRI_CONF_MESA_NO_ERROR("false")
63 DRI_CONF_SECTION_QUALITY
64 DRI_CONF_FORCE_S3TC_ENABLE("false")
66 DRI_CONF_PRECISE_TRIG("false")
68 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
69 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
70 "given integer. If negative, then do not clamp.")
74 DRI_CONF_SECTION_DEBUG
75 DRI_CONF_NO_RAST("false")
76 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
77 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
78 DRI_CONF_DISABLE_THROTTLING("false")
79 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
80 DRI_CONF_FORCE_GLSL_VERSION(0)
81 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
82 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
83 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
84 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
85 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
86 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
87 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
89 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
90 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
94 DRI_CONF_SECTION_MISCELLANEOUS
95 DRI_CONF_GLSL_ZERO_INIT("false")
100 #include "intel_batchbuffer.h"
101 #include "intel_buffers.h"
102 #include "brw_bufmgr.h"
103 #include "intel_fbo.h"
104 #include "intel_mipmap_tree.h"
105 #include "intel_screen.h"
106 #include "intel_tex.h"
107 #include "intel_image.h"
109 #include "brw_context.h"
111 #include "i915_drm.h"
114 * For debugging purposes, this returns a time in seconds.
121 clock_gettime(CLOCK_MONOTONIC
, &tp
);
123 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
126 static const __DRItexBufferExtension intelTexBufferExtension
= {
127 .base
= { __DRI_TEX_BUFFER
, 3 },
129 .setTexBuffer
= intelSetTexBuffer
,
130 .setTexBuffer2
= intelSetTexBuffer2
,
131 .releaseTexBuffer
= NULL
,
135 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
136 __DRIdrawable
*dPriv
,
138 enum __DRI2throttleReason reason
)
140 struct brw_context
*brw
= cPriv
->driverPrivate
;
145 struct gl_context
*ctx
= &brw
->ctx
;
147 FLUSH_VERTICES(ctx
, 0);
149 if (flags
& __DRI2_FLUSH_DRAWABLE
)
150 intel_resolve_for_dri2_flush(brw
, dPriv
);
152 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
153 brw
->need_swap_throttle
= true;
154 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
155 brw
->need_flush_throttle
= true;
157 intel_batchbuffer_flush(brw
);
161 * Provides compatibility with loaders that only support the older (version
162 * 1-3) flush interface.
164 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
167 intel_dri2_flush(__DRIdrawable
*drawable
)
169 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
170 __DRI2_FLUSH_DRAWABLE
,
171 __DRI2_THROTTLE_SWAPBUFFER
);
174 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
175 .base
= { __DRI2_FLUSH
, 4 },
177 .flush
= intel_dri2_flush
,
178 .invalidate
= dri2InvalidateDrawable
,
179 .flush_with_flags
= intel_dri2_flush_with_flags
,
182 static const struct intel_image_format intel_image_formats
[] = {
183 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
184 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
186 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
187 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
189 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
190 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
192 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
193 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
195 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
198 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
201 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
204 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
207 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
210 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
213 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
216 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
218 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
219 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
221 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
223 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
226 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
228 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
231 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
236 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
270 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
271 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
272 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
274 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
275 * and treat them as planar buffers in the compositors.
276 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
277 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
278 * clusters and places pairs and places U into the G component and
279 * V into A. This lets the texture sampler interpolate the Y
280 * components correctly when sampling from plane 0, and interpolate
281 * U and V correctly when sampling from plane 1. */
282 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
284 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
285 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
286 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
287 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
290 static const struct {
293 } supported_modifiers
[] = {
294 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
295 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
296 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
297 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
301 modifier_is_supported(const struct gen_device_info
*devinfo
,
302 const struct intel_image_format
*fmt
, int dri_format
,
305 const struct isl_drm_modifier_info
*modinfo
=
306 isl_drm_modifier_get_info(modifier
);
309 /* ISL had better know about the modifier */
313 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
314 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
315 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
318 /* CCS_E is not supported for planar images */
319 if (fmt
&& fmt
->nplanes
> 1)
323 assert(dri_format
== 0);
324 dri_format
= fmt
->planes
[0].dri_format
;
327 mesa_format format
= driImageFormatToGLFormat(dri_format
);
328 format
= _mesa_get_srgb_format_linear(format
);
329 if (!isl_format_supports_ccs_e(devinfo
,
330 brw_isl_format_for_mesa_format(format
)))
334 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
335 if (supported_modifiers
[i
].modifier
!= modifier
)
338 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
345 tiling_to_modifier(uint32_t tiling
)
347 static const uint64_t map
[] = {
348 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
349 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
350 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
353 assert(tiling
< ARRAY_SIZE(map
));
359 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
361 uint32_t tiling
, swizzle
;
362 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
364 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
365 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
366 func
, image
->offset
);
370 static const struct intel_image_format
*
371 intel_image_format_lookup(int fourcc
)
373 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
374 if (intel_image_formats
[i
].fourcc
== fourcc
)
375 return &intel_image_formats
[i
];
381 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
383 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
384 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
385 *fourcc
= intel_image_formats
[i
].fourcc
;
393 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
398 image
= calloc(1, sizeof *image
);
402 image
->screen
= screen
;
403 image
->dri_format
= dri_format
;
406 image
->format
= driImageFormatToGLFormat(dri_format
);
407 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
408 image
->format
== MESA_FORMAT_NONE
) {
413 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
414 image
->data
= loaderPrivate
;
420 * Sets up a DRIImage structure to point to a slice out of a miptree.
423 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
424 struct intel_mipmap_tree
*mt
, GLuint level
,
427 intel_miptree_make_shareable(brw
, mt
);
429 intel_miptree_check_level_layer(mt
, level
, zoffset
);
431 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
432 level
- mt
->first_level
);
433 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
434 level
- mt
->first_level
);
435 image
->pitch
= mt
->surf
.row_pitch
;
437 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
441 brw_bo_unreference(image
->bo
);
443 brw_bo_reference(mt
->bo
);
447 intel_create_image_from_name(__DRIscreen
*dri_screen
,
448 int width
, int height
, int format
,
449 int name
, int pitch
, void *loaderPrivate
)
451 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
455 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
459 if (image
->format
== MESA_FORMAT_NONE
)
462 cpp
= _mesa_get_format_bytes(image
->format
);
464 image
->width
= width
;
465 image
->height
= height
;
466 image
->pitch
= pitch
* cpp
;
467 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
473 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
479 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
480 int renderbuffer
, void *loaderPrivate
)
483 struct brw_context
*brw
= context
->driverPrivate
;
484 struct gl_context
*ctx
= &brw
->ctx
;
485 struct gl_renderbuffer
*rb
;
486 struct intel_renderbuffer
*irb
;
488 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
490 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
494 irb
= intel_renderbuffer(rb
);
495 intel_miptree_make_shareable(brw
, irb
->mt
);
496 image
= calloc(1, sizeof *image
);
500 image
->internal_format
= rb
->InternalFormat
;
501 image
->format
= rb
->Format
;
502 image
->modifier
= tiling_to_modifier(
503 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
505 image
->data
= loaderPrivate
;
506 brw_bo_unreference(image
->bo
);
507 image
->bo
= irb
->mt
->bo
;
508 brw_bo_reference(irb
->mt
->bo
);
509 image
->width
= rb
->Width
;
510 image
->height
= rb
->Height
;
511 image
->pitch
= irb
->mt
->surf
.row_pitch
;
512 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
513 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
515 rb
->NeedsFinishRenderTexture
= true;
520 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
521 unsigned texture
, int zoffset
,
527 struct brw_context
*brw
= context
->driverPrivate
;
528 struct gl_texture_object
*obj
;
529 struct intel_texture_object
*iobj
;
532 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
533 if (!obj
|| obj
->Target
!= target
) {
534 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
538 if (target
== GL_TEXTURE_CUBE_MAP
)
541 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
542 iobj
= intel_texture_object(obj
);
543 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
544 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
548 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
549 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
553 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
554 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
557 image
= calloc(1, sizeof *image
);
559 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
563 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
564 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
565 image
->modifier
= tiling_to_modifier(
566 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
567 image
->data
= loaderPrivate
;
568 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
569 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
570 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
571 if (image
->dri_format
== MESA_FORMAT_NONE
) {
572 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
577 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
582 intel_destroy_image(__DRIimage
*image
)
584 brw_bo_unreference(image
->bo
);
588 enum modifier_priority
{
589 MODIFIER_PRIORITY_INVALID
= 0,
590 MODIFIER_PRIORITY_LINEAR
,
593 MODIFIER_PRIORITY_Y_CCS
,
596 const uint64_t priority_to_modifier
[] = {
597 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
598 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
599 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
600 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
601 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
605 select_best_modifier(struct gen_device_info
*devinfo
,
607 const uint64_t *modifiers
,
608 const unsigned count
)
610 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
612 for (int i
= 0; i
< count
; i
++) {
613 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
616 switch (modifiers
[i
]) {
617 case I915_FORMAT_MOD_Y_TILED_CCS
:
618 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
620 case I915_FORMAT_MOD_Y_TILED
:
621 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
623 case I915_FORMAT_MOD_X_TILED
:
624 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
626 case DRM_FORMAT_MOD_LINEAR
:
627 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
629 case DRM_FORMAT_MOD_INVALID
:
635 return priority_to_modifier
[prio
];
639 intel_create_image_common(__DRIscreen
*dri_screen
,
640 int width
, int height
, int format
,
642 const uint64_t *modifiers
,
647 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
648 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
651 /* Callers of this may specify a modifier, or a dri usage, but not both. The
652 * newer modifier interface deprecates the older usage flags newer modifier
653 * interface deprecates the older usage flags.
655 assert(!(use
&& count
));
657 if (use
& __DRI_IMAGE_USE_CURSOR
) {
658 if (width
!= 64 || height
!= 64)
660 modifier
= DRM_FORMAT_MOD_LINEAR
;
663 if (use
& __DRI_IMAGE_USE_LINEAR
)
664 modifier
= DRM_FORMAT_MOD_LINEAR
;
666 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
668 /* User requested specific modifiers */
669 modifier
= select_best_modifier(&screen
->devinfo
, format
,
671 if (modifier
== DRM_FORMAT_MOD_INVALID
)
674 /* Historically, X-tiled was the default, and so lack of modifier means
677 modifier
= I915_FORMAT_MOD_X_TILED
;
681 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
685 const struct isl_drm_modifier_info
*mod_info
=
686 isl_drm_modifier_get_info(modifier
);
688 struct isl_surf surf
;
689 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
690 .dim
= ISL_SURF_DIM_2D
,
691 .format
= brw_isl_format_for_mesa_format(image
->format
),
698 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
699 ISL_SURF_USAGE_TEXTURE_BIT
|
700 ISL_SURF_USAGE_STORAGE_BIT
,
701 .tiling_flags
= (1 << mod_info
->tiling
));
708 struct isl_surf aux_surf
;
709 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
710 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
716 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
720 /* We request that the bufmgr zero the buffer for us for two reasons:
722 * 1) If a buffer gets re-used from the pool, we don't want to leak random
723 * garbage from our process to some other.
725 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
726 * a valid state. A CCS value of 0 indicates that the given block is
727 * in the pass-through state which is what we want.
729 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
730 surf
.size
+ aux_surf
.size
,
731 isl_tiling_to_i915_tiling(mod_info
->tiling
),
732 surf
.row_pitch
, BO_ALLOC_ZEROED
);
733 if (image
->bo
== NULL
) {
737 image
->width
= width
;
738 image
->height
= height
;
739 image
->pitch
= surf
.row_pitch
;
740 image
->modifier
= modifier
;
743 image
->aux_offset
= surf
.size
;
744 image
->aux_pitch
= aux_surf
.row_pitch
;
751 intel_create_image(__DRIscreen
*dri_screen
,
752 int width
, int height
, int format
,
756 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
761 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
762 int width
, int height
, int format
,
763 const uint64_t *modifiers
,
764 const unsigned count
,
767 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
768 modifiers
, count
, loaderPrivate
);
772 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
775 case __DRI_IMAGE_ATTRIB_STRIDE
:
776 *value
= image
->pitch
;
778 case __DRI_IMAGE_ATTRIB_HANDLE
:
779 *value
= image
->bo
->gem_handle
;
781 case __DRI_IMAGE_ATTRIB_NAME
:
782 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
783 case __DRI_IMAGE_ATTRIB_FORMAT
:
784 *value
= image
->dri_format
;
786 case __DRI_IMAGE_ATTRIB_WIDTH
:
787 *value
= image
->width
;
789 case __DRI_IMAGE_ATTRIB_HEIGHT
:
790 *value
= image
->height
;
792 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
793 if (image
->planar_format
== NULL
)
795 *value
= image
->planar_format
->components
;
797 case __DRI_IMAGE_ATTRIB_FD
:
798 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
799 case __DRI_IMAGE_ATTRIB_FOURCC
:
800 return intel_lookup_fourcc(image
->dri_format
, value
);
801 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
802 if (isl_drm_modifier_has_aux(image
->modifier
)) {
803 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
805 } else if (image
->planar_format
) {
806 *value
= image
->planar_format
->nplanes
;
811 case __DRI_IMAGE_ATTRIB_OFFSET
:
812 *value
= image
->offset
;
814 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
815 *value
= (image
->modifier
& 0xffffffff);
817 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
818 *value
= ((image
->modifier
>> 32) & 0xffffffff);
827 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
828 uint32_t fourcc
, uint64_t modifier
,
829 int attrib
, uint64_t *value
)
831 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
832 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
834 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
838 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
839 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
848 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
852 image
= calloc(1, sizeof *image
);
856 brw_bo_reference(orig_image
->bo
);
857 image
->bo
= orig_image
->bo
;
858 image
->internal_format
= orig_image
->internal_format
;
859 image
->planar_format
= orig_image
->planar_format
;
860 image
->dri_format
= orig_image
->dri_format
;
861 image
->format
= orig_image
->format
;
862 image
->modifier
= orig_image
->modifier
;
863 image
->offset
= orig_image
->offset
;
864 image
->width
= orig_image
->width
;
865 image
->height
= orig_image
->height
;
866 image
->pitch
= orig_image
->pitch
;
867 image
->tile_x
= orig_image
->tile_x
;
868 image
->tile_y
= orig_image
->tile_y
;
869 image
->has_depthstencil
= orig_image
->has_depthstencil
;
870 image
->data
= loaderPrivate
;
872 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
873 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
879 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
881 if (use
& __DRI_IMAGE_USE_CURSOR
) {
882 if (image
->width
!= 64 || image
->height
!= 64)
890 intel_create_image_from_names(__DRIscreen
*dri_screen
,
891 int width
, int height
, int fourcc
,
892 int *names
, int num_names
,
893 int *strides
, int *offsets
,
896 const struct intel_image_format
*f
= NULL
;
900 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
903 f
= intel_image_format_lookup(fourcc
);
907 image
= intel_create_image_from_name(dri_screen
, width
, height
,
908 __DRI_IMAGE_FORMAT_NONE
,
909 names
[0], strides
[0],
915 image
->planar_format
= f
;
916 for (i
= 0; i
< f
->nplanes
; i
++) {
917 index
= f
->planes
[i
].buffer_index
;
918 image
->offsets
[index
] = offsets
[index
];
919 image
->strides
[index
] = strides
[index
];
926 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
927 int width
, int height
, int fourcc
,
928 uint64_t modifier
, int *fds
, int num_fds
,
929 int *strides
, int *offsets
,
932 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
933 const struct intel_image_format
*f
;
938 if (fds
== NULL
|| num_fds
< 1)
941 f
= intel_image_format_lookup(fourcc
);
945 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
946 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
950 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
953 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
959 image
->width
= width
;
960 image
->height
= height
;
961 image
->pitch
= strides
[0];
963 image
->planar_format
= f
;
965 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
966 if (image
->bo
== NULL
) {
971 /* We only support all planes from the same bo.
972 * brw_bo_gem_create_from_prime() should return the same pointer for all
973 * fds received here */
974 for (i
= 1; i
< num_fds
; i
++) {
975 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
976 brw_bo_unreference(aux
);
977 if (aux
!= image
->bo
) {
978 brw_bo_unreference(image
->bo
);
984 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
985 image
->modifier
= modifier
;
987 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
989 const struct isl_drm_modifier_info
*mod_info
=
990 isl_drm_modifier_get_info(image
->modifier
);
993 struct isl_surf surf
;
994 for (i
= 0; i
< f
->nplanes
; i
++) {
995 index
= f
->planes
[i
].buffer_index
;
996 image
->offsets
[index
] = offsets
[index
];
997 image
->strides
[index
] = strides
[index
];
999 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1001 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1002 .dim
= ISL_SURF_DIM_2D
,
1003 .format
= brw_isl_format_for_mesa_format(format
),
1004 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1005 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1010 .row_pitch
= strides
[index
],
1011 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1012 ISL_SURF_USAGE_TEXTURE_BIT
|
1013 ISL_SURF_USAGE_STORAGE_BIT
,
1014 .tiling_flags
= (1 << mod_info
->tiling
));
1016 brw_bo_unreference(image
->bo
);
1021 const int end
= offsets
[index
] + surf
.size
;
1026 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1027 /* Even though we initialize surf in the loop above, we know that
1028 * anything with CCS_E will have exactly one plane so surf is properly
1029 * initialized when we get here.
1031 assert(f
->nplanes
== 1);
1033 image
->aux_offset
= offsets
[1];
1034 image
->aux_pitch
= strides
[1];
1036 /* Scanout hardware requires that the CCS be placed after the main
1037 * surface in memory. We consider any CCS that is placed any earlier in
1038 * memory to be invalid and reject it.
1040 * At some point in the future, this restriction may be relaxed if the
1041 * hardware becomes less strict but we may need a new modifier for that.
1044 if (image
->aux_offset
< size
) {
1045 brw_bo_unreference(image
->bo
);
1050 struct isl_surf aux_surf
;
1051 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1054 brw_bo_unreference(image
->bo
);
1059 const int end
= image
->aux_offset
+ aux_surf
.size
;
1063 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1066 /* Check that the requested image actually fits within the BO. 'size'
1067 * is already relative to the offsets, so we don't need to add that. */
1068 if (image
->bo
->size
== 0) {
1069 image
->bo
->size
= size
;
1070 } else if (size
> image
->bo
->size
) {
1071 brw_bo_unreference(image
->bo
);
1076 if (f
->nplanes
== 1) {
1077 image
->offset
= image
->offsets
[0];
1078 intel_image_warn_if_unaligned(image
, __func__
);
1085 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1086 int width
, int height
, int fourcc
,
1087 int *fds
, int num_fds
, int *strides
, int *offsets
,
1088 void *loaderPrivate
)
1090 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1091 DRM_FORMAT_MOD_INVALID
,
1092 fds
, num_fds
, strides
, offsets
,
1097 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1098 int width
, int height
,
1099 int fourcc
, uint64_t modifier
,
1100 int *fds
, int num_fds
,
1101 int *strides
, int *offsets
,
1102 enum __DRIYUVColorSpace yuv_color_space
,
1103 enum __DRISampleRange sample_range
,
1104 enum __DRIChromaSiting horizontal_siting
,
1105 enum __DRIChromaSiting vertical_siting
,
1107 void *loaderPrivate
)
1110 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1113 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1117 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1119 fds
, num_fds
, strides
, offsets
,
1123 * Invalid parameters and any inconsistencies between are assumed to be
1124 * checked by the caller. Therefore besides unsupported formats one can fail
1125 * only in allocation.
1128 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1132 image
->dma_buf_imported
= true;
1133 image
->yuv_color_space
= yuv_color_space
;
1134 image
->sample_range
= sample_range
;
1135 image
->horizontal_siting
= horizontal_siting
;
1136 image
->vertical_siting
= vertical_siting
;
1138 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1143 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1144 int width
, int height
, int fourcc
,
1145 int *fds
, int num_fds
,
1146 int *strides
, int *offsets
,
1147 enum __DRIYUVColorSpace yuv_color_space
,
1148 enum __DRISampleRange sample_range
,
1149 enum __DRIChromaSiting horizontal_siting
,
1150 enum __DRIChromaSiting vertical_siting
,
1152 void *loaderPrivate
)
1154 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1155 fourcc
, DRM_FORMAT_MOD_INVALID
,
1156 fds
, num_fds
, strides
, offsets
,
1166 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1167 int *formats
, int *count
)
1172 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1176 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1177 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1179 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1187 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1188 uint64_t *modifiers
,
1189 unsigned int *external_only
,
1192 struct intel_screen
*screen
= _screen
->driverPrivate
;
1193 const struct intel_image_format
*f
;
1194 int num_mods
= 0, i
;
1196 f
= intel_image_format_lookup(fourcc
);
1200 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1201 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1202 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1209 modifiers
[num_mods
- 1] = modifier
;
1210 if (num_mods
>= max
)
1214 if (external_only
!= NULL
) {
1215 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1216 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1217 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1218 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1219 external_only
[i
] = GL_TRUE
;
1222 external_only
[i
] = GL_FALSE
;
1232 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1234 int width
, height
, offset
, stride
, dri_format
, index
;
1235 const struct intel_image_format
*f
;
1238 if (parent
== NULL
) {
1240 } else if (parent
->planar_format
== NULL
) {
1242 isl_drm_modifier_has_aux(parent
->modifier
) && plane
== 1;
1246 width
= parent
->width
;
1247 height
= parent
->height
;
1248 dri_format
= parent
->dri_format
;
1249 offset
= parent
->aux_offset
;
1250 stride
= parent
->aux_pitch
;
1252 /* Planar formats don't support aux buffers/images */
1253 assert(!isl_drm_modifier_has_aux(parent
->modifier
));
1254 f
= parent
->planar_format
;
1256 if (plane
>= f
->nplanes
)
1259 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
1260 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
1261 dri_format
= f
->planes
[plane
].dri_format
;
1262 index
= f
->planes
[plane
].buffer_index
;
1263 offset
= parent
->offsets
[index
];
1264 stride
= parent
->strides
[index
];
1266 if (offset
+ height
* stride
> parent
->bo
->size
) {
1267 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
1272 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1276 image
->bo
= parent
->bo
;
1277 brw_bo_reference(parent
->bo
);
1278 image
->modifier
= parent
->modifier
;
1280 image
->width
= width
;
1281 image
->height
= height
;
1282 image
->pitch
= stride
;
1283 image
->offset
= offset
;
1285 intel_image_warn_if_unaligned(image
, __func__
);
1290 static const __DRIimageExtension intelImageExtension
= {
1291 .base
= { __DRI_IMAGE
, 16 },
1293 .createImageFromName
= intel_create_image_from_name
,
1294 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1295 .destroyImage
= intel_destroy_image
,
1296 .createImage
= intel_create_image
,
1297 .queryImage
= intel_query_image
,
1298 .dupImage
= intel_dup_image
,
1299 .validateUsage
= intel_validate_usage
,
1300 .createImageFromNames
= intel_create_image_from_names
,
1301 .fromPlanar
= intel_from_planar
,
1302 .createImageFromTexture
= intel_create_image_from_texture
,
1303 .createImageFromFds
= intel_create_image_from_fds
,
1304 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1306 .getCapabilities
= NULL
,
1309 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1310 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1311 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1312 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1313 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1317 get_aperture_size(int fd
)
1319 struct drm_i915_gem_get_aperture aperture
;
1321 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1324 return aperture
.aper_size
;
1328 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1329 int param
, unsigned int *value
)
1331 const struct intel_screen
*const screen
=
1332 (struct intel_screen
*) dri_screen
->driverPrivate
;
1335 case __DRI2_RENDERER_VENDOR_ID
:
1338 case __DRI2_RENDERER_DEVICE_ID
:
1339 value
[0] = screen
->deviceID
;
1341 case __DRI2_RENDERER_ACCELERATED
:
1344 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1345 /* Once a batch uses more than 75% of the maximum mappable size, we
1346 * assume that there's some fragmentation, and we start doing extra
1347 * flushing, etc. That's the big cliff apps will care about.
1349 const unsigned gpu_mappable_megabytes
=
1350 screen
->aperture_threshold
/ (1024 * 1024);
1352 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1353 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1355 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1358 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1359 * (uint64_t) system_page_size
;
1361 const unsigned system_memory_megabytes
=
1362 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1364 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1367 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1370 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1374 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1381 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1382 int param
, const char **value
)
1384 const struct intel_screen
*screen
=
1385 (struct intel_screen
*) dri_screen
->driverPrivate
;
1388 case __DRI2_RENDERER_VENDOR_ID
:
1389 value
[0] = brw_vendor_string
;
1391 case __DRI2_RENDERER_DEVICE_ID
:
1392 value
[0] = brw_get_renderer_string(screen
);
1401 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1402 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1404 .queryInteger
= brw_query_renderer_integer
,
1405 .queryString
= brw_query_renderer_string
1408 static const __DRIrobustnessExtension dri2Robustness
= {
1409 .base
= { __DRI2_ROBUSTNESS
, 1 }
1412 static const __DRIextension
*screenExtensions
[] = {
1413 &intelTexBufferExtension
.base
,
1414 &intelFenceExtension
.base
,
1415 &intelFlushExtension
.base
,
1416 &intelImageExtension
.base
,
1417 &intelRendererQueryExtension
.base
,
1418 &dri2ConfigQueryExtension
.base
,
1419 &dri2NoErrorExtension
.base
,
1423 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1424 &intelTexBufferExtension
.base
,
1425 &intelFenceExtension
.base
,
1426 &intelFlushExtension
.base
,
1427 &intelImageExtension
.base
,
1428 &intelRendererQueryExtension
.base
,
1429 &dri2ConfigQueryExtension
.base
,
1430 &dri2Robustness
.base
,
1431 &dri2NoErrorExtension
.base
,
1436 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1439 struct drm_i915_getparam gp
;
1441 memset(&gp
, 0, sizeof(gp
));
1445 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1448 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1455 intel_get_boolean(struct intel_screen
*screen
, int param
)
1458 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1462 intel_get_integer(struct intel_screen
*screen
, int param
)
1466 if (intel_get_param(screen
, param
, &value
) == 0)
1473 intelDestroyScreen(__DRIscreen
* sPriv
)
1475 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1477 brw_bufmgr_destroy(screen
->bufmgr
);
1478 driDestroyOptionInfo(&screen
->optionCache
);
1480 ralloc_free(screen
);
1481 sPriv
->driverPrivate
= NULL
;
1486 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1488 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1489 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1490 * this does not allocate GPU memory.
1493 intelCreateBuffer(__DRIscreen
*dri_screen
,
1494 __DRIdrawable
* driDrawPriv
,
1495 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1497 struct intel_renderbuffer
*rb
;
1498 struct intel_screen
*screen
= (struct intel_screen
*)
1499 dri_screen
->driverPrivate
;
1500 mesa_format rgbFormat
;
1501 unsigned num_samples
=
1502 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1507 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1511 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1513 if (screen
->winsys_msaa_samples_override
!= -1) {
1514 num_samples
= screen
->winsys_msaa_samples_override
;
1515 fb
->Visual
.samples
= num_samples
;
1518 if (mesaVis
->redBits
== 5) {
1519 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1520 : MESA_FORMAT_B5G6R5_UNORM
;
1521 } else if (mesaVis
->sRGBCapable
) {
1522 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1523 : MESA_FORMAT_B8G8R8A8_SRGB
;
1524 } else if (mesaVis
->alphaBits
== 0) {
1525 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1526 : MESA_FORMAT_B8G8R8X8_UNORM
;
1528 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1529 : MESA_FORMAT_B8G8R8A8_SRGB
;
1530 fb
->Visual
.sRGBCapable
= true;
1533 /* setup the hardware-based renderbuffers */
1534 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1535 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1537 if (mesaVis
->doubleBufferMode
) {
1538 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1539 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1543 * Assert here that the gl_config has an expected depth/stencil bit
1544 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1545 * which constructs the advertised configs.)
1547 if (mesaVis
->depthBits
== 24) {
1548 assert(mesaVis
->stencilBits
== 8);
1550 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1551 rb
= intel_create_private_renderbuffer(screen
,
1552 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1554 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1555 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1557 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1560 * Use combined depth/stencil. Note that the renderbuffer is
1561 * attached to two attachment points.
1563 rb
= intel_create_private_renderbuffer(screen
,
1564 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1566 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1567 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1570 else if (mesaVis
->depthBits
== 16) {
1571 assert(mesaVis
->stencilBits
== 0);
1572 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1574 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1577 assert(mesaVis
->depthBits
== 0);
1578 assert(mesaVis
->stencilBits
== 0);
1581 /* now add any/all software-based renderbuffers we may need */
1582 _swrast_add_soft_renderbuffers(fb
,
1583 false, /* never sw color */
1584 false, /* never sw depth */
1585 false, /* never sw stencil */
1586 mesaVis
->accumRedBits
> 0,
1587 false, /* never sw alpha */
1588 false /* never sw aux */ );
1589 driDrawPriv
->driverPrivate
= fb
;
1595 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1597 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1599 _mesa_reference_framebuffer(&fb
, NULL
);
1603 intel_detect_sseu(struct intel_screen
*screen
)
1605 assert(screen
->devinfo
.gen
>= 8);
1608 screen
->subslice_total
= -1;
1609 screen
->eu_total
= -1;
1611 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1612 &screen
->subslice_total
);
1613 if (ret
< 0 && ret
!= -EINVAL
)
1616 ret
= intel_get_param(screen
,
1617 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1618 if (ret
< 0 && ret
!= -EINVAL
)
1621 /* Without this information, we cannot get the right Braswell brandstrings,
1622 * and we have to use conservative numbers for GPGPU on many platforms, but
1623 * otherwise, things will just work.
1625 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1627 "Kernel 4.1 required to properly query GPU properties.\n");
1632 screen
->subslice_total
= -1;
1633 screen
->eu_total
= -1;
1634 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1638 intel_init_bufmgr(struct intel_screen
*screen
)
1640 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1642 if (getenv("INTEL_NO_HW") != NULL
)
1643 screen
->no_hw
= true;
1645 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1646 if (screen
->bufmgr
== NULL
) {
1647 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1648 __func__
, __LINE__
);
1652 if (!intel_get_boolean(screen
, I915_PARAM_HAS_WAIT_TIMEOUT
)) {
1653 fprintf(stderr
, "[%s: %u] Kernel 3.6 required.\n", __func__
, __LINE__
);
1661 intel_detect_swizzling(struct intel_screen
*screen
)
1663 struct brw_bo
*buffer
;
1665 uint32_t aligned_pitch
;
1666 uint32_t tiling
= I915_TILING_X
;
1667 uint32_t swizzle_mode
= 0;
1669 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1670 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1674 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1675 brw_bo_unreference(buffer
);
1677 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1684 intel_detect_timestamp(struct intel_screen
*screen
)
1686 uint64_t dummy
= 0, last
= 0;
1687 int upper
, lower
, loops
;
1689 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1690 * TIMESTAMP register being shifted and the low 32bits always zero.
1692 * More recent kernels offer an interface to read the full 36bits
1695 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1698 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1699 * upper 32bits for a rapidly changing timestamp.
1701 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1705 for (loops
= 0; loops
< 10; loops
++) {
1706 /* The TIMESTAMP should change every 80ns, so several round trips
1707 * through the kernel should be enough to advance it.
1709 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1712 upper
+= (dummy
>> 32) != (last
>> 32);
1713 if (upper
> 1) /* beware 32bit counter overflow */
1714 return 2; /* upper dword holds the low 32bits of the timestamp */
1716 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1718 return 1; /* timestamp is unshifted */
1723 /* No advancement? No timestamp! */
1728 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1730 * Some combinations of hardware and kernel versions allow this feature,
1731 * while others don't. Instead of trying to enumerate every case, just
1732 * try and write a register and see if works.
1735 intel_detect_pipelined_register(struct intel_screen
*screen
,
1736 int reg
, uint32_t expected_value
, bool reset
)
1741 struct brw_bo
*results
, *bo
;
1743 uint32_t offset
= 0;
1745 bool success
= false;
1747 /* Create a zero'ed temporary buffer for reading our results */
1748 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1749 if (results
== NULL
)
1752 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1756 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1762 /* Write the register. */
1763 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1765 *batch
++ = expected_value
;
1767 /* Save the register's value back to the buffer. */
1768 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1770 struct drm_i915_gem_relocation_entry reloc
= {
1771 .offset
= (char *) batch
- (char *) map
,
1772 .delta
= offset
* sizeof(uint32_t),
1773 .target_handle
= results
->gem_handle
,
1774 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1775 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1777 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1779 /* And afterwards clear the register */
1781 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1786 *batch
++ = MI_BATCH_BUFFER_END
;
1788 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1790 .handle
= results
->gem_handle
,
1793 .handle
= bo
->gem_handle
,
1794 .relocation_count
= 1,
1795 .relocs_ptr
= (uintptr_t) &reloc
,
1799 struct drm_i915_gem_execbuffer2 execbuf
= {
1800 .buffers_ptr
= (uintptr_t) exec_objects
,
1802 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1803 .flags
= I915_EXEC_RENDER
,
1806 /* Don't bother with error checking - if the execbuf fails, the
1807 * value won't be written and we'll just report that there's no access.
1809 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1810 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1812 /* Check whether the value got written. */
1813 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1815 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1816 brw_bo_unmap(results
);
1820 brw_bo_unreference(bo
);
1822 brw_bo_unreference(results
);
1828 intel_detect_pipelined_so(struct intel_screen
*screen
)
1830 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1832 /* Supposedly, Broadwell just works. */
1833 if (devinfo
->gen
>= 8)
1836 if (devinfo
->gen
<= 6)
1839 /* See the big explanation about command parser versions below */
1840 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1843 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1844 * statistics registers), and we already reset it to zero before using it.
1846 return intel_detect_pipelined_register(screen
,
1847 GEN7_SO_WRITE_OFFSET(0),
1853 * Return array of MSAA modes supported by the hardware. The array is
1854 * zero-terminated and sorted in decreasing order.
1857 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1859 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1860 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1861 static const int gen7_modes
[] = {8, 4, 0, -1};
1862 static const int gen6_modes
[] = {4, 0, -1};
1863 static const int gen4_modes
[] = {0, -1};
1865 if (screen
->devinfo
.gen
>= 9) {
1867 } else if (screen
->devinfo
.gen
>= 8) {
1869 } else if (screen
->devinfo
.gen
>= 7) {
1871 } else if (screen
->devinfo
.gen
== 6) {
1879 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
1881 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
1882 dri_screen
->dri2
.loader
->getCapability
)
1883 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
1885 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
1886 dri_screen
->image
.loader
->getCapability
)
1887 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
1892 static __DRIconfig
**
1893 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1895 static const mesa_format formats
[] = {
1896 MESA_FORMAT_B5G6R5_UNORM
,
1897 MESA_FORMAT_B8G8R8A8_UNORM
,
1898 MESA_FORMAT_B8G8R8X8_UNORM
,
1900 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
1901 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
1902 * server may disagree on which format the GLXFBConfig represents,
1903 * resulting in swapped color channels.
1905 * The problem, as of 2017-05-30:
1906 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
1907 * order and chooses the first __DRIconfig with the expected channel
1908 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
1909 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
1911 * EGL does not suffer from this problem. It correctly compares the
1912 * channel masks when matching EGLConfig to __DRIconfig.
1915 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
1916 MESA_FORMAT_R8G8B8A8_UNORM
,
1918 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
1919 MESA_FORMAT_R8G8B8X8_UNORM
,
1922 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1923 static const GLenum back_buffer_modes
[] = {
1924 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
1927 static const uint8_t singlesample_samples
[1] = {0};
1929 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1930 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1931 uint8_t depth_bits
[4], stencil_bits
[4];
1932 __DRIconfig
**configs
= NULL
;
1934 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
1935 unsigned num_formats
;
1936 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
1937 num_formats
= ARRAY_SIZE(formats
);
1941 /* Generate singlesample configs without accumulation buffer. */
1942 for (unsigned i
= 0; i
< num_formats
; i
++) {
1943 __DRIconfig
**new_configs
;
1944 int num_depth_stencil_bits
= 2;
1946 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1947 * buffer that has a different number of bits per pixel than the color
1948 * buffer, gen >= 6 supports this.
1951 stencil_bits
[0] = 0;
1953 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1955 stencil_bits
[1] = 0;
1956 if (devinfo
->gen
>= 6) {
1958 stencil_bits
[2] = 8;
1959 num_depth_stencil_bits
= 3;
1963 stencil_bits
[1] = 8;
1966 new_configs
= driCreateConfigs(formats
[i
],
1969 num_depth_stencil_bits
,
1970 back_buffer_modes
, 2,
1971 singlesample_samples
, 1,
1973 configs
= driConcatConfigs(configs
, new_configs
);
1976 /* Generate the minimum possible set of configs that include an
1977 * accumulation buffer.
1979 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1980 __DRIconfig
**new_configs
;
1982 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1984 stencil_bits
[0] = 0;
1987 stencil_bits
[0] = 8;
1990 new_configs
= driCreateConfigs(formats
[i
],
1991 depth_bits
, stencil_bits
, 1,
1992 back_buffer_modes
, 1,
1993 singlesample_samples
, 1,
1995 configs
= driConcatConfigs(configs
, new_configs
);
1998 /* Generate multisample configs.
2000 * This loop breaks early, and hence is a no-op, on gen < 6.
2002 * Multisample configs must follow the singlesample configs in order to
2003 * work around an X server bug present in 1.12. The X server chooses to
2004 * associate the first listed RGBA888-Z24S8 config, regardless of its
2005 * sample count, with the 32-bit depth visual used for compositing.
2007 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2008 * supported. Singlebuffer configs are not supported because no one wants
2011 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
2012 if (devinfo
->gen
< 6)
2015 __DRIconfig
**new_configs
;
2016 const int num_depth_stencil_bits
= 2;
2017 int num_msaa_modes
= 0;
2018 const uint8_t *multisample_samples
= NULL
;
2021 stencil_bits
[0] = 0;
2023 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2025 stencil_bits
[1] = 0;
2028 stencil_bits
[1] = 8;
2031 if (devinfo
->gen
>= 9) {
2032 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2033 multisample_samples
= multisample_samples_gen9
;
2034 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2035 } else if (devinfo
->gen
== 8) {
2036 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2037 multisample_samples
= multisample_samples_gen8
;
2038 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2039 } else if (devinfo
->gen
== 7) {
2040 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2041 multisample_samples
= multisample_samples_gen7
;
2042 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2043 } else if (devinfo
->gen
== 6) {
2044 static const uint8_t multisample_samples_gen6
[] = {4};
2045 multisample_samples
= multisample_samples_gen6
;
2046 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2049 new_configs
= driCreateConfigs(formats
[i
],
2052 num_depth_stencil_bits
,
2053 back_buffer_modes
, 1,
2054 multisample_samples
,
2057 configs
= driConcatConfigs(configs
, new_configs
);
2060 if (configs
== NULL
) {
2061 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2070 set_max_gl_versions(struct intel_screen
*screen
)
2072 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2073 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2075 switch (screen
->devinfo
.gen
) {
2079 dri_screen
->max_gl_core_version
= 45;
2080 dri_screen
->max_gl_compat_version
= 30;
2081 dri_screen
->max_gl_es1_version
= 11;
2082 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2085 dri_screen
->max_gl_core_version
= 33;
2086 if (can_do_pipelined_register_writes(screen
)) {
2087 dri_screen
->max_gl_core_version
= 42;
2088 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2089 dri_screen
->max_gl_core_version
= 43;
2090 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2091 dri_screen
->max_gl_core_version
= 45;
2093 dri_screen
->max_gl_compat_version
= 30;
2094 dri_screen
->max_gl_es1_version
= 11;
2095 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2098 dri_screen
->max_gl_core_version
= 33;
2099 dri_screen
->max_gl_compat_version
= 30;
2100 dri_screen
->max_gl_es1_version
= 11;
2101 dri_screen
->max_gl_es2_version
= 30;
2105 dri_screen
->max_gl_core_version
= 0;
2106 dri_screen
->max_gl_compat_version
= 21;
2107 dri_screen
->max_gl_es1_version
= 11;
2108 dri_screen
->max_gl_es2_version
= 20;
2111 unreachable("unrecognized intel_screen::gen");
2116 * Return the revision (generally the revid field of the PCI header) of the
2119 * XXX: This function is useful to keep around even if it is not currently in
2120 * use. It is necessary for new platforms and revision specific workarounds or
2121 * features. Please don't remove it so that we know it at least continues to
2124 static __attribute__((__unused__
)) int
2125 brw_get_revision(int fd
)
2127 struct drm_i915_getparam gp
;
2131 memset(&gp
, 0, sizeof(gp
));
2132 gp
.param
= I915_PARAM_REVISION
;
2133 gp
.value
= &revision
;
2135 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2143 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2145 struct brw_context
*brw
= (struct brw_context
*)data
;
2148 va_start(args
, fmt
);
2150 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2151 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2152 MESA_DEBUG_TYPE_OTHER
,
2153 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2158 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2160 struct brw_context
*brw
= (struct brw_context
*)data
;
2163 va_start(args
, fmt
);
2165 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2167 va_copy(args_copy
, args
);
2168 vfprintf(stderr
, fmt
, args_copy
);
2172 if (brw
->perf_debug
) {
2174 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2175 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2176 MESA_DEBUG_TYPE_PERFORMANCE
,
2177 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2183 parse_devid_override(const char *devid_override
)
2185 static const struct {
2202 for (unsigned i
= 0; i
< ARRAY_SIZE(name_map
); i
++) {
2203 if (!strcmp(name_map
[i
].name
, devid_override
))
2204 return name_map
[i
].pci_id
;
2207 return strtol(devid_override
, NULL
, 0);
2211 * Get the PCI ID for the device. This can be overridden by setting the
2212 * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
2214 * Returns -1 on ioctl failure.
2217 get_pci_device_id(struct intel_screen
*screen
)
2219 if (geteuid() == getuid()) {
2220 char *devid_override
= getenv("INTEL_DEVID_OVERRIDE");
2221 if (devid_override
) {
2222 screen
->no_hw
= true;
2223 return parse_devid_override(devid_override
);
2227 return intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2231 * This is the driver specific part of the createNewScreen entry point.
2232 * Called when using DRI2.
2234 * \return the struct gl_config supported by this driver
2237 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2239 struct intel_screen
*screen
;
2241 if (dri_screen
->image
.loader
) {
2242 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2243 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2245 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2246 "support required\n");
2250 /* Allocate the private area */
2251 screen
= rzalloc(NULL
, struct intel_screen
);
2253 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2256 /* parse information in __driConfigOptions */
2257 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
2259 screen
->driScrnPriv
= dri_screen
;
2260 dri_screen
->driverPrivate
= (void *) screen
;
2262 screen
->deviceID
= get_pci_device_id(screen
);
2264 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2267 if (!intel_init_bufmgr(screen
))
2270 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2272 brw_process_intel_debug_variable();
2274 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2276 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2277 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2280 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2281 /* Theorectically unlimited! At least for individual objects...
2283 * Currently the entire (global) address space for all GTT maps is
2284 * limited to 64bits. That is all objects on the system that are
2285 * setup for GTT mmapping must fit within 64bits. An attempt to use
2286 * one that exceeds the limit with fail in brw_bo_map_gtt().
2288 * Long before we hit that limit, we will be practically limited by
2289 * that any single object must fit in physical memory (RAM). The upper
2290 * limit on the CPU's address space is currently 48bits (Skylake), of
2291 * which only 39bits can be physical memory. (The GPU itself also has
2292 * a 48bit addressable virtual space.) We can fit over 32 million
2293 * objects of the current maximum allocable size before running out
2296 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2298 /* Estimate the size of the mappable aperture into the GTT. There's an
2299 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2300 * It turns out it's basically always 256MB, though some ancient hardware
2303 uint32_t gtt_size
= 256 * 1024 * 1024;
2305 /* We don't want to map two objects such that a memcpy between them would
2306 * just fault one mapping in and then the other over and over forever. So
2307 * we would need to divide the GTT size by 2. Additionally, some GTT is
2308 * taken up by things like the framebuffer and the ringbuffer and such, so
2309 * be more conservative.
2311 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2314 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2316 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2317 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2319 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2320 screen
->hw_has_swizzling
);
2322 /* GENs prior to 8 do not support EU/Subslice info */
2323 if (devinfo
->gen
>= 8) {
2324 intel_detect_sseu(screen
);
2325 } else if (devinfo
->gen
== 7) {
2326 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2329 /* Gen7-7.5 kernel requirements / command parser saga:
2332 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2334 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2335 * all batches secure, allowing them to use any feature with no checking.
2336 * This is effectively equivalent to a command parser version of
2337 * \infinity - everything is possible.
2339 * The command parser does not exist, and querying the version will
2343 * The kernel enables the command parser by default, for systems with
2344 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2345 * hardware checker is still enabled, so Haswell and Baytrail cannot
2348 * Ivybridge goes from "everything is possible" to "only what the
2349 * command parser allows" (if the user boots with i915.cmd_parser=0,
2350 * then everything is possible again). We can only safely use features
2351 * allowed by the supported command parser version.
2353 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2354 * implemented by the kernel, even if it's turned off. So, checking
2355 * for version > 0 does not mean that you can write registers. We have
2356 * to try it and see. The version does, however, indicate the age of
2359 * Instead of matching the hardware checker's behavior of converting
2360 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2361 * -EINVAL, making it dangerous to try and use privileged features.
2363 * Effective command parser versions:
2364 * - Haswell: 0 (reporting 1, writes don't work)
2365 * - Baytrail: 0 (reporting 1, writes don't work)
2366 * - Ivybridge: 1 (enabled) or infinite (disabled)
2369 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2370 * effectively version 1 (enabled) or infinite (disabled).
2372 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2373 * Command parser v2 supports predicate writes.
2375 * - Haswell: 0 (reporting 1, writes don't work)
2376 * - Baytrail: 2 (enabled) or infinite (disabled)
2377 * - Ivybridge: 2 (enabled) or infinite (disabled)
2379 * So version >= 2 is enough to know that Ivybridge and Baytrail
2380 * will work. Haswell still can't do anything.
2382 * - v4.0: Version 3 happened. Largely not relevant.
2384 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2385 * L3 config registers are properly saved and restored as part
2386 * of the hardware context. We can approximately detect this point
2387 * in time by checking if I915_PARAM_REVISION is recognized - it
2388 * landed in a later commit, but in the same release cycle.
2390 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2391 * Command parser finally gains secure batch promotion. On Haswell,
2392 * the hardware checker gets disabled, which finally allows it to do
2393 * privileged commands.
2395 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2396 * - Haswell: 3 (enabled) or 0 (disabled)
2397 * - Baytrail: 3 (enabled) or infinite (disabled)
2398 * - Ivybridge: 3 (enabled) or infinite (disabled)
2400 * Unfortunately, detecting this point in time is tricky, because
2401 * no version bump happened when this important change occurred.
2402 * On Haswell, if we can write any register, then the kernel is at
2403 * least this new, and we can start trusting the version number.
2405 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2406 * Command parser reaches version 4, allowing access to Haswell
2407 * atomic scratch and chicken3 registers. If version >= 4, we know
2408 * the kernel is new enough to support privileged features on all
2409 * hardware. However, the user might have disabled it...and the
2410 * kernel will still report version 4. So we still have to guess
2413 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2414 * Command parser v5 whitelists indirect compute shader dispatch
2415 * registers, needed for OpenGL 4.3 and later.
2418 * Command parser v7 lets us use MI_MATH on Haswell.
2420 * Additionally, the kernel begins reporting version 0 when
2421 * the command parser is disabled, allowing us to skip the
2422 * guess-and-check step on Haswell. Unfortunately, this also
2423 * means that we can no longer use it as an indicator of the
2424 * age of the kernel.
2426 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2427 &screen
->cmd_parser_version
) < 0) {
2428 /* Command parser does not exist - getparam is unrecognized */
2429 screen
->cmd_parser_version
= 0;
2432 /* Kernel 4.13 retuired for exec object capture */
2433 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2434 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2437 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2438 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2441 if (!intel_detect_pipelined_so(screen
)) {
2442 /* We can't do anything, so the effective version is 0. */
2443 screen
->cmd_parser_version
= 0;
2445 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2448 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2449 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2451 /* Haswell requires command parser version 4 in order to have L3
2452 * atomic scratch1 and chicken3 bits
2454 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2455 screen
->kernel_features
|=
2456 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2459 /* Haswell requires command parser version 6 in order to write to the
2460 * MI_MATH GPR registers, and version 7 in order to use
2461 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2463 if (devinfo
->gen
>= 8 ||
2464 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2465 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2468 /* Gen7 needs at least command parser version 5 to support compute */
2469 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2470 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2472 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2474 screen
->winsys_msaa_samples_override
=
2475 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2476 printf("Forcing winsys sample count to %d\n",
2477 screen
->winsys_msaa_samples_override
);
2479 screen
->winsys_msaa_samples_override
= -1;
2482 set_max_gl_versions(screen
);
2484 /* Notification of GPU resets requires hardware contexts and a kernel new
2485 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2486 * supported, calling it with a context of 0 will either generate EPERM or
2487 * no error. If the ioctl is not supported, it always generate EINVAL.
2488 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2489 * extension to the loader.
2491 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2493 if (devinfo
->gen
>= 6) {
2494 struct drm_i915_reset_stats stats
;
2495 memset(&stats
, 0, sizeof(stats
));
2497 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2499 screen
->has_context_reset_notification
=
2500 (ret
!= -1 || errno
!= EINVAL
);
2503 dri_screen
->extensions
= !screen
->has_context_reset_notification
2504 ? screenExtensions
: intelRobustScreenExtensions
;
2506 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2507 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2508 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2509 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8;
2510 screen
->program_id
= 1;
2512 screen
->has_exec_fence
=
2513 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2515 intel_screen_init_surface_formats(screen
);
2517 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2520 struct intel_buffer
{
2525 static __DRIbuffer
*
2526 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2527 unsigned attachment
, unsigned format
,
2528 int width
, int height
)
2530 struct intel_buffer
*intelBuffer
;
2531 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2533 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2534 attachment
== __DRI_BUFFER_BACK_LEFT
);
2536 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2537 if (intelBuffer
== NULL
)
2540 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2541 * supports Y tiled and compressed buffers, but there is no way to plumb that
2542 * through to here. */
2544 int cpp
= format
/ 8;
2545 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2546 "intelAllocateBuffer",
2550 I915_TILING_X
, &pitch
,
2553 if (intelBuffer
->bo
== NULL
) {
2558 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2560 intelBuffer
->base
.attachment
= attachment
;
2561 intelBuffer
->base
.cpp
= cpp
;
2562 intelBuffer
->base
.pitch
= pitch
;
2564 return &intelBuffer
->base
;
2568 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2570 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2572 brw_bo_unreference(intelBuffer
->bo
);
2576 static const struct __DriverAPIRec brw_driver_api
= {
2577 .InitScreen
= intelInitScreen2
,
2578 .DestroyScreen
= intelDestroyScreen
,
2579 .CreateContext
= brwCreateContext
,
2580 .DestroyContext
= intelDestroyContext
,
2581 .CreateBuffer
= intelCreateBuffer
,
2582 .DestroyBuffer
= intelDestroyBuffer
,
2583 .MakeCurrent
= intelMakeCurrent
,
2584 .UnbindContext
= intelUnbindContext
,
2585 .AllocateBuffer
= intelAllocateBuffer
,
2586 .ReleaseBuffer
= intelReleaseBuffer
2589 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2590 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2591 .vtable
= &brw_driver_api
,
2594 static const __DRIextension
*brw_driver_extensions
[] = {
2595 &driCoreExtension
.base
,
2596 &driImageDriverExtension
.base
,
2597 &driDRI2Extension
.base
,
2599 &brw_config_options
.base
,
2603 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2605 globalDriverAPI
= &brw_driver_api
;
2607 return brw_driver_extensions
;