b72c247bffba5ff2b95e0b8e963c2c5c16ffb0b1
[mesa.git] / src / mesa / drivers / dri / i965 / intel_screen.c
1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "drm-uapi/drm_fourcc.h"
27 #include <errno.h>
28 #include <time.h>
29 #include <unistd.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "main/glthread.h"
38 #include "swrast/s_renderbuffer.h"
39 #include "util/ralloc.h"
40 #include "util/disk_cache.h"
41 #include "brw_defines.h"
42 #include "brw_state.h"
43 #include "compiler/nir/nir.h"
44
45 #include "utils.h"
46 #include "util/disk_cache.h"
47 #include "util/driconf.h"
48 #include "util/u_memory.h"
49
50 #include "common/gen_defines.h"
51
52 static const __DRIconfigOptionsExtension brw_config_options = {
53 .base = { __DRI_CONFIG_OPTIONS, 1 },
54 .xml =
55 DRI_CONF_BEGIN
56 DRI_CONF_SECTION_PERFORMANCE
57 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
58 * DRI_CONF_BO_REUSE_ALL
59 */
60 DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1")
61 DRI_CONF_DESC_BEGIN("Buffer object reuse")
62 DRI_CONF_ENUM(0, "Disable buffer object reuse")
63 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
64 DRI_CONF_DESC_END
65 DRI_CONF_OPT_END
66 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_MESA_GLTHREAD("false")
68 DRI_CONF_SECTION_END
69
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_PRECISE_TRIG("false")
72
73 DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
74 DRI_CONF_DESC("Clamp the value of GL_MAX_SAMPLES to the "
75 "given integer. If negative, then do not clamp.")
76 DRI_CONF_OPT_END
77 DRI_CONF_SECTION_END
78
79 DRI_CONF_SECTION_DEBUG
80 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
81 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
82 DRI_CONF_DISABLE_THROTTLING("false")
83 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
84 DRI_CONF_FORCE_GLSL_VERSION(0)
85 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
86 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
87 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
88 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
89 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
90 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
91 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
92 DRI_CONF_FORCE_COMPAT_PROFILE("false")
93 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
94
95 DRI_CONF_OPT_BEGIN_B(shader_precompile, "true")
96 DRI_CONF_DESC("Perform code generation at shader link time.")
97 DRI_CONF_OPT_END
98 DRI_CONF_SECTION_END
99
100 DRI_CONF_SECTION_MISCELLANEOUS
101 DRI_CONF_GLSL_ZERO_INIT("false")
102 DRI_CONF_VS_POSITION_ALWAYS_INVARIANT("false")
103 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
104 DRI_CONF_ALLOW_RGB565_CONFIGS("true")
105 DRI_CONF_ALLOW_FP16_CONFIGS("false")
106 DRI_CONF_SECTION_END
107 DRI_CONF_END
108 };
109
110 #include "intel_batchbuffer.h"
111 #include "intel_buffers.h"
112 #include "brw_bufmgr.h"
113 #include "intel_fbo.h"
114 #include "intel_mipmap_tree.h"
115 #include "intel_screen.h"
116 #include "intel_tex.h"
117 #include "intel_image.h"
118
119 #include "brw_context.h"
120
121 #include "drm-uapi/i915_drm.h"
122
123 /**
124 * For debugging purposes, this returns a time in seconds.
125 */
126 double
127 get_time(void)
128 {
129 struct timespec tp;
130
131 clock_gettime(CLOCK_MONOTONIC, &tp);
132
133 return tp.tv_sec + tp.tv_nsec / 1000000000.0;
134 }
135
136 static const __DRItexBufferExtension intelTexBufferExtension = {
137 .base = { __DRI_TEX_BUFFER, 3 },
138
139 .setTexBuffer = intelSetTexBuffer,
140 .setTexBuffer2 = intelSetTexBuffer2,
141 .releaseTexBuffer = intelReleaseTexBuffer,
142 };
143
144 static void
145 intel_dri2_flush_with_flags(__DRIcontext *cPriv,
146 __DRIdrawable *dPriv,
147 unsigned flags,
148 enum __DRI2throttleReason reason)
149 {
150 struct brw_context *brw = cPriv->driverPrivate;
151
152 if (!brw)
153 return;
154
155 struct gl_context *ctx = &brw->ctx;
156
157 _mesa_glthread_finish(ctx);
158
159 FLUSH_VERTICES(ctx, 0);
160
161 if (flags & __DRI2_FLUSH_DRAWABLE)
162 intel_resolve_for_dri2_flush(brw, dPriv);
163
164 if (reason == __DRI2_THROTTLE_SWAPBUFFER)
165 brw->need_swap_throttle = true;
166 if (reason == __DRI2_THROTTLE_FLUSHFRONT)
167 brw->need_flush_throttle = true;
168
169 intel_batchbuffer_flush(brw);
170 }
171
172 /**
173 * Provides compatibility with loaders that only support the older (version
174 * 1-3) flush interface.
175 *
176 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
177 */
178 static void
179 intel_dri2_flush(__DRIdrawable *drawable)
180 {
181 intel_dri2_flush_with_flags(drawable->driContextPriv, drawable,
182 __DRI2_FLUSH_DRAWABLE,
183 __DRI2_THROTTLE_SWAPBUFFER);
184 }
185
186 static const struct __DRI2flushExtensionRec intelFlushExtension = {
187 .base = { __DRI2_FLUSH, 4 },
188
189 .flush = intel_dri2_flush,
190 .invalidate = dri2InvalidateDrawable,
191 .flush_with_flags = intel_dri2_flush_with_flags,
192 };
193
194 static const struct intel_image_format intel_image_formats[] = {
195 { DRM_FORMAT_ABGR16161616F, __DRI_IMAGE_COMPONENTS_RGBA, 1,
196 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR16161616F, 8 } } },
197
198 { DRM_FORMAT_XBGR16161616F, __DRI_IMAGE_COMPONENTS_RGB, 1,
199 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR16161616F, 8 } } },
200
201 { DRM_FORMAT_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
202 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } },
203
204 { DRM_FORMAT_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
205 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } },
206
207 { DRM_FORMAT_ABGR2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
208 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010, 4 } } },
209
210 { DRM_FORMAT_XBGR2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
211 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010, 4 } } },
212
213 { DRM_FORMAT_ARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
214 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
215
216 { DRM_FORMAT_ABGR8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
217 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
218
219 { __DRI_IMAGE_FOURCC_SARGB8888, __DRI_IMAGE_COMPONENTS_RGBA, 1,
220 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
221
222 { __DRI_IMAGE_FOURCC_SXRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
223 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SXRGB8, 4 } } },
224
225 { DRM_FORMAT_XRGB8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
226 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888, 4 }, } },
227
228 { DRM_FORMAT_XBGR8888, __DRI_IMAGE_COMPONENTS_RGB, 1,
229 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 }, } },
230
231 { DRM_FORMAT_ARGB1555, __DRI_IMAGE_COMPONENTS_RGBA, 1,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555, 2 } } },
233
234 { DRM_FORMAT_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
235 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
236
237 { DRM_FORMAT_R8, __DRI_IMAGE_COMPONENTS_R, 1,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
239
240 { DRM_FORMAT_R16, __DRI_IMAGE_COMPONENTS_R, 1,
241 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
242
243 { DRM_FORMAT_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
244 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
245
246 { DRM_FORMAT_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
248
249 { DRM_FORMAT_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
250 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
251 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
252 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
253
254 { DRM_FORMAT_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
255 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
256 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
257 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
258
259 { DRM_FORMAT_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
260 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
261 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
262 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
263
264 { DRM_FORMAT_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
265 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
266 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
267 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
268
269 { DRM_FORMAT_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
270 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
271 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
272 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
273
274 { DRM_FORMAT_YVU410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
275 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
276 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
277 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
278
279 { DRM_FORMAT_YVU411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
280 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
281 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
282 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
283
284 { DRM_FORMAT_YVU420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
285 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
286 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
287 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
288
289 { DRM_FORMAT_YVU422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
290 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
291 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
292 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
293
294 { DRM_FORMAT_YVU444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
295 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
296 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
297 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
298
299 { DRM_FORMAT_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
300 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
301 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
302
303 { DRM_FORMAT_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
304 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
305 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
306
307 { DRM_FORMAT_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
308 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
309 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
310
311 { DRM_FORMAT_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
312 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 },
313 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } },
314
315 { DRM_FORMAT_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
316 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
317 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
318
319 { DRM_FORMAT_AYUV, __DRI_IMAGE_COMPONENTS_AYUV, 1,
320 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } },
321
322 { DRM_FORMAT_XYUV8888, __DRI_IMAGE_COMPONENTS_XYUV, 1,
323 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888, 4 } } },
324
325 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
326 * and treat them as planar buffers in the compositors.
327 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
328 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
329 * clusters and places pairs and places U into the G component and
330 * V into A. This lets the texture sampler interpolate the Y
331 * components correctly when sampling from plane 0, and interpolate
332 * U and V correctly when sampling from plane 1. */
333 { DRM_FORMAT_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
334 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
335 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888, 4 } } },
336 { DRM_FORMAT_UYVY, __DRI_IMAGE_COMPONENTS_Y_UXVX, 2,
337 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
338 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888, 4 } } }
339 };
340
341 static const struct {
342 uint64_t modifier;
343 unsigned since_gen;
344 } supported_modifiers[] = {
345 { .modifier = DRM_FORMAT_MOD_LINEAR , .since_gen = 1 },
346 { .modifier = I915_FORMAT_MOD_X_TILED , .since_gen = 1 },
347 { .modifier = I915_FORMAT_MOD_Y_TILED , .since_gen = 6 },
348 { .modifier = I915_FORMAT_MOD_Y_TILED_CCS , .since_gen = 9 },
349 };
350
351 static bool
352 modifier_is_supported(const struct gen_device_info *devinfo,
353 const struct intel_image_format *fmt, int dri_format,
354 uint64_t modifier)
355 {
356 const struct isl_drm_modifier_info *modinfo =
357 isl_drm_modifier_get_info(modifier);
358 int i;
359
360 /* ISL had better know about the modifier */
361 if (!modinfo)
362 return false;
363
364 if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
365 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
366 if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC))
367 return false;
368
369 /* CCS_E is not supported for planar images */
370 if (fmt && fmt->nplanes > 1)
371 return false;
372
373 if (fmt) {
374 assert(dri_format == 0);
375 dri_format = fmt->planes[0].dri_format;
376 }
377
378 mesa_format format = driImageFormatToGLFormat(dri_format);
379 /* Whether or not we support compression is based on the RGBA non-sRGB
380 * version of the format.
381 */
382 format = _mesa_format_fallback_rgbx_to_rgba(format);
383 format = _mesa_get_srgb_format_linear(format);
384 if (!isl_format_supports_ccs_e(devinfo,
385 brw_isl_format_for_mesa_format(format)))
386 return false;
387 }
388
389 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
390 if (supported_modifiers[i].modifier != modifier)
391 continue;
392
393 return supported_modifiers[i].since_gen <= devinfo->gen;
394 }
395
396 return false;
397 }
398
399 static uint64_t
400 tiling_to_modifier(uint32_t tiling)
401 {
402 static const uint64_t map[] = {
403 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
404 [I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
405 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
406 };
407
408 assert(tiling < ARRAY_SIZE(map));
409
410 return map[tiling];
411 }
412
413 static void
414 intel_image_warn_if_unaligned(__DRIimage *image, const char *func)
415 {
416 uint32_t tiling, swizzle;
417 brw_bo_get_tiling(image->bo, &tiling, &swizzle);
418
419 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) {
420 _mesa_warning(NULL, "%s: offset 0x%08x not on tile boundary",
421 func, image->offset);
422 }
423 }
424
425 static const struct intel_image_format *
426 intel_image_format_lookup(int fourcc)
427 {
428 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
429 if (intel_image_formats[i].fourcc == fourcc)
430 return &intel_image_formats[i];
431 }
432
433 return NULL;
434 }
435
436 static bool
437 intel_image_get_fourcc(__DRIimage *image, int *fourcc)
438 {
439 if (image->planar_format) {
440 *fourcc = image->planar_format->fourcc;
441 return true;
442 }
443
444 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
445 if (intel_image_formats[i].planes[0].dri_format == image->dri_format) {
446 *fourcc = intel_image_formats[i].fourcc;
447 return true;
448 }
449 }
450 return false;
451 }
452
453 static __DRIimage *
454 intel_allocate_image(struct intel_screen *screen, int dri_format,
455 void *loaderPrivate)
456 {
457 __DRIimage *image;
458
459 image = calloc(1, sizeof *image);
460 if (image == NULL)
461 return NULL;
462
463 image->screen = screen;
464 image->dri_format = dri_format;
465 image->offset = 0;
466
467 image->format = driImageFormatToGLFormat(dri_format);
468 if (dri_format != __DRI_IMAGE_FORMAT_NONE &&
469 image->format == MESA_FORMAT_NONE) {
470 free(image);
471 return NULL;
472 }
473
474 image->internal_format = _mesa_get_format_base_format(image->format);
475 image->data = loaderPrivate;
476
477 return image;
478 }
479
480 /**
481 * Sets up a DRIImage structure to point to a slice out of a miptree.
482 */
483 static void
484 intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
485 struct intel_mipmap_tree *mt, GLuint level,
486 GLuint zoffset)
487 {
488 intel_miptree_make_shareable(brw, mt);
489
490 intel_miptree_check_level_layer(mt, level, zoffset);
491
492 image->width = minify(mt->surf.phys_level0_sa.width,
493 level - mt->first_level);
494 image->height = minify(mt->surf.phys_level0_sa.height,
495 level - mt->first_level);
496 image->pitch = mt->surf.row_pitch_B;
497
498 image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
499 &image->tile_x,
500 &image->tile_y);
501
502 brw_bo_unreference(image->bo);
503 image->bo = mt->bo;
504 brw_bo_reference(mt->bo);
505 }
506
507 static __DRIimage *
508 intel_create_image_from_name(__DRIscreen *dri_screen,
509 int width, int height, int format,
510 int name, int pitch, void *loaderPrivate)
511 {
512 struct intel_screen *screen = dri_screen->driverPrivate;
513 __DRIimage *image;
514 int cpp;
515
516 image = intel_allocate_image(screen, format, loaderPrivate);
517 if (image == NULL)
518 return NULL;
519
520 if (image->format == MESA_FORMAT_NONE)
521 cpp = 1;
522 else
523 cpp = _mesa_get_format_bytes(image->format);
524
525 image->width = width;
526 image->height = height;
527 image->pitch = pitch * cpp;
528 image->bo = brw_bo_gem_create_from_name(screen->bufmgr, "image",
529 name);
530 if (!image->bo) {
531 free(image);
532 return NULL;
533 }
534 image->modifier = tiling_to_modifier(image->bo->tiling_mode);
535
536 return image;
537 }
538
539 static __DRIimage *
540 intel_create_image_from_renderbuffer(__DRIcontext *context,
541 int renderbuffer, void *loaderPrivate)
542 {
543 __DRIimage *image;
544 struct brw_context *brw = context->driverPrivate;
545 struct gl_context *ctx = &brw->ctx;
546 struct gl_renderbuffer *rb;
547 struct intel_renderbuffer *irb;
548
549 rb = _mesa_lookup_renderbuffer(ctx, renderbuffer);
550 if (!rb) {
551 _mesa_error(ctx, GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
552 return NULL;
553 }
554
555 irb = intel_renderbuffer(rb);
556 intel_miptree_make_shareable(brw, irb->mt);
557 image = calloc(1, sizeof *image);
558 if (image == NULL)
559 return NULL;
560
561 image->internal_format = rb->InternalFormat;
562 image->format = rb->Format;
563 image->modifier = tiling_to_modifier(
564 isl_tiling_to_i915_tiling(irb->mt->surf.tiling));
565 image->offset = 0;
566 image->data = loaderPrivate;
567 brw_bo_unreference(image->bo);
568 image->bo = irb->mt->bo;
569 brw_bo_reference(irb->mt->bo);
570 image->width = rb->Width;
571 image->height = rb->Height;
572 image->pitch = irb->mt->surf.row_pitch_B;
573 image->dri_format = driGLFormatToImageFormat(image->format);
574 image->has_depthstencil = irb->mt->stencil_mt? true : false;
575
576 rb->NeedsFinishRenderTexture = true;
577 return image;
578 }
579
580 static __DRIimage *
581 intel_create_image_from_texture(__DRIcontext *context, int target,
582 unsigned texture, int zoffset,
583 int level,
584 unsigned *error,
585 void *loaderPrivate)
586 {
587 __DRIimage *image;
588 struct brw_context *brw = context->driverPrivate;
589 struct gl_texture_object *obj;
590 struct intel_texture_object *iobj;
591 GLuint face = 0;
592
593 obj = _mesa_lookup_texture(&brw->ctx, texture);
594 if (!obj || obj->Target != target) {
595 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
596 return NULL;
597 }
598
599 if (target == GL_TEXTURE_CUBE_MAP)
600 face = zoffset;
601
602 _mesa_test_texobj_completeness(&brw->ctx, obj);
603 iobj = intel_texture_object(obj);
604 if (!obj->_BaseComplete || (level > 0 && !obj->_MipmapComplete)) {
605 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
606 return NULL;
607 }
608
609 if (level < obj->BaseLevel || level > obj->_MaxLevel) {
610 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
611 return NULL;
612 }
613
614 if (target == GL_TEXTURE_3D && obj->Image[face][level]->Depth < zoffset) {
615 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
616 return NULL;
617 }
618 image = calloc(1, sizeof *image);
619 if (image == NULL) {
620 *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
621 return NULL;
622 }
623
624 image->internal_format = obj->Image[face][level]->InternalFormat;
625 image->format = obj->Image[face][level]->TexFormat;
626 image->modifier = tiling_to_modifier(
627 isl_tiling_to_i915_tiling(iobj->mt->surf.tiling));
628 image->data = loaderPrivate;
629 intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
630 image->dri_format = driGLFormatToImageFormat(image->format);
631 image->has_depthstencil = iobj->mt->stencil_mt? true : false;
632 image->planar_format = iobj->planar_format;
633 if (image->dri_format == __DRI_IMAGE_FORMAT_NONE) {
634 *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
635 free(image);
636 return NULL;
637 }
638
639 *error = __DRI_IMAGE_ERROR_SUCCESS;
640 return image;
641 }
642
643 static void
644 intel_destroy_image(__DRIimage *image)
645 {
646 brw_bo_unreference(image->bo);
647 free(image);
648 }
649
650 enum modifier_priority {
651 MODIFIER_PRIORITY_INVALID = 0,
652 MODIFIER_PRIORITY_LINEAR,
653 MODIFIER_PRIORITY_X,
654 MODIFIER_PRIORITY_Y,
655 MODIFIER_PRIORITY_Y_CCS,
656 };
657
658 const uint64_t priority_to_modifier[] = {
659 [MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
660 [MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
661 [MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
662 [MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
663 [MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
664 };
665
666 static uint64_t
667 select_best_modifier(struct gen_device_info *devinfo,
668 int dri_format,
669 const uint64_t *modifiers,
670 const unsigned count)
671 {
672 enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
673
674 for (int i = 0; i < count; i++) {
675 if (!modifier_is_supported(devinfo, NULL, dri_format, modifiers[i]))
676 continue;
677
678 switch (modifiers[i]) {
679 case I915_FORMAT_MOD_Y_TILED_CCS:
680 prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
681 break;
682 case I915_FORMAT_MOD_Y_TILED:
683 prio = MAX2(prio, MODIFIER_PRIORITY_Y);
684 break;
685 case I915_FORMAT_MOD_X_TILED:
686 prio = MAX2(prio, MODIFIER_PRIORITY_X);
687 break;
688 case DRM_FORMAT_MOD_LINEAR:
689 prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
690 break;
691 case DRM_FORMAT_MOD_INVALID:
692 default:
693 break;
694 }
695 }
696
697 return priority_to_modifier[prio];
698 }
699
700 static __DRIimage *
701 intel_create_image_common(__DRIscreen *dri_screen,
702 int width, int height, int format,
703 unsigned int use,
704 const uint64_t *modifiers,
705 unsigned count,
706 void *loaderPrivate)
707 {
708 __DRIimage *image;
709 struct intel_screen *screen = dri_screen->driverPrivate;
710 uint64_t modifier = DRM_FORMAT_MOD_INVALID;
711 bool ok;
712
713 /* Callers of this may specify a modifier, or a dri usage, but not both. The
714 * newer modifier interface deprecates the older usage flags.
715 */
716 assert(!(use && count));
717
718 if (use & __DRI_IMAGE_USE_CURSOR) {
719 if (width != 64 || height != 64)
720 return NULL;
721 modifier = DRM_FORMAT_MOD_LINEAR;
722 }
723
724 if (use & __DRI_IMAGE_USE_LINEAR)
725 modifier = DRM_FORMAT_MOD_LINEAR;
726
727 if (modifier == DRM_FORMAT_MOD_INVALID) {
728 if (modifiers) {
729 /* User requested specific modifiers */
730 modifier = select_best_modifier(&screen->devinfo, format,
731 modifiers, count);
732 if (modifier == DRM_FORMAT_MOD_INVALID)
733 return NULL;
734 } else {
735 /* Historically, X-tiled was the default, and so lack of modifier means
736 * X-tiled.
737 */
738 modifier = I915_FORMAT_MOD_X_TILED;
739 }
740 }
741
742 image = intel_allocate_image(screen, format, loaderPrivate);
743 if (image == NULL)
744 return NULL;
745
746 const struct isl_drm_modifier_info *mod_info =
747 isl_drm_modifier_get_info(modifier);
748
749 struct isl_surf surf;
750 ok = isl_surf_init(&screen->isl_dev, &surf,
751 .dim = ISL_SURF_DIM_2D,
752 .format = brw_isl_format_for_mesa_format(image->format),
753 .width = width,
754 .height = height,
755 .depth = 1,
756 .levels = 1,
757 .array_len = 1,
758 .samples = 1,
759 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
760 ISL_SURF_USAGE_TEXTURE_BIT |
761 ISL_SURF_USAGE_STORAGE_BIT |
762 ((use & __DRI_IMAGE_USE_SCANOUT) ?
763 ISL_SURF_USAGE_DISPLAY_BIT : 0),
764 .tiling_flags = (1 << mod_info->tiling));
765 assert(ok);
766 if (!ok) {
767 free(image);
768 return NULL;
769 }
770
771 struct isl_surf aux_surf = {0,};
772 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
773 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL, 0);
774 if (!ok) {
775 free(image);
776 return NULL;
777 }
778 } else {
779 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
780 aux_surf.size_B = 0;
781 }
782
783 /* We request that the bufmgr zero the buffer for us for two reasons:
784 *
785 * 1) If a buffer gets re-used from the pool, we don't want to leak random
786 * garbage from our process to some other.
787 *
788 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
789 * a valid state. A CCS value of 0 indicates that the given block is
790 * in the pass-through state which is what we want.
791 */
792 image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image",
793 surf.size_B + aux_surf.size_B,
794 BRW_MEMZONE_OTHER,
795 isl_tiling_to_i915_tiling(mod_info->tiling),
796 surf.row_pitch_B, BO_ALLOC_ZEROED);
797 if (image->bo == NULL) {
798 free(image);
799 return NULL;
800 }
801 image->width = width;
802 image->height = height;
803 image->pitch = surf.row_pitch_B;
804 image->modifier = modifier;
805
806 if (aux_surf.size_B) {
807 image->aux_offset = surf.size_B;
808 image->aux_pitch = aux_surf.row_pitch_B;
809 image->aux_size = aux_surf.size_B;
810 }
811
812 return image;
813 }
814
815 static __DRIimage *
816 intel_create_image(__DRIscreen *dri_screen,
817 int width, int height, int format,
818 unsigned int use,
819 void *loaderPrivate)
820 {
821 return intel_create_image_common(dri_screen, width, height, format, use, NULL, 0,
822 loaderPrivate);
823 }
824
825 static void *
826 intel_map_image(__DRIcontext *context, __DRIimage *image,
827 int x0, int y0, int width, int height,
828 unsigned int flags, int *stride, void **map_info)
829 {
830 struct brw_context *brw = NULL;
831 struct brw_bo *bo = NULL;
832 void *raw_data = NULL;
833 GLuint pix_w = 1;
834 GLuint pix_h = 1;
835 GLint pix_bytes = 1;
836
837 if (!context || !image || !stride || !map_info || *map_info)
838 return NULL;
839
840 if (x0 < 0 || x0 >= image->width || width > image->width - x0)
841 return NULL;
842
843 if (y0 < 0 || y0 >= image->height || height > image->height - y0)
844 return NULL;
845
846 if (flags & MAP_INTERNAL_MASK)
847 return NULL;
848
849 brw = context->driverPrivate;
850 bo = image->bo;
851
852 assert(brw);
853 assert(bo);
854
855 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
856 raw_data = brw_bo_map(brw, bo, flags);
857 if (!raw_data)
858 return NULL;
859
860 _mesa_get_format_block_size(image->format, &pix_w, &pix_h);
861 pix_bytes = _mesa_get_format_bytes(image->format);
862
863 assert(pix_w);
864 assert(pix_h);
865 assert(pix_bytes > 0);
866
867 raw_data += (x0 / pix_w) * pix_bytes + (y0 / pix_h) * image->pitch;
868
869 brw_bo_reference(bo);
870
871 *stride = image->pitch;
872 *map_info = bo;
873
874 return raw_data;
875 }
876
877 static void
878 intel_unmap_image(__DRIcontext *context, __DRIimage *image, void *map_info)
879 {
880 struct brw_bo *bo = map_info;
881
882 brw_bo_unmap(bo);
883 brw_bo_unreference(bo);
884 }
885
886 static __DRIimage *
887 intel_create_image_with_modifiers(__DRIscreen *dri_screen,
888 int width, int height, int format,
889 const uint64_t *modifiers,
890 const unsigned count,
891 void *loaderPrivate)
892 {
893 return intel_create_image_common(dri_screen, width, height, format, 0,
894 modifiers, count, loaderPrivate);
895 }
896
897 static GLboolean
898 intel_query_image(__DRIimage *image, int attrib, int *value)
899 {
900 switch (attrib) {
901 case __DRI_IMAGE_ATTRIB_STRIDE:
902 *value = image->pitch;
903 return true;
904 case __DRI_IMAGE_ATTRIB_HANDLE: {
905 __DRIscreen *dri_screen = image->screen->driScrnPriv;
906 uint32_t handle;
907 if (brw_bo_export_gem_handle_for_device(image->bo,
908 dri_screen->fd,
909 &handle))
910 return false;
911 *value = handle;
912 return true;
913 }
914 case __DRI_IMAGE_ATTRIB_NAME:
915 return !brw_bo_flink(image->bo, (uint32_t *) value);
916 case __DRI_IMAGE_ATTRIB_FORMAT:
917 *value = image->dri_format;
918 return true;
919 case __DRI_IMAGE_ATTRIB_WIDTH:
920 *value = image->width;
921 return true;
922 case __DRI_IMAGE_ATTRIB_HEIGHT:
923 *value = image->height;
924 return true;
925 case __DRI_IMAGE_ATTRIB_COMPONENTS:
926 if (image->planar_format == NULL)
927 return false;
928 *value = image->planar_format->components;
929 return true;
930 case __DRI_IMAGE_ATTRIB_FD:
931 return !brw_bo_gem_export_to_prime(image->bo, value);
932 case __DRI_IMAGE_ATTRIB_FOURCC:
933 return intel_image_get_fourcc(image, value);
934 case __DRI_IMAGE_ATTRIB_NUM_PLANES:
935 if (isl_drm_modifier_has_aux(image->modifier)) {
936 assert(!image->planar_format || image->planar_format->nplanes == 1);
937 *value = 2;
938 } else if (image->planar_format) {
939 *value = image->planar_format->nplanes;
940 } else {
941 *value = 1;
942 }
943 return true;
944 case __DRI_IMAGE_ATTRIB_OFFSET:
945 *value = image->offset;
946 return true;
947 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER:
948 *value = (image->modifier & 0xffffffff);
949 return true;
950 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER:
951 *value = ((image->modifier >> 32) & 0xffffffff);
952 return true;
953
954 default:
955 return false;
956 }
957 }
958
959 static GLboolean
960 intel_query_format_modifier_attribs(__DRIscreen *dri_screen,
961 uint32_t fourcc, uint64_t modifier,
962 int attrib, uint64_t *value)
963 {
964 struct intel_screen *screen = dri_screen->driverPrivate;
965 const struct intel_image_format *f = intel_image_format_lookup(fourcc);
966
967 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
968 return false;
969
970 switch (attrib) {
971 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT:
972 *value = isl_drm_modifier_has_aux(modifier) ? 2 : f->nplanes;
973 return true;
974
975 default:
976 return false;
977 }
978 }
979
980 static __DRIimage *
981 intel_dup_image(__DRIimage *orig_image, void *loaderPrivate)
982 {
983 __DRIimage *image;
984
985 image = calloc(1, sizeof *image);
986 if (image == NULL)
987 return NULL;
988
989 brw_bo_reference(orig_image->bo);
990 image->screen = orig_image->screen;
991 image->bo = orig_image->bo;
992 image->internal_format = orig_image->internal_format;
993 image->planar_format = orig_image->planar_format;
994 image->dri_format = orig_image->dri_format;
995 image->format = orig_image->format;
996 image->modifier = orig_image->modifier;
997 image->offset = orig_image->offset;
998 image->width = orig_image->width;
999 image->height = orig_image->height;
1000 image->pitch = orig_image->pitch;
1001 image->tile_x = orig_image->tile_x;
1002 image->tile_y = orig_image->tile_y;
1003 image->has_depthstencil = orig_image->has_depthstencil;
1004 image->data = loaderPrivate;
1005 image->aux_offset = orig_image->aux_offset;
1006 image->aux_pitch = orig_image->aux_pitch;
1007
1008 memcpy(image->strides, orig_image->strides, sizeof(image->strides));
1009 memcpy(image->offsets, orig_image->offsets, sizeof(image->offsets));
1010
1011 return image;
1012 }
1013
1014 static GLboolean
1015 intel_validate_usage(__DRIimage *image, unsigned int use)
1016 {
1017 if (use & __DRI_IMAGE_USE_CURSOR) {
1018 if (image->width != 64 || image->height != 64)
1019 return GL_FALSE;
1020 }
1021
1022 return GL_TRUE;
1023 }
1024
1025 static __DRIimage *
1026 intel_create_image_from_names(__DRIscreen *dri_screen,
1027 int width, int height, int fourcc,
1028 int *names, int num_names,
1029 int *strides, int *offsets,
1030 void *loaderPrivate)
1031 {
1032 const struct intel_image_format *f = NULL;
1033 __DRIimage *image;
1034 int i, index;
1035
1036 if (dri_screen == NULL || names == NULL || num_names != 1)
1037 return NULL;
1038
1039 f = intel_image_format_lookup(fourcc);
1040 if (f == NULL)
1041 return NULL;
1042
1043 image = intel_create_image_from_name(dri_screen, width, height,
1044 __DRI_IMAGE_FORMAT_NONE,
1045 names[0], strides[0],
1046 loaderPrivate);
1047
1048 if (image == NULL)
1049 return NULL;
1050
1051 image->planar_format = f;
1052 for (i = 0; i < f->nplanes; i++) {
1053 index = f->planes[i].buffer_index;
1054 image->offsets[index] = offsets[index];
1055 image->strides[index] = strides[index];
1056 }
1057
1058 return image;
1059 }
1060
1061 static __DRIimage *
1062 intel_create_image_from_fds_common(__DRIscreen *dri_screen,
1063 int width, int height, int fourcc,
1064 uint64_t modifier, int *fds, int num_fds,
1065 int *strides, int *offsets,
1066 void *loaderPrivate)
1067 {
1068 struct intel_screen *screen = dri_screen->driverPrivate;
1069 const struct intel_image_format *f;
1070 __DRIimage *image;
1071 int i, index;
1072 bool ok;
1073
1074 if (fds == NULL || num_fds < 1)
1075 return NULL;
1076
1077 f = intel_image_format_lookup(fourcc);
1078 if (f == NULL)
1079 return NULL;
1080
1081 if (modifier != DRM_FORMAT_MOD_INVALID &&
1082 !modifier_is_supported(&screen->devinfo, f, 0, modifier))
1083 return NULL;
1084
1085 if (f->nplanes == 1)
1086 image = intel_allocate_image(screen, f->planes[0].dri_format,
1087 loaderPrivate);
1088 else
1089 image = intel_allocate_image(screen, __DRI_IMAGE_FORMAT_NONE,
1090 loaderPrivate);
1091
1092 if (image == NULL)
1093 return NULL;
1094
1095 image->width = width;
1096 image->height = height;
1097 image->pitch = strides[0];
1098
1099 image->planar_format = f;
1100
1101 if (modifier != DRM_FORMAT_MOD_INVALID) {
1102 const struct isl_drm_modifier_info *mod_info =
1103 isl_drm_modifier_get_info(modifier);
1104 uint32_t tiling = isl_tiling_to_i915_tiling(mod_info->tiling);
1105 image->bo = brw_bo_gem_create_from_prime_tiled(screen->bufmgr, fds[0],
1106 tiling, strides[0]);
1107 } else {
1108 image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
1109 }
1110
1111 if (image->bo == NULL) {
1112 free(image);
1113 return NULL;
1114 }
1115
1116 /* We only support all planes from the same bo.
1117 * brw_bo_gem_create_from_prime() should return the same pointer for all
1118 * fds received here */
1119 for (i = 1; i < num_fds; i++) {
1120 struct brw_bo *aux = brw_bo_gem_create_from_prime(screen->bufmgr, fds[i]);
1121 brw_bo_unreference(aux);
1122 if (aux != image->bo) {
1123 brw_bo_unreference(image->bo);
1124 free(image);
1125 return NULL;
1126 }
1127 }
1128
1129 if (modifier != DRM_FORMAT_MOD_INVALID)
1130 image->modifier = modifier;
1131 else
1132 image->modifier = tiling_to_modifier(image->bo->tiling_mode);
1133
1134 const struct isl_drm_modifier_info *mod_info =
1135 isl_drm_modifier_get_info(image->modifier);
1136
1137 int size = 0;
1138 struct isl_surf surf;
1139 for (i = 0; i < f->nplanes; i++) {
1140 index = f->planes[i].buffer_index;
1141 image->offsets[index] = offsets[index];
1142 image->strides[index] = strides[index];
1143
1144 mesa_format format = driImageFormatToGLFormat(f->planes[i].dri_format);
1145 /* The images we will create are actually based on the RGBA non-sRGB
1146 * version of the format.
1147 */
1148 format = _mesa_format_fallback_rgbx_to_rgba(format);
1149 format = _mesa_get_srgb_format_linear(format);
1150
1151 ok = isl_surf_init(&screen->isl_dev, &surf,
1152 .dim = ISL_SURF_DIM_2D,
1153 .format = brw_isl_format_for_mesa_format(format),
1154 .width = image->width >> f->planes[i].width_shift,
1155 .height = image->height >> f->planes[i].height_shift,
1156 .depth = 1,
1157 .levels = 1,
1158 .array_len = 1,
1159 .samples = 1,
1160 .row_pitch_B = strides[index],
1161 .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT |
1162 ISL_SURF_USAGE_TEXTURE_BIT |
1163 ISL_SURF_USAGE_STORAGE_BIT,
1164 .tiling_flags = (1 << mod_info->tiling));
1165 if (!ok) {
1166 brw_bo_unreference(image->bo);
1167 free(image);
1168 return NULL;
1169 }
1170
1171 const int end = offsets[index] + surf.size_B;
1172 if (size < end)
1173 size = end;
1174 }
1175
1176 if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E) {
1177 /* Even though we initialize surf in the loop above, we know that
1178 * anything with CCS_E will have exactly one plane so surf is properly
1179 * initialized when we get here.
1180 */
1181 assert(f->nplanes == 1);
1182
1183 image->aux_offset = offsets[1];
1184 image->aux_pitch = strides[1];
1185
1186 /* Scanout hardware requires that the CCS be placed after the main
1187 * surface in memory. We consider any CCS that is placed any earlier in
1188 * memory to be invalid and reject it.
1189 *
1190 * At some point in the future, this restriction may be relaxed if the
1191 * hardware becomes less strict but we may need a new modifier for that.
1192 */
1193 assert(size > 0);
1194 if (image->aux_offset < size) {
1195 brw_bo_unreference(image->bo);
1196 free(image);
1197 return NULL;
1198 }
1199
1200 struct isl_surf aux_surf = {0,};
1201 ok = isl_surf_get_ccs_surf(&screen->isl_dev, &surf, &aux_surf, NULL,
1202 image->aux_pitch);
1203 if (!ok) {
1204 brw_bo_unreference(image->bo);
1205 free(image);
1206 return NULL;
1207 }
1208
1209 image->aux_size = aux_surf.size_B;
1210
1211 const int end = image->aux_offset + aux_surf.size_B;
1212 if (size < end)
1213 size = end;
1214 } else {
1215 assert(mod_info->aux_usage == ISL_AUX_USAGE_NONE);
1216 }
1217
1218 /* Check that the requested image actually fits within the BO. 'size'
1219 * is already relative to the offsets, so we don't need to add that. */
1220 if (image->bo->size == 0) {
1221 image->bo->size = size;
1222 } else if (size > image->bo->size) {
1223 brw_bo_unreference(image->bo);
1224 free(image);
1225 return NULL;
1226 }
1227
1228 if (f->nplanes == 1) {
1229 image->offset = image->offsets[0];
1230 intel_image_warn_if_unaligned(image, __func__);
1231 }
1232
1233 return image;
1234 }
1235
1236 static __DRIimage *
1237 intel_create_image_from_fds(__DRIscreen *dri_screen,
1238 int width, int height, int fourcc,
1239 int *fds, int num_fds, int *strides, int *offsets,
1240 void *loaderPrivate)
1241 {
1242 return intel_create_image_from_fds_common(dri_screen, width, height, fourcc,
1243 DRM_FORMAT_MOD_INVALID,
1244 fds, num_fds, strides, offsets,
1245 loaderPrivate);
1246 }
1247
1248 static __DRIimage *
1249 intel_create_image_from_dma_bufs2(__DRIscreen *dri_screen,
1250 int width, int height,
1251 int fourcc, uint64_t modifier,
1252 int *fds, int num_fds,
1253 int *strides, int *offsets,
1254 enum __DRIYUVColorSpace yuv_color_space,
1255 enum __DRISampleRange sample_range,
1256 enum __DRIChromaSiting horizontal_siting,
1257 enum __DRIChromaSiting vertical_siting,
1258 unsigned *error,
1259 void *loaderPrivate)
1260 {
1261 __DRIimage *image;
1262 const struct intel_image_format *f = intel_image_format_lookup(fourcc);
1263
1264 if (!f) {
1265 *error = __DRI_IMAGE_ERROR_BAD_MATCH;
1266 return NULL;
1267 }
1268
1269 image = intel_create_image_from_fds_common(dri_screen, width, height,
1270 fourcc, modifier,
1271 fds, num_fds, strides, offsets,
1272 loaderPrivate);
1273
1274 /*
1275 * Invalid parameters and any inconsistencies between are assumed to be
1276 * checked by the caller. Therefore besides unsupported formats one can fail
1277 * only in allocation.
1278 */
1279 if (!image) {
1280 *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
1281 return NULL;
1282 }
1283
1284 image->yuv_color_space = yuv_color_space;
1285 image->sample_range = sample_range;
1286 image->horizontal_siting = horizontal_siting;
1287 image->vertical_siting = vertical_siting;
1288 image->imported_dmabuf = true;
1289
1290 *error = __DRI_IMAGE_ERROR_SUCCESS;
1291 return image;
1292 }
1293
1294 static __DRIimage *
1295 intel_create_image_from_dma_bufs(__DRIscreen *dri_screen,
1296 int width, int height, int fourcc,
1297 int *fds, int num_fds,
1298 int *strides, int *offsets,
1299 enum __DRIYUVColorSpace yuv_color_space,
1300 enum __DRISampleRange sample_range,
1301 enum __DRIChromaSiting horizontal_siting,
1302 enum __DRIChromaSiting vertical_siting,
1303 unsigned *error,
1304 void *loaderPrivate)
1305 {
1306 return intel_create_image_from_dma_bufs2(dri_screen, width, height,
1307 fourcc, DRM_FORMAT_MOD_INVALID,
1308 fds, num_fds, strides, offsets,
1309 yuv_color_space,
1310 sample_range,
1311 horizontal_siting,
1312 vertical_siting,
1313 error,
1314 loaderPrivate);
1315 }
1316
1317 static bool
1318 intel_image_format_is_supported(const struct gen_device_info *devinfo,
1319 const struct intel_image_format *fmt)
1320 {
1321 /* Currently, all formats with an intel_image_format are available on all
1322 * platforms so there's really nothing to check there.
1323 */
1324
1325 #ifndef NDEBUG
1326 if (fmt->nplanes == 1) {
1327 mesa_format format = driImageFormatToGLFormat(fmt->planes[0].dri_format);
1328 /* The images we will create are actually based on the RGBA non-sRGB
1329 * version of the format.
1330 */
1331 format = _mesa_format_fallback_rgbx_to_rgba(format);
1332 format = _mesa_get_srgb_format_linear(format);
1333 enum isl_format isl_format = brw_isl_format_for_mesa_format(format);
1334 assert(isl_format_supports_rendering(devinfo, isl_format));
1335 }
1336 #endif
1337
1338 return true;
1339 }
1340
1341 static GLboolean
1342 intel_query_dma_buf_formats(__DRIscreen *_screen, int max,
1343 int *formats, int *count)
1344 {
1345 struct intel_screen *screen = _screen->driverPrivate;
1346 int num_formats = 0, i;
1347
1348 for (i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
1349 /* These formats are valid DRI formats but do not exist in drm_fourcc.h
1350 * in the Linux kernel. We don't want to accidentally advertise them
1351 * them through the EGL layer.
1352 */
1353 if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB8888 ||
1354 intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR8888 ||
1355 intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SXRGB8888)
1356 continue;
1357
1358 if (!intel_image_format_is_supported(&screen->devinfo,
1359 &intel_image_formats[i]))
1360 continue;
1361
1362 num_formats++;
1363 if (max == 0)
1364 continue;
1365
1366 formats[num_formats - 1] = intel_image_formats[i].fourcc;
1367 if (num_formats >= max)
1368 break;
1369 }
1370
1371 *count = num_formats;
1372 return true;
1373 }
1374
1375 static GLboolean
1376 intel_query_dma_buf_modifiers(__DRIscreen *_screen, int fourcc, int max,
1377 uint64_t *modifiers,
1378 unsigned int *external_only,
1379 int *count)
1380 {
1381 struct intel_screen *screen = _screen->driverPrivate;
1382 const struct intel_image_format *f;
1383 int num_mods = 0, i;
1384
1385 f = intel_image_format_lookup(fourcc);
1386 if (f == NULL)
1387 return false;
1388
1389 if (!intel_image_format_is_supported(&screen->devinfo, f))
1390 return false;
1391
1392 for (i = 0; i < ARRAY_SIZE(supported_modifiers); i++) {
1393 uint64_t modifier = supported_modifiers[i].modifier;
1394 if (!modifier_is_supported(&screen->devinfo, f, 0, modifier))
1395 continue;
1396
1397 num_mods++;
1398 if (max == 0)
1399 continue;
1400
1401 modifiers[num_mods - 1] = modifier;
1402 if (num_mods >= max)
1403 break;
1404 }
1405
1406 if (external_only != NULL) {
1407 for (i = 0; i < num_mods && i < max; i++) {
1408 if (f->components == __DRI_IMAGE_COMPONENTS_Y_U_V ||
1409 f->components == __DRI_IMAGE_COMPONENTS_Y_UV ||
1410 f->components == __DRI_IMAGE_COMPONENTS_AYUV ||
1411 f->components == __DRI_IMAGE_COMPONENTS_XYUV ||
1412 f->components == __DRI_IMAGE_COMPONENTS_Y_XUXV ||
1413 f->components == __DRI_IMAGE_COMPONENTS_Y_UXVX) {
1414 external_only[i] = GL_TRUE;
1415 }
1416 else {
1417 external_only[i] = GL_FALSE;
1418 }
1419 }
1420 }
1421
1422 *count = num_mods;
1423 return true;
1424 }
1425
1426 static __DRIimage *
1427 intel_from_planar(__DRIimage *parent, int plane, void *loaderPrivate)
1428 {
1429 int width, height, offset, stride, size, dri_format;
1430 __DRIimage *image;
1431
1432 if (parent == NULL)
1433 return NULL;
1434
1435 width = parent->width;
1436 height = parent->height;
1437
1438 const struct intel_image_format *f = parent->planar_format;
1439
1440 if (f && plane < f->nplanes) {
1441 /* Use the planar format definition. */
1442 width >>= f->planes[plane].width_shift;
1443 height >>= f->planes[plane].height_shift;
1444 dri_format = f->planes[plane].dri_format;
1445 int index = f->planes[plane].buffer_index;
1446 offset = parent->offsets[index];
1447 stride = parent->strides[index];
1448 size = height * stride;
1449 } else if (plane == 0) {
1450 /* The only plane of a non-planar image: copy the parent definition
1451 * directly. */
1452 dri_format = parent->dri_format;
1453 offset = parent->offset;
1454 stride = parent->pitch;
1455 size = height * stride;
1456 } else if (plane == 1 && parent->modifier != DRM_FORMAT_MOD_INVALID &&
1457 isl_drm_modifier_has_aux(parent->modifier)) {
1458 /* Auxiliary plane */
1459 dri_format = parent->dri_format;
1460 offset = parent->aux_offset;
1461 stride = parent->aux_pitch;
1462 size = parent->aux_size;
1463 } else {
1464 return NULL;
1465 }
1466
1467 if (offset + size > parent->bo->size) {
1468 _mesa_warning(NULL, "intel_from_planar: subimage out of bounds");
1469 return NULL;
1470 }
1471
1472 image = intel_allocate_image(parent->screen, dri_format, loaderPrivate);
1473 if (image == NULL)
1474 return NULL;
1475
1476 image->bo = parent->bo;
1477 brw_bo_reference(parent->bo);
1478 image->modifier = parent->modifier;
1479
1480 image->width = width;
1481 image->height = height;
1482 image->pitch = stride;
1483 image->offset = offset;
1484
1485 intel_image_warn_if_unaligned(image, __func__);
1486
1487 return image;
1488 }
1489
1490 static const __DRIimageExtension intelImageExtension = {
1491 .base = { __DRI_IMAGE, 16 },
1492
1493 .createImageFromName = intel_create_image_from_name,
1494 .createImageFromRenderbuffer = intel_create_image_from_renderbuffer,
1495 .destroyImage = intel_destroy_image,
1496 .createImage = intel_create_image,
1497 .queryImage = intel_query_image,
1498 .dupImage = intel_dup_image,
1499 .validateUsage = intel_validate_usage,
1500 .createImageFromNames = intel_create_image_from_names,
1501 .fromPlanar = intel_from_planar,
1502 .createImageFromTexture = intel_create_image_from_texture,
1503 .createImageFromFds = intel_create_image_from_fds,
1504 .createImageFromDmaBufs = intel_create_image_from_dma_bufs,
1505 .blitImage = NULL,
1506 .getCapabilities = NULL,
1507 .mapImage = intel_map_image,
1508 .unmapImage = intel_unmap_image,
1509 .createImageWithModifiers = intel_create_image_with_modifiers,
1510 .createImageFromDmaBufs2 = intel_create_image_from_dma_bufs2,
1511 .queryDmaBufFormats = intel_query_dma_buf_formats,
1512 .queryDmaBufModifiers = intel_query_dma_buf_modifiers,
1513 .queryDmaBufFormatModifierAttribs = intel_query_format_modifier_attribs,
1514 };
1515
1516 static int
1517 brw_query_renderer_integer(__DRIscreen *dri_screen,
1518 int param, unsigned int *value)
1519 {
1520 const struct intel_screen *const screen =
1521 (struct intel_screen *) dri_screen->driverPrivate;
1522
1523 switch (param) {
1524 case __DRI2_RENDERER_VENDOR_ID:
1525 value[0] = 0x8086;
1526 return 0;
1527 case __DRI2_RENDERER_DEVICE_ID:
1528 value[0] = screen->deviceID;
1529 return 0;
1530 case __DRI2_RENDERER_ACCELERATED:
1531 value[0] = 1;
1532 return 0;
1533 case __DRI2_RENDERER_VIDEO_MEMORY: {
1534 /* Once a batch uses more than 75% of the maximum mappable size, we
1535 * assume that there's some fragmentation, and we start doing extra
1536 * flushing, etc. That's the big cliff apps will care about.
1537 */
1538 const unsigned gpu_mappable_megabytes =
1539 screen->aperture_threshold / (1024 * 1024);
1540
1541 const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
1542 const long system_page_size = sysconf(_SC_PAGE_SIZE);
1543
1544 if (system_memory_pages <= 0 || system_page_size <= 0)
1545 return -1;
1546
1547 const uint64_t system_memory_bytes = (uint64_t) system_memory_pages
1548 * (uint64_t) system_page_size;
1549
1550 const unsigned system_memory_megabytes =
1551 (unsigned) (system_memory_bytes / (1024 * 1024));
1552
1553 value[0] = MIN2(system_memory_megabytes, gpu_mappable_megabytes);
1554 return 0;
1555 }
1556 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE:
1557 value[0] = 1;
1558 return 0;
1559 case __DRI2_RENDERER_HAS_TEXTURE_3D:
1560 value[0] = 1;
1561 return 0;
1562 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY:
1563 value[0] = 0;
1564 if (brw_hw_context_set_priority(screen->bufmgr,
1565 0, GEN_CONTEXT_HIGH_PRIORITY) == 0)
1566 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH;
1567 if (brw_hw_context_set_priority(screen->bufmgr,
1568 0, GEN_CONTEXT_LOW_PRIORITY) == 0)
1569 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW;
1570 /* reset to default last, just in case */
1571 if (brw_hw_context_set_priority(screen->bufmgr,
1572 0, GEN_CONTEXT_MEDIUM_PRIORITY) == 0)
1573 value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM;
1574 return 0;
1575 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB:
1576 value[0] = 1;
1577 return 0;
1578 default:
1579 return driQueryRendererIntegerCommon(dri_screen, param, value);
1580 }
1581
1582 return -1;
1583 }
1584
1585 static int
1586 brw_query_renderer_string(__DRIscreen *dri_screen,
1587 int param, const char **value)
1588 {
1589 const struct intel_screen *screen =
1590 (struct intel_screen *) dri_screen->driverPrivate;
1591
1592 switch (param) {
1593 case __DRI2_RENDERER_VENDOR_ID:
1594 value[0] = brw_vendor_string;
1595 return 0;
1596 case __DRI2_RENDERER_DEVICE_ID:
1597 value[0] = brw_get_renderer_string(screen);
1598 return 0;
1599 default:
1600 break;
1601 }
1602
1603 return -1;
1604 }
1605
1606 static void
1607 brw_set_cache_funcs(__DRIscreen *dri_screen,
1608 __DRIblobCacheSet set, __DRIblobCacheGet get)
1609 {
1610 const struct intel_screen *const screen =
1611 (struct intel_screen *) dri_screen->driverPrivate;
1612
1613 if (!screen->disk_cache)
1614 return;
1615
1616 disk_cache_set_callbacks(screen->disk_cache, set, get);
1617 }
1618
1619 static const __DRI2rendererQueryExtension intelRendererQueryExtension = {
1620 .base = { __DRI2_RENDERER_QUERY, 1 },
1621
1622 .queryInteger = brw_query_renderer_integer,
1623 .queryString = brw_query_renderer_string
1624 };
1625
1626 static const __DRIrobustnessExtension dri2Robustness = {
1627 .base = { __DRI2_ROBUSTNESS, 1 }
1628 };
1629
1630 static const __DRI2blobExtension intelBlobExtension = {
1631 .base = { __DRI2_BLOB, 1 },
1632 .set_cache_funcs = brw_set_cache_funcs
1633 };
1634
1635 static const __DRImutableRenderBufferDriverExtension intelMutableRenderBufferExtension = {
1636 .base = { __DRI_MUTABLE_RENDER_BUFFER_DRIVER, 1 },
1637 };
1638
1639 static const __DRIextension *screenExtensions[] = {
1640 &intelTexBufferExtension.base,
1641 &intelFenceExtension.base,
1642 &intelFlushExtension.base,
1643 &intelImageExtension.base,
1644 &intelRendererQueryExtension.base,
1645 &intelMutableRenderBufferExtension.base,
1646 &dri2ConfigQueryExtension.base,
1647 &dri2NoErrorExtension.base,
1648 &intelBlobExtension.base,
1649 NULL
1650 };
1651
1652 static const __DRIextension *intelRobustScreenExtensions[] = {
1653 &intelTexBufferExtension.base,
1654 &intelFenceExtension.base,
1655 &intelFlushExtension.base,
1656 &intelImageExtension.base,
1657 &intelRendererQueryExtension.base,
1658 &intelMutableRenderBufferExtension.base,
1659 &dri2ConfigQueryExtension.base,
1660 &dri2Robustness.base,
1661 &dri2NoErrorExtension.base,
1662 &intelBlobExtension.base,
1663 NULL
1664 };
1665
1666 static int
1667 intel_get_param(struct intel_screen *screen, int param, int *value)
1668 {
1669 int ret = 0;
1670 struct drm_i915_getparam gp;
1671
1672 memset(&gp, 0, sizeof(gp));
1673 gp.param = param;
1674 gp.value = value;
1675
1676 if (drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) {
1677 ret = -errno;
1678 if (ret != -EINVAL)
1679 _mesa_warning(NULL, "drm_i915_getparam: %d", ret);
1680 }
1681
1682 return ret;
1683 }
1684
1685 static bool
1686 intel_get_boolean(struct intel_screen *screen, int param)
1687 {
1688 int value = 0;
1689 return (intel_get_param(screen, param, &value) == 0) && value;
1690 }
1691
1692 static int
1693 intel_get_integer(struct intel_screen *screen, int param)
1694 {
1695 int value = -1;
1696
1697 if (intel_get_param(screen, param, &value) == 0)
1698 return value;
1699
1700 return -1;
1701 }
1702
1703 static void
1704 intelDestroyScreen(__DRIscreen * sPriv)
1705 {
1706 struct intel_screen *screen = sPriv->driverPrivate;
1707
1708 brw_bufmgr_unref(screen->bufmgr);
1709 driDestroyOptionInfo(&screen->optionCache);
1710
1711 disk_cache_destroy(screen->disk_cache);
1712
1713 ralloc_free(screen);
1714 sPriv->driverPrivate = NULL;
1715 }
1716
1717
1718 /**
1719 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1720 *
1721 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1722 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1723 * this does not allocate GPU memory.
1724 */
1725 static GLboolean
1726 intelCreateBuffer(__DRIscreen *dri_screen,
1727 __DRIdrawable * driDrawPriv,
1728 const struct gl_config * mesaVis, GLboolean isPixmap)
1729 {
1730 struct intel_renderbuffer *rb;
1731 struct intel_screen *screen = (struct intel_screen *)
1732 dri_screen->driverPrivate;
1733 mesa_format rgbFormat;
1734 unsigned num_samples =
1735 intel_quantize_num_samples(screen, mesaVis->samples);
1736
1737 if (isPixmap)
1738 return false;
1739
1740 struct gl_framebuffer *fb = CALLOC_STRUCT(gl_framebuffer);
1741 if (!fb)
1742 return false;
1743
1744 _mesa_initialize_window_framebuffer(fb, mesaVis);
1745
1746 if (screen->winsys_msaa_samples_override != -1) {
1747 num_samples = screen->winsys_msaa_samples_override;
1748 fb->Visual.samples = num_samples;
1749 }
1750
1751 if (mesaVis->redBits == 16 && mesaVis->alphaBits > 0 && mesaVis->floatMode) {
1752 rgbFormat = MESA_FORMAT_RGBA_FLOAT16;
1753 } else if (mesaVis->redBits == 16 && mesaVis->floatMode) {
1754 rgbFormat = MESA_FORMAT_RGBX_FLOAT16;
1755 } else if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
1756 rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1757 : MESA_FORMAT_R10G10B10A2_UNORM;
1758 } else if (mesaVis->redBits == 10) {
1759 rgbFormat = mesaVis->redMask == 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1760 : MESA_FORMAT_R10G10B10X2_UNORM;
1761 } else if (mesaVis->redBits == 5) {
1762 rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1763 : MESA_FORMAT_B5G6R5_UNORM;
1764 } else if (mesaVis->alphaBits == 0) {
1765 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8X8_SRGB
1766 : MESA_FORMAT_B8G8R8X8_SRGB;
1767 fb->Visual.sRGBCapable = true;
1768 } else if (mesaVis->sRGBCapable) {
1769 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1770 : MESA_FORMAT_B8G8R8A8_SRGB;
1771 fb->Visual.sRGBCapable = true;
1772 } else {
1773 rgbFormat = mesaVis->redMask == 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1774 : MESA_FORMAT_B8G8R8A8_SRGB;
1775 fb->Visual.sRGBCapable = true;
1776 }
1777
1778 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1779 bool srgb_cap_set = mesaVis->redBits >= 8 && mesaVis->sRGBCapable;
1780
1781 /* setup the hardware-based renderbuffers */
1782 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
1783 _mesa_attach_and_own_rb(fb, BUFFER_FRONT_LEFT, &rb->Base.Base);
1784 rb->need_srgb = srgb_cap_set;
1785
1786 if (mesaVis->doubleBufferMode) {
1787 rb = intel_create_winsys_renderbuffer(screen, rgbFormat, num_samples);
1788 _mesa_attach_and_own_rb(fb, BUFFER_BACK_LEFT, &rb->Base.Base);
1789 rb->need_srgb = srgb_cap_set;
1790 }
1791
1792 /*
1793 * Assert here that the gl_config has an expected depth/stencil bit
1794 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1795 * which constructs the advertised configs.)
1796 */
1797 if (mesaVis->depthBits == 24) {
1798 assert(mesaVis->stencilBits == 8);
1799
1800 if (screen->devinfo.has_hiz_and_separate_stencil) {
1801 rb = intel_create_private_renderbuffer(screen,
1802 MESA_FORMAT_Z24_UNORM_X8_UINT,
1803 num_samples);
1804 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1805 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_S_UINT8,
1806 num_samples);
1807 _mesa_attach_and_own_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
1808 } else {
1809 /*
1810 * Use combined depth/stencil. Note that the renderbuffer is
1811 * attached to two attachment points.
1812 */
1813 rb = intel_create_private_renderbuffer(screen,
1814 MESA_FORMAT_Z24_UNORM_S8_UINT,
1815 num_samples);
1816 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1817 _mesa_attach_and_reference_rb(fb, BUFFER_STENCIL, &rb->Base.Base);
1818 }
1819 }
1820 else if (mesaVis->depthBits == 16) {
1821 assert(mesaVis->stencilBits == 0);
1822 rb = intel_create_private_renderbuffer(screen, MESA_FORMAT_Z_UNORM16,
1823 num_samples);
1824 _mesa_attach_and_own_rb(fb, BUFFER_DEPTH, &rb->Base.Base);
1825 }
1826 else {
1827 assert(mesaVis->depthBits == 0);
1828 assert(mesaVis->stencilBits == 0);
1829 }
1830
1831 /* now add any/all software-based renderbuffers we may need */
1832 _swrast_add_soft_renderbuffers(fb,
1833 false, /* never sw color */
1834 false, /* never sw depth */
1835 false, /* never sw stencil */
1836 mesaVis->accumRedBits > 0,
1837 false, /* never sw alpha */
1838 false /* never sw aux */ );
1839 driDrawPriv->driverPrivate = fb;
1840
1841 return true;
1842 }
1843
1844 static void
1845 intelDestroyBuffer(__DRIdrawable * driDrawPriv)
1846 {
1847 struct gl_framebuffer *fb = driDrawPriv->driverPrivate;
1848
1849 _mesa_reference_framebuffer(&fb, NULL);
1850 }
1851
1852 static void
1853 intel_cs_timestamp_frequency(struct intel_screen *screen)
1854 {
1855 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1856 * gen10, PCI-id is enough to figure it out.
1857 */
1858 assert(screen->devinfo.gen >= 10);
1859
1860 int ret, freq;
1861
1862 ret = intel_get_param(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY,
1863 &freq);
1864 if (ret < 0) {
1865 _mesa_warning(NULL,
1866 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1867 return;
1868 }
1869
1870 screen->devinfo.timestamp_frequency = freq;
1871 }
1872
1873 static void
1874 intel_detect_sseu(struct intel_screen *screen)
1875 {
1876 assert(screen->devinfo.gen >= 8);
1877 int ret;
1878
1879 screen->subslice_total = -1;
1880 screen->eu_total = -1;
1881
1882 ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL,
1883 &screen->subslice_total);
1884 if (ret < 0 && ret != -EINVAL)
1885 goto err_out;
1886
1887 ret = intel_get_param(screen,
1888 I915_PARAM_EU_TOTAL, &screen->eu_total);
1889 if (ret < 0 && ret != -EINVAL)
1890 goto err_out;
1891
1892 /* Without this information, we cannot get the right Braswell brandstrings,
1893 * and we have to use conservative numbers for GPGPU on many platforms, but
1894 * otherwise, things will just work.
1895 */
1896 if (screen->subslice_total < 1 || screen->eu_total < 1)
1897 _mesa_warning(NULL,
1898 "Kernel 4.1 required to properly query GPU properties.\n");
1899
1900 return;
1901
1902 err_out:
1903 screen->subslice_total = -1;
1904 screen->eu_total = -1;
1905 _mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret));
1906 }
1907
1908 static bool
1909 intel_init_bufmgr(struct intel_screen *screen)
1910 {
1911 __DRIscreen *dri_screen = screen->driScrnPriv;
1912
1913 if (getenv("INTEL_NO_HW") != NULL)
1914 screen->no_hw = true;
1915
1916 bool bo_reuse = false;
1917 int bo_reuse_mode = driQueryOptioni(&screen->optionCache, "bo_reuse");
1918 switch (bo_reuse_mode) {
1919 case DRI_CONF_BO_REUSE_DISABLED:
1920 break;
1921 case DRI_CONF_BO_REUSE_ALL:
1922 bo_reuse = true;
1923 break;
1924 }
1925
1926 screen->bufmgr = brw_bufmgr_get_for_fd(&screen->devinfo, dri_screen->fd, bo_reuse);
1927 if (screen->bufmgr == NULL) {
1928 fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
1929 __func__, __LINE__);
1930 return false;
1931 }
1932 screen->fd = brw_bufmgr_get_fd(screen->bufmgr);
1933
1934 if (!intel_get_boolean(screen, I915_PARAM_HAS_EXEC_NO_RELOC)) {
1935 fprintf(stderr, "[%s: %u] Kernel 3.9 required.\n", __func__, __LINE__);
1936 return false;
1937 }
1938
1939 return true;
1940 }
1941
1942 static bool
1943 intel_detect_swizzling(struct intel_screen *screen)
1944 {
1945 /* Broadwell PRM says:
1946 *
1947 * "Before Gen8, there was a historical configuration control field to
1948 * swizzle address bit[6] for in X/Y tiling modes. This was set in three
1949 * different places: TILECTL[1:0], ARB_MODE[5:4], and
1950 * DISP_ARB_CTL[14:13].
1951 *
1952 * For Gen8 and subsequent generations, the swizzle fields are all
1953 * reserved, and the CPU's memory controller performs all address
1954 * swizzling modifications."
1955 */
1956 if (screen->devinfo.gen >= 8)
1957 return false;
1958
1959 uint32_t tiling = I915_TILING_X;
1960 uint32_t swizzle_mode = 0;
1961 struct brw_bo *buffer =
1962 brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
1963 BRW_MEMZONE_OTHER, tiling, 512, 0);
1964 if (buffer == NULL)
1965 return false;
1966
1967 brw_bo_get_tiling(buffer, &tiling, &swizzle_mode);
1968 brw_bo_unreference(buffer);
1969
1970 return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
1971 }
1972
1973 static int
1974 intel_detect_timestamp(struct intel_screen *screen)
1975 {
1976 uint64_t dummy = 0, last = 0;
1977 int upper, lower, loops;
1978
1979 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1980 * TIMESTAMP register being shifted and the low 32bits always zero.
1981 *
1982 * More recent kernels offer an interface to read the full 36bits
1983 * everywhere.
1984 */
1985 if (brw_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0)
1986 return 3;
1987
1988 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1989 * upper 32bits for a rapidly changing timestamp.
1990 */
1991 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &last))
1992 return 0;
1993
1994 upper = lower = 0;
1995 for (loops = 0; loops < 10; loops++) {
1996 /* The TIMESTAMP should change every 80ns, so several round trips
1997 * through the kernel should be enough to advance it.
1998 */
1999 if (brw_reg_read(screen->bufmgr, TIMESTAMP, &dummy))
2000 return 0;
2001
2002 upper += (dummy >> 32) != (last >> 32);
2003 if (upper > 1) /* beware 32bit counter overflow */
2004 return 2; /* upper dword holds the low 32bits of the timestamp */
2005
2006 lower += (dummy & 0xffffffff) != (last & 0xffffffff);
2007 if (lower > 1)
2008 return 1; /* timestamp is unshifted */
2009
2010 last = dummy;
2011 }
2012
2013 /* No advancement? No timestamp! */
2014 return 0;
2015 }
2016
2017 /**
2018 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
2019 *
2020 * Some combinations of hardware and kernel versions allow this feature,
2021 * while others don't. Instead of trying to enumerate every case, just
2022 * try and write a register and see if works.
2023 */
2024 static bool
2025 intel_detect_pipelined_register(struct intel_screen *screen,
2026 int reg, uint32_t expected_value, bool reset)
2027 {
2028 if (screen->no_hw)
2029 return false;
2030
2031 struct brw_bo *results, *bo;
2032 uint32_t *batch;
2033 uint32_t offset = 0;
2034 void *map;
2035 bool success = false;
2036
2037 /* Create a zero'ed temporary buffer for reading our results */
2038 results = brw_bo_alloc(screen->bufmgr, "registers", 4096, BRW_MEMZONE_OTHER);
2039 if (results == NULL)
2040 goto err;
2041
2042 bo = brw_bo_alloc(screen->bufmgr, "batchbuffer", 4096, BRW_MEMZONE_OTHER);
2043 if (bo == NULL)
2044 goto err_results;
2045
2046 map = brw_bo_map(NULL, bo, MAP_WRITE);
2047 if (!map)
2048 goto err_batch;
2049
2050 batch = map;
2051
2052 /* Write the register. */
2053 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2);
2054 *batch++ = reg;
2055 *batch++ = expected_value;
2056
2057 /* Save the register's value back to the buffer. */
2058 *batch++ = MI_STORE_REGISTER_MEM | (3 - 2);
2059 *batch++ = reg;
2060 struct drm_i915_gem_relocation_entry reloc = {
2061 .offset = (char *) batch - (char *) map,
2062 .delta = offset * sizeof(uint32_t),
2063 .target_handle = results->gem_handle,
2064 .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
2065 .write_domain = I915_GEM_DOMAIN_INSTRUCTION,
2066 };
2067 *batch++ = reloc.presumed_offset + reloc.delta;
2068
2069 /* And afterwards clear the register */
2070 if (reset) {
2071 *batch++ = MI_LOAD_REGISTER_IMM | (3 - 2);
2072 *batch++ = reg;
2073 *batch++ = 0;
2074 }
2075
2076 *batch++ = MI_BATCH_BUFFER_END;
2077
2078 struct drm_i915_gem_exec_object2 exec_objects[2] = {
2079 {
2080 .handle = results->gem_handle,
2081 },
2082 {
2083 .handle = bo->gem_handle,
2084 .relocation_count = 1,
2085 .relocs_ptr = (uintptr_t) &reloc,
2086 }
2087 };
2088
2089 struct drm_i915_gem_execbuffer2 execbuf = {
2090 .buffers_ptr = (uintptr_t) exec_objects,
2091 .buffer_count = 2,
2092 .batch_len = ALIGN((char *) batch - (char *) map, 8),
2093 .flags = I915_EXEC_RENDER,
2094 };
2095
2096 /* Don't bother with error checking - if the execbuf fails, the
2097 * value won't be written and we'll just report that there's no access.
2098 */
2099 drmIoctl(screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
2100
2101 /* Check whether the value got written. */
2102 void *results_map = brw_bo_map(NULL, results, MAP_READ);
2103 if (results_map) {
2104 success = *((uint32_t *)results_map + offset) == expected_value;
2105 brw_bo_unmap(results);
2106 }
2107
2108 err_batch:
2109 brw_bo_unreference(bo);
2110 err_results:
2111 brw_bo_unreference(results);
2112 err:
2113 return success;
2114 }
2115
2116 static bool
2117 intel_detect_pipelined_so(struct intel_screen *screen)
2118 {
2119 const struct gen_device_info *devinfo = &screen->devinfo;
2120
2121 /* Supposedly, Broadwell just works. */
2122 if (devinfo->gen >= 8)
2123 return true;
2124
2125 if (devinfo->gen <= 6)
2126 return false;
2127
2128 /* See the big explanation about command parser versions below */
2129 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2))
2130 return true;
2131
2132 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2133 * statistics registers), and we already reset it to zero before using it.
2134 */
2135 return intel_detect_pipelined_register(screen,
2136 GEN7_SO_WRITE_OFFSET(0),
2137 0x1337d0d0,
2138 false);
2139 }
2140
2141 /**
2142 * Return array of MSAA modes supported by the hardware. The array is
2143 * zero-terminated and sorted in decreasing order.
2144 */
2145 const int*
2146 intel_supported_msaa_modes(const struct intel_screen *screen)
2147 {
2148 static const int gen9_modes[] = {16, 8, 4, 2, 0, -1};
2149 static const int gen8_modes[] = {8, 4, 2, 0, -1};
2150 static const int gen7_modes[] = {8, 4, 0, -1};
2151 static const int gen6_modes[] = {4, 0, -1};
2152 static const int gen4_modes[] = {0, -1};
2153
2154 if (screen->devinfo.gen >= 9) {
2155 return gen9_modes;
2156 } else if (screen->devinfo.gen >= 8) {
2157 return gen8_modes;
2158 } else if (screen->devinfo.gen >= 7) {
2159 return gen7_modes;
2160 } else if (screen->devinfo.gen == 6) {
2161 return gen6_modes;
2162 } else {
2163 return gen4_modes;
2164 }
2165 }
2166
2167 static unsigned
2168 intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap)
2169 {
2170 if (dri_screen->dri2.loader && dri_screen->dri2.loader->base.version >= 4 &&
2171 dri_screen->dri2.loader->getCapability)
2172 return dri_screen->dri2.loader->getCapability(dri_screen->loaderPrivate, cap);
2173
2174 if (dri_screen->image.loader && dri_screen->image.loader->base.version >= 2 &&
2175 dri_screen->image.loader->getCapability)
2176 return dri_screen->image.loader->getCapability(dri_screen->loaderPrivate, cap);
2177
2178 return 0;
2179 }
2180
2181 static bool
2182 intel_allowed_format(__DRIscreen *dri_screen, mesa_format format)
2183 {
2184 struct intel_screen *screen = dri_screen->driverPrivate;
2185
2186 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2187 bool allow_rgba_ordering = intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING);
2188 if (!allow_rgba_ordering &&
2189 (format == MESA_FORMAT_R8G8B8A8_UNORM ||
2190 format == MESA_FORMAT_R8G8B8X8_UNORM ||
2191 format == MESA_FORMAT_R8G8B8A8_SRGB))
2192 return false;
2193
2194 /* Shall we expose 10 bpc formats? */
2195 bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache,
2196 "allow_rgb10_configs");
2197 if (!allow_rgb10_configs &&
2198 (format == MESA_FORMAT_B10G10R10A2_UNORM ||
2199 format == MESA_FORMAT_B10G10R10X2_UNORM))
2200 return false;
2201
2202 /* Shall we expose 565 formats? */
2203 bool allow_rgb565_configs = driQueryOptionb(&screen->optionCache,
2204 "allow_rgb565_configs");
2205 if (!allow_rgb565_configs && format == MESA_FORMAT_B5G6R5_UNORM)
2206 return false;
2207
2208 /* Shall we expose fp16 formats? */
2209 bool allow_fp16_configs = driQueryOptionb(&screen->optionCache,
2210 "allow_fp16_configs");
2211 allow_fp16_configs &= intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_FP16);
2212 if (!allow_fp16_configs &&
2213 (format == MESA_FORMAT_RGBA_FLOAT16 ||
2214 format == MESA_FORMAT_RGBX_FLOAT16))
2215 return false;
2216
2217 return true;
2218 }
2219
2220 static __DRIconfig**
2221 intel_screen_make_configs(__DRIscreen *dri_screen)
2222 {
2223 static const mesa_format formats[] = {
2224 MESA_FORMAT_B5G6R5_UNORM,
2225 MESA_FORMAT_B8G8R8A8_UNORM,
2226 MESA_FORMAT_B8G8R8X8_UNORM,
2227
2228 MESA_FORMAT_B8G8R8A8_SRGB,
2229 MESA_FORMAT_B8G8R8X8_SRGB,
2230
2231 /* For 10 bpc, 30 bit depth framebuffers. */
2232 MESA_FORMAT_B10G10R10A2_UNORM,
2233 MESA_FORMAT_B10G10R10X2_UNORM,
2234
2235 MESA_FORMAT_RGBA_FLOAT16,
2236 MESA_FORMAT_RGBX_FLOAT16,
2237
2238 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2239 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2240 * server may disagree on which format the GLXFBConfig represents,
2241 * resulting in swapped color channels.
2242 *
2243 * The problem, as of 2017-05-30:
2244 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2245 * order and chooses the first __DRIconfig with the expected channel
2246 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2247 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2248 *
2249 * EGL does not suffer from this problem. It correctly compares the
2250 * channel masks when matching EGLConfig to __DRIconfig.
2251 */
2252
2253 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2254 MESA_FORMAT_R8G8B8A8_UNORM,
2255
2256 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2257 MESA_FORMAT_R8G8B8X8_UNORM,
2258
2259 MESA_FORMAT_R8G8B8A8_SRGB,
2260 };
2261
2262 /* __DRI_ATTRIB_SWAP_COPY is not supported due to page flipping. */
2263 static const GLenum back_buffer_modes[] = {
2264 __DRI_ATTRIB_SWAP_UNDEFINED, __DRI_ATTRIB_SWAP_NONE
2265 };
2266
2267 static const uint8_t singlesample_samples[1] = {0};
2268
2269 struct intel_screen *screen = dri_screen->driverPrivate;
2270 const struct gen_device_info *devinfo = &screen->devinfo;
2271 uint8_t depth_bits[4], stencil_bits[4];
2272 __DRIconfig **configs = NULL;
2273
2274 unsigned num_formats = ARRAY_SIZE(formats);
2275
2276 /* Generate singlesample configs, each without accumulation buffer
2277 * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR.
2278 */
2279 for (unsigned i = 0; i < num_formats; i++) {
2280 __DRIconfig **new_configs;
2281 int num_depth_stencil_bits = 1;
2282
2283 if (!intel_allowed_format(dri_screen, formats[i]))
2284 continue;
2285
2286 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2287 * buffer that has a different number of bits per pixel than the color
2288 * buffer, gen >= 6 supports this.
2289 */
2290 depth_bits[0] = 0;
2291 stencil_bits[0] = 0;
2292
2293 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2294 if (devinfo->gen >= 8) {
2295 depth_bits[num_depth_stencil_bits] = 16;
2296 stencil_bits[num_depth_stencil_bits] = 0;
2297 num_depth_stencil_bits++;
2298 }
2299 if (devinfo->gen >= 6) {
2300 depth_bits[num_depth_stencil_bits] = 24;
2301 stencil_bits[num_depth_stencil_bits] = 8;
2302 num_depth_stencil_bits++;
2303 }
2304 } else {
2305 depth_bits[num_depth_stencil_bits] = 24;
2306 stencil_bits[num_depth_stencil_bits] = 8;
2307 num_depth_stencil_bits++;
2308 }
2309
2310 new_configs = driCreateConfigs(formats[i],
2311 depth_bits,
2312 stencil_bits,
2313 num_depth_stencil_bits,
2314 back_buffer_modes, 2,
2315 singlesample_samples, 1,
2316 false, false,
2317 /*mutable_render_buffer*/ true);
2318 configs = driConcatConfigs(configs, new_configs);
2319 }
2320
2321 /* Generate the minimum possible set of configs that include an
2322 * accumulation buffer.
2323 */
2324 for (unsigned i = 0; i < num_formats; i++) {
2325 __DRIconfig **new_configs;
2326
2327 if (!intel_allowed_format(dri_screen, formats[i]))
2328 continue;
2329
2330 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
2331 if (devinfo->gen >= 8) {
2332 depth_bits[0] = 16;
2333 stencil_bits[0] = 0;
2334 } else if (devinfo->gen >= 6) {
2335 depth_bits[0] = 24;
2336 stencil_bits[0] = 8;
2337 } else {
2338 depth_bits[0] = 0;
2339 stencil_bits[0] = 0;
2340 }
2341 } else {
2342 depth_bits[0] = 24;
2343 stencil_bits[0] = 8;
2344 }
2345
2346 new_configs = driCreateConfigs(formats[i],
2347 depth_bits, stencil_bits, 1,
2348 back_buffer_modes, 1,
2349 singlesample_samples, 1,
2350 true, false, false);
2351 configs = driConcatConfigs(configs, new_configs);
2352 }
2353
2354 /* Generate multisample configs.
2355 *
2356 * This loop breaks early, and hence is a no-op, on gen < 6.
2357 *
2358 * Multisample configs must follow the singlesample configs in order to
2359 * work around an X server bug present in 1.12. The X server chooses to
2360 * associate the first listed RGBA888-Z24S8 config, regardless of its
2361 * sample count, with the 32-bit depth visual used for compositing.
2362 *
2363 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2364 * supported. Singlebuffer configs are not supported because no one wants
2365 * them.
2366 */
2367 for (unsigned i = 0; i < num_formats; i++) {
2368 if (devinfo->gen < 6)
2369 break;
2370
2371 if (!intel_allowed_format(dri_screen, formats[i]))
2372 continue;
2373
2374 __DRIconfig **new_configs;
2375 const int num_depth_stencil_bits = 2;
2376 int num_msaa_modes = 0;
2377 const uint8_t *multisample_samples = NULL;
2378
2379 depth_bits[0] = 0;
2380 stencil_bits[0] = 0;
2381
2382 if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) {
2383 depth_bits[1] = 16;
2384 stencil_bits[1] = 0;
2385 } else {
2386 depth_bits[1] = 24;
2387 stencil_bits[1] = 8;
2388 }
2389
2390 if (devinfo->gen >= 9) {
2391 static const uint8_t multisample_samples_gen9[] = {2, 4, 8, 16};
2392 multisample_samples = multisample_samples_gen9;
2393 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen9);
2394 } else if (devinfo->gen == 8) {
2395 static const uint8_t multisample_samples_gen8[] = {2, 4, 8};
2396 multisample_samples = multisample_samples_gen8;
2397 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen8);
2398 } else if (devinfo->gen == 7) {
2399 static const uint8_t multisample_samples_gen7[] = {4, 8};
2400 multisample_samples = multisample_samples_gen7;
2401 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen7);
2402 } else if (devinfo->gen == 6) {
2403 static const uint8_t multisample_samples_gen6[] = {4};
2404 multisample_samples = multisample_samples_gen6;
2405 num_msaa_modes = ARRAY_SIZE(multisample_samples_gen6);
2406 }
2407
2408 new_configs = driCreateConfigs(formats[i],
2409 depth_bits,
2410 stencil_bits,
2411 num_depth_stencil_bits,
2412 back_buffer_modes, 1,
2413 multisample_samples,
2414 num_msaa_modes,
2415 false, false, false);
2416 configs = driConcatConfigs(configs, new_configs);
2417 }
2418
2419 if (configs == NULL) {
2420 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2421 __LINE__);
2422 return NULL;
2423 }
2424
2425 return configs;
2426 }
2427
2428 static void
2429 set_max_gl_versions(struct intel_screen *screen)
2430 {
2431 __DRIscreen *dri_screen = screen->driScrnPriv;
2432 const bool has_astc = screen->devinfo.gen >= 9;
2433
2434 switch (screen->devinfo.gen) {
2435 case 11:
2436 case 10:
2437 case 9:
2438 case 8:
2439 dri_screen->max_gl_core_version = 46;
2440 dri_screen->max_gl_compat_version = 30;
2441 dri_screen->max_gl_es1_version = 11;
2442 dri_screen->max_gl_es2_version = has_astc ? 32 : 31;
2443 break;
2444 case 7:
2445 dri_screen->max_gl_core_version = 33;
2446 if (can_do_pipelined_register_writes(screen)) {
2447 dri_screen->max_gl_core_version = 42;
2448 if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen))
2449 dri_screen->max_gl_core_version = 43;
2450 if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen))
2451 dri_screen->max_gl_core_version = 45;
2452 }
2453 dri_screen->max_gl_compat_version = 30;
2454 dri_screen->max_gl_es1_version = 11;
2455 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
2456 break;
2457 case 6:
2458 dri_screen->max_gl_core_version = 33;
2459 dri_screen->max_gl_compat_version = 30;
2460 dri_screen->max_gl_es1_version = 11;
2461 dri_screen->max_gl_es2_version = 30;
2462 break;
2463 case 5:
2464 case 4:
2465 dri_screen->max_gl_core_version = 0;
2466 dri_screen->max_gl_compat_version = 21;
2467 dri_screen->max_gl_es1_version = 11;
2468 dri_screen->max_gl_es2_version = 20;
2469 break;
2470 default:
2471 unreachable("unrecognized intel_screen::gen");
2472 }
2473 }
2474
2475 static void
2476 shader_debug_log_mesa(void *data, const char *fmt, ...)
2477 {
2478 struct brw_context *brw = (struct brw_context *)data;
2479 va_list args;
2480
2481 va_start(args, fmt);
2482 GLuint msg_id = 0;
2483 _mesa_gl_vdebugf(&brw->ctx, &msg_id,
2484 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2485 MESA_DEBUG_TYPE_OTHER,
2486 MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
2487 va_end(args);
2488 }
2489
2490 static void
2491 shader_perf_log_mesa(void *data, const char *fmt, ...)
2492 {
2493 struct brw_context *brw = (struct brw_context *)data;
2494
2495 va_list args;
2496 va_start(args, fmt);
2497
2498 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
2499 va_list args_copy;
2500 va_copy(args_copy, args);
2501 vfprintf(stderr, fmt, args_copy);
2502 va_end(args_copy);
2503 }
2504
2505 if (brw->perf_debug) {
2506 GLuint msg_id = 0;
2507 _mesa_gl_vdebugf(&brw->ctx, &msg_id,
2508 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2509 MESA_DEBUG_TYPE_PERFORMANCE,
2510 MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
2511 }
2512 va_end(args);
2513 }
2514
2515 /**
2516 * This is the driver specific part of the createNewScreen entry point.
2517 * Called when using DRI2.
2518 *
2519 * \return the struct gl_config supported by this driver
2520 */
2521 static const
2522 __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
2523 {
2524 struct intel_screen *screen;
2525
2526 if (dri_screen->image.loader) {
2527 } else if (dri_screen->dri2.loader->base.version <= 2 ||
2528 dri_screen->dri2.loader->getBuffersWithFormat == NULL) {
2529 fprintf(stderr,
2530 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2531 "support required\n");
2532 return NULL;
2533 }
2534
2535 /* Allocate the private area */
2536 screen = rzalloc(NULL, struct intel_screen);
2537 if (!screen) {
2538 fprintf(stderr, "\nERROR! Allocating private area failed\n");
2539 return NULL;
2540 }
2541 /* parse information in __driConfigOptions */
2542 driOptionCache options;
2543 memset(&options, 0, sizeof(options));
2544
2545 driParseOptionInfo(&options, brw_config_options.xml);
2546 driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
2547 "i965", NULL, NULL, 0);
2548 driDestroyOptionCache(&options);
2549
2550 screen->driScrnPriv = dri_screen;
2551 dri_screen->driverPrivate = (void *) screen;
2552
2553 if (!gen_get_device_info_from_fd(dri_screen->fd, &screen->devinfo))
2554 return NULL;
2555
2556 const struct gen_device_info *devinfo = &screen->devinfo;
2557 screen->deviceID = devinfo->chipset_id;
2558 screen->no_hw = devinfo->no_hw;
2559
2560 if (devinfo->gen >= 12) {
2561 fprintf(stderr, "gen12 and newer are not supported on i965\n");
2562 return NULL;
2563 }
2564
2565 if (!intel_init_bufmgr(screen))
2566 return NULL;
2567
2568 brw_process_intel_debug_variable();
2569
2570 if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
2571 fprintf(stderr,
2572 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2573 INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
2574 }
2575
2576 if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
2577 /* Theorectically unlimited! At least for individual objects...
2578 *
2579 * Currently the entire (global) address space for all GTT maps is
2580 * limited to 64bits. That is all objects on the system that are
2581 * setup for GTT mmapping must fit within 64bits. An attempt to use
2582 * one that exceeds the limit with fail in brw_bo_map_gtt().
2583 *
2584 * Long before we hit that limit, we will be practically limited by
2585 * that any single object must fit in physical memory (RAM). The upper
2586 * limit on the CPU's address space is currently 48bits (Skylake), of
2587 * which only 39bits can be physical memory. (The GPU itself also has
2588 * a 48bit addressable virtual space.) We can fit over 32 million
2589 * objects of the current maximum allocable size before running out
2590 * of mmap space.
2591 */
2592 screen->max_gtt_map_object_size = UINT64_MAX;
2593 } else {
2594 /* Estimate the size of the mappable aperture into the GTT. There's an
2595 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2596 * It turns out it's basically always 256MB, though some ancient hardware
2597 * was smaller.
2598 */
2599 uint32_t gtt_size = 256 * 1024 * 1024;
2600
2601 /* We don't want to map two objects such that a memcpy between them would
2602 * just fault one mapping in and then the other over and over forever. So
2603 * we would need to divide the GTT size by 2. Additionally, some GTT is
2604 * taken up by things like the framebuffer and the ringbuffer and such, so
2605 * be more conservative.
2606 */
2607 screen->max_gtt_map_object_size = gtt_size / 4;
2608 }
2609
2610 screen->aperture_threshold = devinfo->aperture_bytes * 3 / 4;
2611
2612 screen->hw_has_swizzling = intel_detect_swizzling(screen);
2613 screen->hw_has_timestamp = intel_detect_timestamp(screen);
2614
2615 isl_device_init(&screen->isl_dev, &screen->devinfo,
2616 screen->hw_has_swizzling);
2617
2618 if (devinfo->gen >= 10)
2619 intel_cs_timestamp_frequency(screen);
2620
2621 /* GENs prior to 8 do not support EU/Subslice info */
2622 if (devinfo->gen >= 8) {
2623 intel_detect_sseu(screen);
2624 } else if (devinfo->gen == 7) {
2625 screen->subslice_total = 1 << (devinfo->gt - 1);
2626 }
2627
2628 /* Gen7-7.5 kernel requirements / command parser saga:
2629 *
2630 * - pre-v3.16:
2631 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2632 *
2633 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2634 * all batches secure, allowing them to use any feature with no checking.
2635 * This is effectively equivalent to a command parser version of
2636 * \infinity - everything is possible.
2637 *
2638 * The command parser does not exist, and querying the version will
2639 * return -EINVAL.
2640 *
2641 * - v3.16:
2642 * The kernel enables the command parser by default, for systems with
2643 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2644 * hardware checker is still enabled, so Haswell and Baytrail cannot
2645 * do anything.
2646 *
2647 * Ivybridge goes from "everything is possible" to "only what the
2648 * command parser allows" (if the user boots with i915.cmd_parser=0,
2649 * then everything is possible again). We can only safely use features
2650 * allowed by the supported command parser version.
2651 *
2652 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2653 * implemented by the kernel, even if it's turned off. So, checking
2654 * for version > 0 does not mean that you can write registers. We have
2655 * to try it and see. The version does, however, indicate the age of
2656 * the kernel.
2657 *
2658 * Instead of matching the hardware checker's behavior of converting
2659 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2660 * -EINVAL, making it dangerous to try and use privileged features.
2661 *
2662 * Effective command parser versions:
2663 * - Haswell: 0 (reporting 1, writes don't work)
2664 * - Baytrail: 0 (reporting 1, writes don't work)
2665 * - Ivybridge: 1 (enabled) or infinite (disabled)
2666 *
2667 * - v3.17:
2668 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2669 * effectively version 1 (enabled) or infinite (disabled).
2670 *
2671 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2672 * Command parser v2 supports predicate writes.
2673 *
2674 * - Haswell: 0 (reporting 1, writes don't work)
2675 * - Baytrail: 2 (enabled) or infinite (disabled)
2676 * - Ivybridge: 2 (enabled) or infinite (disabled)
2677 *
2678 * So version >= 2 is enough to know that Ivybridge and Baytrail
2679 * will work. Haswell still can't do anything.
2680 *
2681 * - v4.0: Version 3 happened. Largely not relevant.
2682 *
2683 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2684 * L3 config registers are properly saved and restored as part
2685 * of the hardware context. We can approximately detect this point
2686 * in time by checking if I915_PARAM_REVISION is recognized - it
2687 * landed in a later commit, but in the same release cycle.
2688 *
2689 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2690 * Command parser finally gains secure batch promotion. On Haswell,
2691 * the hardware checker gets disabled, which finally allows it to do
2692 * privileged commands.
2693 *
2694 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2695 * - Haswell: 3 (enabled) or 0 (disabled)
2696 * - Baytrail: 3 (enabled) or infinite (disabled)
2697 * - Ivybridge: 3 (enabled) or infinite (disabled)
2698 *
2699 * Unfortunately, detecting this point in time is tricky, because
2700 * no version bump happened when this important change occurred.
2701 * On Haswell, if we can write any register, then the kernel is at
2702 * least this new, and we can start trusting the version number.
2703 *
2704 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2705 * Command parser reaches version 4, allowing access to Haswell
2706 * atomic scratch and chicken3 registers. If version >= 4, we know
2707 * the kernel is new enough to support privileged features on all
2708 * hardware. However, the user might have disabled it...and the
2709 * kernel will still report version 4. So we still have to guess
2710 * and check.
2711 *
2712 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2713 * Command parser v5 whitelists indirect compute shader dispatch
2714 * registers, needed for OpenGL 4.3 and later.
2715 *
2716 * - v4.8:
2717 * Command parser v7 lets us use MI_MATH on Haswell.
2718 *
2719 * Additionally, the kernel begins reporting version 0 when
2720 * the command parser is disabled, allowing us to skip the
2721 * guess-and-check step on Haswell. Unfortunately, this also
2722 * means that we can no longer use it as an indicator of the
2723 * age of the kernel.
2724 */
2725 if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
2726 &screen->cmd_parser_version) < 0) {
2727 /* Command parser does not exist - getparam is unrecognized */
2728 screen->cmd_parser_version = 0;
2729 }
2730
2731 /* Kernel 4.13 retuired for exec object capture */
2732 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_CAPTURE)) {
2733 screen->kernel_features |= KERNEL_ALLOWS_EXEC_CAPTURE;
2734 }
2735
2736 if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_BATCH_FIRST)) {
2737 screen->kernel_features |= KERNEL_ALLOWS_EXEC_BATCH_FIRST;
2738 }
2739
2740 if (!intel_detect_pipelined_so(screen)) {
2741 /* We can't do anything, so the effective version is 0. */
2742 screen->cmd_parser_version = 0;
2743 } else {
2744 screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES;
2745 }
2746
2747 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2)
2748 screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES;
2749
2750 /* Haswell requires command parser version 4 in order to have L3
2751 * atomic scratch1 and chicken3 bits
2752 */
2753 if (devinfo->is_haswell && screen->cmd_parser_version >= 4) {
2754 screen->kernel_features |=
2755 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3;
2756 }
2757
2758 /* Haswell requires command parser version 6 in order to write to the
2759 * MI_MATH GPR registers, and version 7 in order to use
2760 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2761 */
2762 if (devinfo->gen >= 8 ||
2763 (devinfo->is_haswell && screen->cmd_parser_version >= 7)) {
2764 screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR;
2765 }
2766
2767 /* Gen7 needs at least command parser version 5 to support compute */
2768 if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5)
2769 screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH;
2770
2771 if (intel_get_boolean(screen, I915_PARAM_HAS_CONTEXT_ISOLATION))
2772 screen->kernel_features |= KERNEL_ALLOWS_CONTEXT_ISOLATION;
2773
2774 const char *force_msaa = getenv("INTEL_FORCE_MSAA");
2775 if (force_msaa) {
2776 screen->winsys_msaa_samples_override =
2777 intel_quantize_num_samples(screen, atoi(force_msaa));
2778 printf("Forcing winsys sample count to %d\n",
2779 screen->winsys_msaa_samples_override);
2780 } else {
2781 screen->winsys_msaa_samples_override = -1;
2782 }
2783
2784 set_max_gl_versions(screen);
2785
2786 /* Notification of GPU resets requires hardware contexts and a kernel new
2787 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2788 * supported, calling it with a context of 0 will either generate EPERM or
2789 * no error. If the ioctl is not supported, it always generate EINVAL.
2790 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2791 * extension to the loader.
2792 *
2793 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2794 */
2795 if (devinfo->gen >= 6) {
2796 struct drm_i915_reset_stats stats;
2797 memset(&stats, 0, sizeof(stats));
2798
2799 const int ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats);
2800
2801 screen->has_context_reset_notification =
2802 (ret != -1 || errno != EINVAL);
2803 }
2804
2805 dri_screen->extensions = !screen->has_context_reset_notification
2806 ? screenExtensions : intelRobustScreenExtensions;
2807
2808 screen->compiler = brw_compiler_create(screen, devinfo);
2809 screen->compiler->shader_debug_log = shader_debug_log_mesa;
2810 screen->compiler->shader_perf_log = shader_perf_log_mesa;
2811
2812 /* Changing the meaning of constant buffer pointers from a dynamic state
2813 * offset to an absolute address is only safe if the kernel isolates other
2814 * contexts from our changes.
2815 */
2816 screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8 ||
2817 !(screen->kernel_features & KERNEL_ALLOWS_CONTEXT_ISOLATION);
2818
2819 screen->compiler->glsl_compiler_options[MESA_SHADER_VERTEX].PositionAlwaysInvariant = driQueryOptionb(&screen->optionCache, "vs_position_always_invariant");
2820
2821 screen->compiler->supports_pull_constants = true;
2822 screen->compiler->compact_params = true;
2823 screen->compiler->lower_variable_group_size = true;
2824
2825 screen->has_exec_fence =
2826 intel_get_boolean(screen, I915_PARAM_HAS_EXEC_FENCE);
2827
2828 intel_screen_init_surface_formats(screen);
2829
2830 if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
2831 unsigned int caps = intel_get_integer(screen, I915_PARAM_HAS_SCHEDULER);
2832 if (caps) {
2833 fprintf(stderr, "Kernel scheduler detected: %08x\n", caps);
2834 if (caps & I915_SCHEDULER_CAP_PRIORITY)
2835 fprintf(stderr, " - User priority sorting enabled\n");
2836 if (caps & I915_SCHEDULER_CAP_PREEMPTION)
2837 fprintf(stderr, " - Preemption enabled\n");
2838 }
2839 }
2840
2841 brw_disk_cache_init(screen);
2842
2843 return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
2844 }
2845
2846 struct intel_buffer {
2847 __DRIbuffer base;
2848 struct brw_bo *bo;
2849 };
2850
2851 static __DRIbuffer *
2852 intelAllocateBuffer(__DRIscreen *dri_screen,
2853 unsigned attachment, unsigned format,
2854 int width, int height)
2855 {
2856 struct intel_buffer *intelBuffer;
2857 struct intel_screen *screen = dri_screen->driverPrivate;
2858
2859 assert(attachment == __DRI_BUFFER_FRONT_LEFT ||
2860 attachment == __DRI_BUFFER_BACK_LEFT);
2861
2862 intelBuffer = calloc(1, sizeof *intelBuffer);
2863 if (intelBuffer == NULL)
2864 return NULL;
2865
2866 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2867 * supports Y tiled and compressed buffers, but there is no way to plumb that
2868 * through to here. */
2869 uint32_t pitch;
2870 int cpp = format / 8;
2871 intelBuffer->bo = brw_bo_alloc_tiled_2d(screen->bufmgr,
2872 "intelAllocateBuffer",
2873 width,
2874 height,
2875 cpp,
2876 BRW_MEMZONE_OTHER,
2877 I915_TILING_X, &pitch,
2878 BO_ALLOC_BUSY);
2879
2880 if (intelBuffer->bo == NULL) {
2881 free(intelBuffer);
2882 return NULL;
2883 }
2884
2885 brw_bo_flink(intelBuffer->bo, &intelBuffer->base.name);
2886
2887 intelBuffer->base.attachment = attachment;
2888 intelBuffer->base.cpp = cpp;
2889 intelBuffer->base.pitch = pitch;
2890
2891 return &intelBuffer->base;
2892 }
2893
2894 static void
2895 intelReleaseBuffer(__DRIscreen *dri_screen, __DRIbuffer *buffer)
2896 {
2897 struct intel_buffer *intelBuffer = (struct intel_buffer *) buffer;
2898
2899 brw_bo_unreference(intelBuffer->bo);
2900 free(intelBuffer);
2901 }
2902
2903 static const struct __DriverAPIRec brw_driver_api = {
2904 .InitScreen = intelInitScreen2,
2905 .DestroyScreen = intelDestroyScreen,
2906 .CreateContext = brwCreateContext,
2907 .DestroyContext = intelDestroyContext,
2908 .CreateBuffer = intelCreateBuffer,
2909 .DestroyBuffer = intelDestroyBuffer,
2910 .MakeCurrent = intelMakeCurrent,
2911 .UnbindContext = intelUnbindContext,
2912 .AllocateBuffer = intelAllocateBuffer,
2913 .ReleaseBuffer = intelReleaseBuffer
2914 };
2915
2916 static const struct __DRIDriverVtableExtensionRec brw_vtable = {
2917 .base = { __DRI_DRIVER_VTABLE, 1 },
2918 .vtable = &brw_driver_api,
2919 };
2920
2921 static const __DRIextension *brw_driver_extensions[] = {
2922 &driCoreExtension.base,
2923 &driImageDriverExtension.base,
2924 &driDRI2Extension.base,
2925 &brw_vtable.base,
2926 &brw_config_options.base,
2927 NULL
2928 };
2929
2930 PUBLIC const __DRIextension **__driDriverGetExtensions_i965(void)
2931 {
2932 globalDriverAPI = &brw_driver_api;
2933
2934 return brw_driver_extensions;
2935 }