2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "util/disk_cache.h"
40 #include "brw_defines.h"
41 #include "brw_state.h"
42 #include "compiler/nir/nir.h"
45 #include "util/disk_cache.h"
46 #include "util/xmlpool.h"
48 #include "common/gen_defines.h"
50 static const __DRIconfigOptionsExtension brw_config_options
= {
51 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
54 DRI_CONF_SECTION_PERFORMANCE
55 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
56 * DRI_CONF_BO_REUSE_ALL
58 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
59 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
60 DRI_CONF_ENUM(0, "Disable buffer object reuse")
61 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
64 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_SECTION_QUALITY
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_FORCE_GLSL_VERSION(0)
83 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
84 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
85 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
86 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
88 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
89 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
90 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
92 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
93 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
97 DRI_CONF_SECTION_MISCELLANEOUS
98 DRI_CONF_GLSL_ZERO_INIT("false")
99 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
104 #include "intel_batchbuffer.h"
105 #include "intel_buffers.h"
106 #include "brw_bufmgr.h"
107 #include "intel_fbo.h"
108 #include "intel_mipmap_tree.h"
109 #include "intel_screen.h"
110 #include "intel_tex.h"
111 #include "intel_image.h"
113 #include "brw_context.h"
115 #include "i915_drm.h"
118 * For debugging purposes, this returns a time in seconds.
125 clock_gettime(CLOCK_MONOTONIC
, &tp
);
127 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
130 static const __DRItexBufferExtension intelTexBufferExtension
= {
131 .base
= { __DRI_TEX_BUFFER
, 3 },
133 .setTexBuffer
= intelSetTexBuffer
,
134 .setTexBuffer2
= intelSetTexBuffer2
,
135 .releaseTexBuffer
= intelReleaseTexBuffer
,
139 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
140 __DRIdrawable
*dPriv
,
142 enum __DRI2throttleReason reason
)
144 struct brw_context
*brw
= cPriv
->driverPrivate
;
149 struct gl_context
*ctx
= &brw
->ctx
;
151 FLUSH_VERTICES(ctx
, 0);
153 if (flags
& __DRI2_FLUSH_DRAWABLE
)
154 intel_resolve_for_dri2_flush(brw
, dPriv
);
156 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
157 brw
->need_swap_throttle
= true;
158 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
159 brw
->need_flush_throttle
= true;
161 intel_batchbuffer_flush(brw
);
165 * Provides compatibility with loaders that only support the older (version
166 * 1-3) flush interface.
168 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
171 intel_dri2_flush(__DRIdrawable
*drawable
)
173 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
174 __DRI2_FLUSH_DRAWABLE
,
175 __DRI2_THROTTLE_SWAPBUFFER
);
178 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
179 .base
= { __DRI2_FLUSH
, 4 },
181 .flush
= intel_dri2_flush
,
182 .invalidate
= dri2InvalidateDrawable
,
183 .flush_with_flags
= intel_dri2_flush_with_flags
,
186 static const struct intel_image_format intel_image_formats
[] = {
187 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
188 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
190 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
191 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
193 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
194 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
196 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
199 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
202 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
205 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
208 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
211 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
214 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
217 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
220 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
223 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
226 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
228 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
231 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
236 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
271 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
276 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
277 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
278 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
280 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
281 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
282 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
284 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
285 * and treat them as planar buffers in the compositors.
286 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
287 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
288 * clusters and places pairs and places U into the G component and
289 * V into A. This lets the texture sampler interpolate the Y
290 * components correctly when sampling from plane 0, and interpolate
291 * U and V correctly when sampling from plane 1. */
292 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
293 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
294 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
295 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
296 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
297 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
300 static const struct {
303 } supported_modifiers
[] = {
304 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
305 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
306 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
307 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
311 modifier_is_supported(const struct gen_device_info
*devinfo
,
312 const struct intel_image_format
*fmt
, int dri_format
,
315 const struct isl_drm_modifier_info
*modinfo
=
316 isl_drm_modifier_get_info(modifier
);
319 /* ISL had better know about the modifier */
323 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
324 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
325 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
328 /* CCS_E is not supported for planar images */
329 if (fmt
&& fmt
->nplanes
> 1)
333 assert(dri_format
== 0);
334 dri_format
= fmt
->planes
[0].dri_format
;
337 mesa_format format
= driImageFormatToGLFormat(dri_format
);
338 format
= _mesa_get_srgb_format_linear(format
);
339 if (!isl_format_supports_ccs_e(devinfo
,
340 brw_isl_format_for_mesa_format(format
)))
344 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
345 if (supported_modifiers
[i
].modifier
!= modifier
)
348 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
355 tiling_to_modifier(uint32_t tiling
)
357 static const uint64_t map
[] = {
358 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
359 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
360 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
363 assert(tiling
< ARRAY_SIZE(map
));
369 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
371 uint32_t tiling
, swizzle
;
372 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
374 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
375 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
376 func
, image
->offset
);
380 static const struct intel_image_format
*
381 intel_image_format_lookup(int fourcc
)
383 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
384 if (intel_image_formats
[i
].fourcc
== fourcc
)
385 return &intel_image_formats
[i
];
391 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
393 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
394 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
395 *fourcc
= intel_image_formats
[i
].fourcc
;
403 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
408 image
= calloc(1, sizeof *image
);
412 image
->screen
= screen
;
413 image
->dri_format
= dri_format
;
416 image
->format
= driImageFormatToGLFormat(dri_format
);
417 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
418 image
->format
== MESA_FORMAT_NONE
) {
423 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
424 image
->data
= loaderPrivate
;
430 * Sets up a DRIImage structure to point to a slice out of a miptree.
433 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
434 struct intel_mipmap_tree
*mt
, GLuint level
,
437 intel_miptree_make_shareable(brw
, mt
);
439 intel_miptree_check_level_layer(mt
, level
, zoffset
);
441 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
442 level
- mt
->first_level
);
443 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
444 level
- mt
->first_level
);
445 image
->pitch
= mt
->surf
.row_pitch
;
447 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
451 brw_bo_unreference(image
->bo
);
453 brw_bo_reference(mt
->bo
);
457 intel_create_image_from_name(__DRIscreen
*dri_screen
,
458 int width
, int height
, int format
,
459 int name
, int pitch
, void *loaderPrivate
)
461 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
465 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
469 if (image
->format
== MESA_FORMAT_NONE
)
472 cpp
= _mesa_get_format_bytes(image
->format
);
474 image
->width
= width
;
475 image
->height
= height
;
476 image
->pitch
= pitch
* cpp
;
477 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
483 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
489 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
490 int renderbuffer
, void *loaderPrivate
)
493 struct brw_context
*brw
= context
->driverPrivate
;
494 struct gl_context
*ctx
= &brw
->ctx
;
495 struct gl_renderbuffer
*rb
;
496 struct intel_renderbuffer
*irb
;
498 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
500 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
504 irb
= intel_renderbuffer(rb
);
505 intel_miptree_make_shareable(brw
, irb
->mt
);
506 image
= calloc(1, sizeof *image
);
510 image
->internal_format
= rb
->InternalFormat
;
511 image
->format
= rb
->Format
;
512 image
->modifier
= tiling_to_modifier(
513 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
515 image
->data
= loaderPrivate
;
516 brw_bo_unreference(image
->bo
);
517 image
->bo
= irb
->mt
->bo
;
518 brw_bo_reference(irb
->mt
->bo
);
519 image
->width
= rb
->Width
;
520 image
->height
= rb
->Height
;
521 image
->pitch
= irb
->mt
->surf
.row_pitch
;
522 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
523 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
525 rb
->NeedsFinishRenderTexture
= true;
530 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
531 unsigned texture
, int zoffset
,
537 struct brw_context
*brw
= context
->driverPrivate
;
538 struct gl_texture_object
*obj
;
539 struct intel_texture_object
*iobj
;
542 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
543 if (!obj
|| obj
->Target
!= target
) {
544 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
548 if (target
== GL_TEXTURE_CUBE_MAP
)
551 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
552 iobj
= intel_texture_object(obj
);
553 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
554 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
558 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
559 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
563 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
564 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
567 image
= calloc(1, sizeof *image
);
569 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
573 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
574 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
575 image
->modifier
= tiling_to_modifier(
576 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
577 image
->data
= loaderPrivate
;
578 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
579 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
580 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
581 if (image
->dri_format
== MESA_FORMAT_NONE
) {
582 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
587 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
592 intel_destroy_image(__DRIimage
*image
)
594 brw_bo_unreference(image
->bo
);
598 enum modifier_priority
{
599 MODIFIER_PRIORITY_INVALID
= 0,
600 MODIFIER_PRIORITY_LINEAR
,
603 MODIFIER_PRIORITY_Y_CCS
,
606 const uint64_t priority_to_modifier
[] = {
607 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
608 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
609 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
610 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
611 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
615 select_best_modifier(struct gen_device_info
*devinfo
,
617 const uint64_t *modifiers
,
618 const unsigned count
)
620 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
622 for (int i
= 0; i
< count
; i
++) {
623 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
626 switch (modifiers
[i
]) {
627 case I915_FORMAT_MOD_Y_TILED_CCS
:
628 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
630 case I915_FORMAT_MOD_Y_TILED
:
631 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
633 case I915_FORMAT_MOD_X_TILED
:
634 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
636 case DRM_FORMAT_MOD_LINEAR
:
637 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
639 case DRM_FORMAT_MOD_INVALID
:
645 return priority_to_modifier
[prio
];
649 intel_create_image_common(__DRIscreen
*dri_screen
,
650 int width
, int height
, int format
,
652 const uint64_t *modifiers
,
657 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
658 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
661 /* Callers of this may specify a modifier, or a dri usage, but not both. The
662 * newer modifier interface deprecates the older usage flags newer modifier
663 * interface deprecates the older usage flags.
665 assert(!(use
&& count
));
667 if (use
& __DRI_IMAGE_USE_CURSOR
) {
668 if (width
!= 64 || height
!= 64)
670 modifier
= DRM_FORMAT_MOD_LINEAR
;
673 if (use
& __DRI_IMAGE_USE_LINEAR
)
674 modifier
= DRM_FORMAT_MOD_LINEAR
;
676 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
678 /* User requested specific modifiers */
679 modifier
= select_best_modifier(&screen
->devinfo
, format
,
681 if (modifier
== DRM_FORMAT_MOD_INVALID
)
684 /* Historically, X-tiled was the default, and so lack of modifier means
687 modifier
= I915_FORMAT_MOD_X_TILED
;
691 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
695 const struct isl_drm_modifier_info
*mod_info
=
696 isl_drm_modifier_get_info(modifier
);
698 struct isl_surf surf
;
699 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
700 .dim
= ISL_SURF_DIM_2D
,
701 .format
= brw_isl_format_for_mesa_format(image
->format
),
708 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
709 ISL_SURF_USAGE_TEXTURE_BIT
|
710 ISL_SURF_USAGE_STORAGE_BIT
,
711 .tiling_flags
= (1 << mod_info
->tiling
));
718 struct isl_surf aux_surf
;
719 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
720 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
726 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
730 /* We request that the bufmgr zero the buffer for us for two reasons:
732 * 1) If a buffer gets re-used from the pool, we don't want to leak random
733 * garbage from our process to some other.
735 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
736 * a valid state. A CCS value of 0 indicates that the given block is
737 * in the pass-through state which is what we want.
739 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
740 surf
.size
+ aux_surf
.size
,
741 isl_tiling_to_i915_tiling(mod_info
->tiling
),
742 surf
.row_pitch
, BO_ALLOC_ZEROED
);
743 if (image
->bo
== NULL
) {
747 image
->width
= width
;
748 image
->height
= height
;
749 image
->pitch
= surf
.row_pitch
;
750 image
->modifier
= modifier
;
753 image
->aux_offset
= surf
.size
;
754 image
->aux_pitch
= aux_surf
.row_pitch
;
755 image
->aux_size
= aux_surf
.size
;
762 intel_create_image(__DRIscreen
*dri_screen
,
763 int width
, int height
, int format
,
767 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
772 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
773 int x0
, int y0
, int width
, int height
,
774 unsigned int flags
, int *stride
, void **map_info
)
776 struct brw_context
*brw
= NULL
;
777 struct brw_bo
*bo
= NULL
;
778 void *raw_data
= NULL
;
783 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
786 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
789 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
792 if (flags
& MAP_INTERNAL_MASK
)
795 brw
= context
->driverPrivate
;
801 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
802 raw_data
= brw_bo_map(brw
, bo
, flags
);
806 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
807 pix_bytes
= _mesa_get_format_bytes(image
->format
);
811 assert(pix_bytes
> 0);
813 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
815 brw_bo_reference(bo
);
817 *stride
= image
->pitch
;
824 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
826 struct brw_bo
*bo
= map_info
;
829 brw_bo_unreference(bo
);
833 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
834 int width
, int height
, int format
,
835 const uint64_t *modifiers
,
836 const unsigned count
,
839 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
840 modifiers
, count
, loaderPrivate
);
844 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
847 case __DRI_IMAGE_ATTRIB_STRIDE
:
848 *value
= image
->pitch
;
850 case __DRI_IMAGE_ATTRIB_HANDLE
:
851 *value
= brw_bo_export_gem_handle(image
->bo
);
853 case __DRI_IMAGE_ATTRIB_NAME
:
854 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
855 case __DRI_IMAGE_ATTRIB_FORMAT
:
856 *value
= image
->dri_format
;
858 case __DRI_IMAGE_ATTRIB_WIDTH
:
859 *value
= image
->width
;
861 case __DRI_IMAGE_ATTRIB_HEIGHT
:
862 *value
= image
->height
;
864 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
865 if (image
->planar_format
== NULL
)
867 *value
= image
->planar_format
->components
;
869 case __DRI_IMAGE_ATTRIB_FD
:
870 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
871 case __DRI_IMAGE_ATTRIB_FOURCC
:
872 return intel_lookup_fourcc(image
->dri_format
, value
);
873 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
874 if (isl_drm_modifier_has_aux(image
->modifier
)) {
875 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
877 } else if (image
->planar_format
) {
878 *value
= image
->planar_format
->nplanes
;
883 case __DRI_IMAGE_ATTRIB_OFFSET
:
884 *value
= image
->offset
;
886 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
887 *value
= (image
->modifier
& 0xffffffff);
889 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
890 *value
= ((image
->modifier
>> 32) & 0xffffffff);
899 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
900 uint32_t fourcc
, uint64_t modifier
,
901 int attrib
, uint64_t *value
)
903 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
904 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
906 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
910 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
911 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
920 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
924 image
= calloc(1, sizeof *image
);
928 brw_bo_reference(orig_image
->bo
);
929 image
->bo
= orig_image
->bo
;
930 image
->internal_format
= orig_image
->internal_format
;
931 image
->planar_format
= orig_image
->planar_format
;
932 image
->dri_format
= orig_image
->dri_format
;
933 image
->format
= orig_image
->format
;
934 image
->modifier
= orig_image
->modifier
;
935 image
->offset
= orig_image
->offset
;
936 image
->width
= orig_image
->width
;
937 image
->height
= orig_image
->height
;
938 image
->pitch
= orig_image
->pitch
;
939 image
->tile_x
= orig_image
->tile_x
;
940 image
->tile_y
= orig_image
->tile_y
;
941 image
->has_depthstencil
= orig_image
->has_depthstencil
;
942 image
->data
= loaderPrivate
;
943 image
->dma_buf_imported
= orig_image
->dma_buf_imported
;
944 image
->aux_offset
= orig_image
->aux_offset
;
945 image
->aux_pitch
= orig_image
->aux_pitch
;
947 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
948 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
954 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
956 if (use
& __DRI_IMAGE_USE_CURSOR
) {
957 if (image
->width
!= 64 || image
->height
!= 64)
965 intel_create_image_from_names(__DRIscreen
*dri_screen
,
966 int width
, int height
, int fourcc
,
967 int *names
, int num_names
,
968 int *strides
, int *offsets
,
971 const struct intel_image_format
*f
= NULL
;
975 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
978 f
= intel_image_format_lookup(fourcc
);
982 image
= intel_create_image_from_name(dri_screen
, width
, height
,
983 __DRI_IMAGE_FORMAT_NONE
,
984 names
[0], strides
[0],
990 image
->planar_format
= f
;
991 for (i
= 0; i
< f
->nplanes
; i
++) {
992 index
= f
->planes
[i
].buffer_index
;
993 image
->offsets
[index
] = offsets
[index
];
994 image
->strides
[index
] = strides
[index
];
1001 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1002 int width
, int height
, int fourcc
,
1003 uint64_t modifier
, int *fds
, int num_fds
,
1004 int *strides
, int *offsets
,
1005 void *loaderPrivate
)
1007 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1008 const struct intel_image_format
*f
;
1013 if (fds
== NULL
|| num_fds
< 1)
1016 f
= intel_image_format_lookup(fourcc
);
1020 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1021 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1024 if (f
->nplanes
== 1)
1025 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1028 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1034 image
->width
= width
;
1035 image
->height
= height
;
1036 image
->pitch
= strides
[0];
1038 image
->planar_format
= f
;
1040 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1041 const struct isl_drm_modifier_info
*mod_info
=
1042 isl_drm_modifier_get_info(modifier
);
1043 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1044 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1045 tiling
, strides
[0]);
1047 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1050 if (image
->bo
== NULL
) {
1055 /* We only support all planes from the same bo.
1056 * brw_bo_gem_create_from_prime() should return the same pointer for all
1057 * fds received here */
1058 for (i
= 1; i
< num_fds
; i
++) {
1059 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1060 brw_bo_unreference(aux
);
1061 if (aux
!= image
->bo
) {
1062 brw_bo_unreference(image
->bo
);
1068 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1069 image
->modifier
= modifier
;
1071 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1073 const struct isl_drm_modifier_info
*mod_info
=
1074 isl_drm_modifier_get_info(image
->modifier
);
1077 struct isl_surf surf
;
1078 for (i
= 0; i
< f
->nplanes
; i
++) {
1079 index
= f
->planes
[i
].buffer_index
;
1080 image
->offsets
[index
] = offsets
[index
];
1081 image
->strides
[index
] = strides
[index
];
1083 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1085 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1086 .dim
= ISL_SURF_DIM_2D
,
1087 .format
= brw_isl_format_for_mesa_format(format
),
1088 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1089 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1094 .row_pitch
= strides
[index
],
1095 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1096 ISL_SURF_USAGE_TEXTURE_BIT
|
1097 ISL_SURF_USAGE_STORAGE_BIT
,
1098 .tiling_flags
= (1 << mod_info
->tiling
));
1100 brw_bo_unreference(image
->bo
);
1105 const int end
= offsets
[index
] + surf
.size
;
1110 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1111 /* Even though we initialize surf in the loop above, we know that
1112 * anything with CCS_E will have exactly one plane so surf is properly
1113 * initialized when we get here.
1115 assert(f
->nplanes
== 1);
1117 image
->aux_offset
= offsets
[1];
1118 image
->aux_pitch
= strides
[1];
1120 /* Scanout hardware requires that the CCS be placed after the main
1121 * surface in memory. We consider any CCS that is placed any earlier in
1122 * memory to be invalid and reject it.
1124 * At some point in the future, this restriction may be relaxed if the
1125 * hardware becomes less strict but we may need a new modifier for that.
1128 if (image
->aux_offset
< size
) {
1129 brw_bo_unreference(image
->bo
);
1134 struct isl_surf aux_surf
;
1135 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1138 brw_bo_unreference(image
->bo
);
1143 image
->aux_size
= aux_surf
.size
;
1145 const int end
= image
->aux_offset
+ aux_surf
.size
;
1149 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1152 /* Check that the requested image actually fits within the BO. 'size'
1153 * is already relative to the offsets, so we don't need to add that. */
1154 if (image
->bo
->size
== 0) {
1155 image
->bo
->size
= size
;
1156 } else if (size
> image
->bo
->size
) {
1157 brw_bo_unreference(image
->bo
);
1162 if (f
->nplanes
== 1) {
1163 image
->offset
= image
->offsets
[0];
1164 intel_image_warn_if_unaligned(image
, __func__
);
1171 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1172 int width
, int height
, int fourcc
,
1173 int *fds
, int num_fds
, int *strides
, int *offsets
,
1174 void *loaderPrivate
)
1176 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1177 DRM_FORMAT_MOD_INVALID
,
1178 fds
, num_fds
, strides
, offsets
,
1183 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1184 int width
, int height
,
1185 int fourcc
, uint64_t modifier
,
1186 int *fds
, int num_fds
,
1187 int *strides
, int *offsets
,
1188 enum __DRIYUVColorSpace yuv_color_space
,
1189 enum __DRISampleRange sample_range
,
1190 enum __DRIChromaSiting horizontal_siting
,
1191 enum __DRIChromaSiting vertical_siting
,
1193 void *loaderPrivate
)
1196 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1199 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1203 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1205 fds
, num_fds
, strides
, offsets
,
1209 * Invalid parameters and any inconsistencies between are assumed to be
1210 * checked by the caller. Therefore besides unsupported formats one can fail
1211 * only in allocation.
1214 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1218 image
->dma_buf_imported
= true;
1219 image
->yuv_color_space
= yuv_color_space
;
1220 image
->sample_range
= sample_range
;
1221 image
->horizontal_siting
= horizontal_siting
;
1222 image
->vertical_siting
= vertical_siting
;
1224 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1229 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1230 int width
, int height
, int fourcc
,
1231 int *fds
, int num_fds
,
1232 int *strides
, int *offsets
,
1233 enum __DRIYUVColorSpace yuv_color_space
,
1234 enum __DRISampleRange sample_range
,
1235 enum __DRIChromaSiting horizontal_siting
,
1236 enum __DRIChromaSiting vertical_siting
,
1238 void *loaderPrivate
)
1240 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1241 fourcc
, DRM_FORMAT_MOD_INVALID
,
1242 fds
, num_fds
, strides
, offsets
,
1252 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1253 int *formats
, int *count
)
1258 *count
= ARRAY_SIZE(intel_image_formats
) - 1; /* not SARGB */
1262 for (i
= 0; i
< (ARRAY_SIZE(intel_image_formats
)) && j
< max
; i
++) {
1263 if (intel_image_formats
[i
].fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
)
1265 formats
[j
++] = intel_image_formats
[i
].fourcc
;
1273 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1274 uint64_t *modifiers
,
1275 unsigned int *external_only
,
1278 struct intel_screen
*screen
= _screen
->driverPrivate
;
1279 const struct intel_image_format
*f
;
1280 int num_mods
= 0, i
;
1282 f
= intel_image_format_lookup(fourcc
);
1286 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1287 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1288 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1295 modifiers
[num_mods
- 1] = modifier
;
1296 if (num_mods
>= max
)
1300 if (external_only
!= NULL
) {
1301 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1302 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1303 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1304 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1305 external_only
[i
] = GL_TRUE
;
1308 external_only
[i
] = GL_FALSE
;
1318 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1320 int width
, height
, offset
, stride
, size
, dri_format
;
1326 width
= parent
->width
;
1327 height
= parent
->height
;
1329 const struct intel_image_format
*f
= parent
->planar_format
;
1331 if (f
&& plane
< f
->nplanes
) {
1332 /* Use the planar format definition. */
1333 width
>>= f
->planes
[plane
].width_shift
;
1334 height
>>= f
->planes
[plane
].height_shift
;
1335 dri_format
= f
->planes
[plane
].dri_format
;
1336 int index
= f
->planes
[plane
].buffer_index
;
1337 offset
= parent
->offsets
[index
];
1338 stride
= parent
->strides
[index
];
1339 size
= height
* stride
;
1340 } else if (plane
== 0) {
1341 /* The only plane of a non-planar image: copy the parent definition
1343 dri_format
= parent
->dri_format
;
1344 offset
= parent
->offset
;
1345 stride
= parent
->pitch
;
1346 size
= height
* stride
;
1347 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1348 isl_drm_modifier_has_aux(parent
->modifier
)) {
1349 /* Auxiliary plane */
1350 dri_format
= parent
->dri_format
;
1351 offset
= parent
->aux_offset
;
1352 stride
= parent
->aux_pitch
;
1353 size
= parent
->aux_size
;
1358 if (offset
+ size
> parent
->bo
->size
) {
1359 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1363 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1367 image
->bo
= parent
->bo
;
1368 brw_bo_reference(parent
->bo
);
1369 image
->modifier
= parent
->modifier
;
1371 image
->width
= width
;
1372 image
->height
= height
;
1373 image
->pitch
= stride
;
1374 image
->offset
= offset
;
1376 intel_image_warn_if_unaligned(image
, __func__
);
1381 static const __DRIimageExtension intelImageExtension
= {
1382 .base
= { __DRI_IMAGE
, 16 },
1384 .createImageFromName
= intel_create_image_from_name
,
1385 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1386 .destroyImage
= intel_destroy_image
,
1387 .createImage
= intel_create_image
,
1388 .queryImage
= intel_query_image
,
1389 .dupImage
= intel_dup_image
,
1390 .validateUsage
= intel_validate_usage
,
1391 .createImageFromNames
= intel_create_image_from_names
,
1392 .fromPlanar
= intel_from_planar
,
1393 .createImageFromTexture
= intel_create_image_from_texture
,
1394 .createImageFromFds
= intel_create_image_from_fds
,
1395 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1397 .getCapabilities
= NULL
,
1398 .mapImage
= intel_map_image
,
1399 .unmapImage
= intel_unmap_image
,
1400 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1401 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1402 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1403 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1404 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1408 get_aperture_size(int fd
)
1410 struct drm_i915_gem_get_aperture aperture
;
1412 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1415 return aperture
.aper_size
;
1419 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1420 int param
, unsigned int *value
)
1422 const struct intel_screen
*const screen
=
1423 (struct intel_screen
*) dri_screen
->driverPrivate
;
1426 case __DRI2_RENDERER_VENDOR_ID
:
1429 case __DRI2_RENDERER_DEVICE_ID
:
1430 value
[0] = screen
->deviceID
;
1432 case __DRI2_RENDERER_ACCELERATED
:
1435 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1436 /* Once a batch uses more than 75% of the maximum mappable size, we
1437 * assume that there's some fragmentation, and we start doing extra
1438 * flushing, etc. That's the big cliff apps will care about.
1440 const unsigned gpu_mappable_megabytes
=
1441 screen
->aperture_threshold
/ (1024 * 1024);
1443 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1444 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1446 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1449 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1450 * (uint64_t) system_page_size
;
1452 const unsigned system_memory_megabytes
=
1453 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1455 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1458 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1461 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1464 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1466 if (brw_hw_context_set_priority(screen
->bufmgr
,
1467 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1468 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1469 if (brw_hw_context_set_priority(screen
->bufmgr
,
1470 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1471 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1472 /* reset to default last, just in case */
1473 if (brw_hw_context_set_priority(screen
->bufmgr
,
1474 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1475 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1477 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1481 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1488 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1489 int param
, const char **value
)
1491 const struct intel_screen
*screen
=
1492 (struct intel_screen
*) dri_screen
->driverPrivate
;
1495 case __DRI2_RENDERER_VENDOR_ID
:
1496 value
[0] = brw_vendor_string
;
1498 case __DRI2_RENDERER_DEVICE_ID
:
1499 value
[0] = brw_get_renderer_string(screen
);
1509 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1510 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1512 const struct intel_screen
*const screen
=
1513 (struct intel_screen
*) dri_screen
->driverPrivate
;
1515 if (!screen
->disk_cache
)
1518 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1521 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1522 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1524 .queryInteger
= brw_query_renderer_integer
,
1525 .queryString
= brw_query_renderer_string
1528 static const __DRIrobustnessExtension dri2Robustness
= {
1529 .base
= { __DRI2_ROBUSTNESS
, 1 }
1532 static const __DRI2blobExtension intelBlobExtension
= {
1533 .base
= { __DRI2_BLOB
, 1 },
1534 .set_cache_funcs
= brw_set_cache_funcs
1537 static const __DRIextension
*screenExtensions
[] = {
1538 &intelTexBufferExtension
.base
,
1539 &intelFenceExtension
.base
,
1540 &intelFlushExtension
.base
,
1541 &intelImageExtension
.base
,
1542 &intelRendererQueryExtension
.base
,
1543 &dri2ConfigQueryExtension
.base
,
1544 &dri2NoErrorExtension
.base
,
1545 &intelBlobExtension
.base
,
1549 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1550 &intelTexBufferExtension
.base
,
1551 &intelFenceExtension
.base
,
1552 &intelFlushExtension
.base
,
1553 &intelImageExtension
.base
,
1554 &intelRendererQueryExtension
.base
,
1555 &dri2ConfigQueryExtension
.base
,
1556 &dri2Robustness
.base
,
1557 &dri2NoErrorExtension
.base
,
1558 &intelBlobExtension
.base
,
1563 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1566 struct drm_i915_getparam gp
;
1568 memset(&gp
, 0, sizeof(gp
));
1572 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1575 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1582 intel_get_boolean(struct intel_screen
*screen
, int param
)
1585 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1589 intel_get_integer(struct intel_screen
*screen
, int param
)
1593 if (intel_get_param(screen
, param
, &value
) == 0)
1600 intelDestroyScreen(__DRIscreen
* sPriv
)
1602 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1604 brw_bufmgr_destroy(screen
->bufmgr
);
1605 driDestroyOptionInfo(&screen
->optionCache
);
1607 disk_cache_destroy(screen
->disk_cache
);
1609 ralloc_free(screen
);
1610 sPriv
->driverPrivate
= NULL
;
1615 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1617 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1618 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1619 * this does not allocate GPU memory.
1622 intelCreateBuffer(__DRIscreen
*dri_screen
,
1623 __DRIdrawable
* driDrawPriv
,
1624 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1626 struct intel_renderbuffer
*rb
;
1627 struct intel_screen
*screen
= (struct intel_screen
*)
1628 dri_screen
->driverPrivate
;
1629 mesa_format rgbFormat
;
1630 unsigned num_samples
=
1631 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1636 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1640 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1642 if (screen
->winsys_msaa_samples_override
!= -1) {
1643 num_samples
= screen
->winsys_msaa_samples_override
;
1644 fb
->Visual
.samples
= num_samples
;
1647 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1648 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1649 : MESA_FORMAT_R10G10B10A2_UNORM
;
1650 } else if (mesaVis
->redBits
== 10) {
1651 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1652 : MESA_FORMAT_R10G10B10X2_UNORM
;
1653 } else if (mesaVis
->redBits
== 5) {
1654 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1655 : MESA_FORMAT_B5G6R5_UNORM
;
1656 } else if (mesaVis
->sRGBCapable
) {
1657 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1658 : MESA_FORMAT_B8G8R8A8_SRGB
;
1659 } else if (mesaVis
->alphaBits
== 0) {
1660 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1661 : MESA_FORMAT_B8G8R8X8_UNORM
;
1663 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1664 : MESA_FORMAT_B8G8R8A8_SRGB
;
1665 fb
->Visual
.sRGBCapable
= true;
1668 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1669 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1671 /* setup the hardware-based renderbuffers */
1672 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1673 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1674 rb
->need_srgb
= srgb_cap_set
;
1676 if (mesaVis
->doubleBufferMode
) {
1677 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1678 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1679 rb
->need_srgb
= srgb_cap_set
;
1683 * Assert here that the gl_config has an expected depth/stencil bit
1684 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1685 * which constructs the advertised configs.)
1687 if (mesaVis
->depthBits
== 24) {
1688 assert(mesaVis
->stencilBits
== 8);
1690 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1691 rb
= intel_create_private_renderbuffer(screen
,
1692 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1694 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1695 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1697 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1700 * Use combined depth/stencil. Note that the renderbuffer is
1701 * attached to two attachment points.
1703 rb
= intel_create_private_renderbuffer(screen
,
1704 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1706 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1707 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1710 else if (mesaVis
->depthBits
== 16) {
1711 assert(mesaVis
->stencilBits
== 0);
1712 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1714 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1717 assert(mesaVis
->depthBits
== 0);
1718 assert(mesaVis
->stencilBits
== 0);
1721 /* now add any/all software-based renderbuffers we may need */
1722 _swrast_add_soft_renderbuffers(fb
,
1723 false, /* never sw color */
1724 false, /* never sw depth */
1725 false, /* never sw stencil */
1726 mesaVis
->accumRedBits
> 0,
1727 false, /* never sw alpha */
1728 false /* never sw aux */ );
1729 driDrawPriv
->driverPrivate
= fb
;
1735 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1737 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1739 _mesa_reference_framebuffer(&fb
, NULL
);
1743 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1745 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1746 * gen10, PCI-id is enough to figure it out.
1748 assert(screen
->devinfo
.gen
>= 10);
1752 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1756 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1760 screen
->devinfo
.timestamp_frequency
= freq
;
1764 intel_detect_sseu(struct intel_screen
*screen
)
1766 assert(screen
->devinfo
.gen
>= 8);
1769 screen
->subslice_total
= -1;
1770 screen
->eu_total
= -1;
1772 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1773 &screen
->subslice_total
);
1774 if (ret
< 0 && ret
!= -EINVAL
)
1777 ret
= intel_get_param(screen
,
1778 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1779 if (ret
< 0 && ret
!= -EINVAL
)
1782 /* Without this information, we cannot get the right Braswell brandstrings,
1783 * and we have to use conservative numbers for GPGPU on many platforms, but
1784 * otherwise, things will just work.
1786 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1788 "Kernel 4.1 required to properly query GPU properties.\n");
1793 screen
->subslice_total
= -1;
1794 screen
->eu_total
= -1;
1795 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1799 intel_init_bufmgr(struct intel_screen
*screen
)
1801 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1803 if (getenv("INTEL_NO_HW") != NULL
)
1804 screen
->no_hw
= true;
1806 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1807 if (screen
->bufmgr
== NULL
) {
1808 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1809 __func__
, __LINE__
);
1813 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1814 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1822 intel_detect_swizzling(struct intel_screen
*screen
)
1824 struct brw_bo
*buffer
;
1826 uint32_t aligned_pitch
;
1827 uint32_t tiling
= I915_TILING_X
;
1828 uint32_t swizzle_mode
= 0;
1830 buffer
= brw_bo_alloc_tiled_2d(screen
->bufmgr
, "swizzle test",
1831 64, 64, 4, tiling
, &aligned_pitch
, flags
);
1835 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1836 brw_bo_unreference(buffer
);
1838 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1845 intel_detect_timestamp(struct intel_screen
*screen
)
1847 uint64_t dummy
= 0, last
= 0;
1848 int upper
, lower
, loops
;
1850 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1851 * TIMESTAMP register being shifted and the low 32bits always zero.
1853 * More recent kernels offer an interface to read the full 36bits
1856 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1859 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1860 * upper 32bits for a rapidly changing timestamp.
1862 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1866 for (loops
= 0; loops
< 10; loops
++) {
1867 /* The TIMESTAMP should change every 80ns, so several round trips
1868 * through the kernel should be enough to advance it.
1870 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1873 upper
+= (dummy
>> 32) != (last
>> 32);
1874 if (upper
> 1) /* beware 32bit counter overflow */
1875 return 2; /* upper dword holds the low 32bits of the timestamp */
1877 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1879 return 1; /* timestamp is unshifted */
1884 /* No advancement? No timestamp! */
1889 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1891 * Some combinations of hardware and kernel versions allow this feature,
1892 * while others don't. Instead of trying to enumerate every case, just
1893 * try and write a register and see if works.
1896 intel_detect_pipelined_register(struct intel_screen
*screen
,
1897 int reg
, uint32_t expected_value
, bool reset
)
1902 struct brw_bo
*results
, *bo
;
1904 uint32_t offset
= 0;
1906 bool success
= false;
1908 /* Create a zero'ed temporary buffer for reading our results */
1909 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096);
1910 if (results
== NULL
)
1913 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096);
1917 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1923 /* Write the register. */
1924 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1926 *batch
++ = expected_value
;
1928 /* Save the register's value back to the buffer. */
1929 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1931 struct drm_i915_gem_relocation_entry reloc
= {
1932 .offset
= (char *) batch
- (char *) map
,
1933 .delta
= offset
* sizeof(uint32_t),
1934 .target_handle
= results
->gem_handle
,
1935 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1936 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1938 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1940 /* And afterwards clear the register */
1942 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1947 *batch
++ = MI_BATCH_BUFFER_END
;
1949 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1951 .handle
= results
->gem_handle
,
1954 .handle
= bo
->gem_handle
,
1955 .relocation_count
= 1,
1956 .relocs_ptr
= (uintptr_t) &reloc
,
1960 struct drm_i915_gem_execbuffer2 execbuf
= {
1961 .buffers_ptr
= (uintptr_t) exec_objects
,
1963 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1964 .flags
= I915_EXEC_RENDER
,
1967 /* Don't bother with error checking - if the execbuf fails, the
1968 * value won't be written and we'll just report that there's no access.
1970 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1971 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
1973 /* Check whether the value got written. */
1974 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
1976 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
1977 brw_bo_unmap(results
);
1981 brw_bo_unreference(bo
);
1983 brw_bo_unreference(results
);
1989 intel_detect_pipelined_so(struct intel_screen
*screen
)
1991 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1993 /* Supposedly, Broadwell just works. */
1994 if (devinfo
->gen
>= 8)
1997 if (devinfo
->gen
<= 6)
2000 /* See the big explanation about command parser versions below */
2001 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2004 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2005 * statistics registers), and we already reset it to zero before using it.
2007 return intel_detect_pipelined_register(screen
,
2008 GEN7_SO_WRITE_OFFSET(0),
2014 * Return array of MSAA modes supported by the hardware. The array is
2015 * zero-terminated and sorted in decreasing order.
2018 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2020 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2021 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2022 static const int gen7_modes
[] = {8, 4, 0, -1};
2023 static const int gen6_modes
[] = {4, 0, -1};
2024 static const int gen4_modes
[] = {0, -1};
2026 if (screen
->devinfo
.gen
>= 9) {
2028 } else if (screen
->devinfo
.gen
>= 8) {
2030 } else if (screen
->devinfo
.gen
>= 7) {
2032 } else if (screen
->devinfo
.gen
== 6) {
2040 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2042 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2043 dri_screen
->dri2
.loader
->getCapability
)
2044 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2046 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2047 dri_screen
->image
.loader
->getCapability
)
2048 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2053 static __DRIconfig
**
2054 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2056 static const mesa_format formats
[] = {
2057 MESA_FORMAT_B5G6R5_UNORM
,
2058 MESA_FORMAT_B8G8R8A8_UNORM
,
2059 MESA_FORMAT_B8G8R8X8_UNORM
,
2061 MESA_FORMAT_B8G8R8A8_SRGB
,
2063 /* For 10 bpc, 30 bit depth framebuffers. */
2064 MESA_FORMAT_B10G10R10A2_UNORM
,
2065 MESA_FORMAT_B10G10R10X2_UNORM
,
2067 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2068 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2069 * server may disagree on which format the GLXFBConfig represents,
2070 * resulting in swapped color channels.
2072 * The problem, as of 2017-05-30:
2073 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2074 * order and chooses the first __DRIconfig with the expected channel
2075 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2076 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2078 * EGL does not suffer from this problem. It correctly compares the
2079 * channel masks when matching EGLConfig to __DRIconfig.
2082 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2083 MESA_FORMAT_R8G8B8A8_UNORM
,
2085 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2086 MESA_FORMAT_R8G8B8X8_UNORM
,
2089 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
2090 static const GLenum back_buffer_modes
[] = {
2091 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2094 static const uint8_t singlesample_samples
[1] = {0};
2096 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2097 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2098 uint8_t depth_bits
[4], stencil_bits
[4];
2099 __DRIconfig
**configs
= NULL
;
2101 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2102 unsigned num_formats
;
2103 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2104 num_formats
= ARRAY_SIZE(formats
);
2106 num_formats
= ARRAY_SIZE(formats
) - 2; /* all - RGBA_ORDERING formats */
2108 /* Shall we expose 10 bpc formats? */
2109 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2110 "allow_rgb10_configs");
2112 /* Generate singlesample configs without accumulation buffer. */
2113 for (unsigned i
= 0; i
< num_formats
; i
++) {
2114 __DRIconfig
**new_configs
;
2115 int num_depth_stencil_bits
= 2;
2117 if (!allow_rgb10_configs
&&
2118 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2119 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2122 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2123 * buffer that has a different number of bits per pixel than the color
2124 * buffer, gen >= 6 supports this.
2127 stencil_bits
[0] = 0;
2129 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2131 stencil_bits
[1] = 0;
2132 if (devinfo
->gen
>= 6) {
2134 stencil_bits
[2] = 8;
2135 num_depth_stencil_bits
= 3;
2139 stencil_bits
[1] = 8;
2142 new_configs
= driCreateConfigs(formats
[i
],
2145 num_depth_stencil_bits
,
2146 back_buffer_modes
, 2,
2147 singlesample_samples
, 1,
2149 configs
= driConcatConfigs(configs
, new_configs
);
2152 /* Generate the minimum possible set of configs that include an
2153 * accumulation buffer.
2155 for (unsigned i
= 0; i
< num_formats
; i
++) {
2156 __DRIconfig
**new_configs
;
2158 if (!allow_rgb10_configs
&&
2159 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2160 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2163 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2165 stencil_bits
[0] = 0;
2168 stencil_bits
[0] = 8;
2171 new_configs
= driCreateConfigs(formats
[i
],
2172 depth_bits
, stencil_bits
, 1,
2173 back_buffer_modes
, 1,
2174 singlesample_samples
, 1,
2176 configs
= driConcatConfigs(configs
, new_configs
);
2179 /* Generate multisample configs.
2181 * This loop breaks early, and hence is a no-op, on gen < 6.
2183 * Multisample configs must follow the singlesample configs in order to
2184 * work around an X server bug present in 1.12. The X server chooses to
2185 * associate the first listed RGBA888-Z24S8 config, regardless of its
2186 * sample count, with the 32-bit depth visual used for compositing.
2188 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2189 * supported. Singlebuffer configs are not supported because no one wants
2192 for (unsigned i
= 0; i
< num_formats
; i
++) {
2193 if (devinfo
->gen
< 6)
2196 if (!allow_rgb10_configs
&&
2197 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2198 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2201 __DRIconfig
**new_configs
;
2202 const int num_depth_stencil_bits
= 2;
2203 int num_msaa_modes
= 0;
2204 const uint8_t *multisample_samples
= NULL
;
2207 stencil_bits
[0] = 0;
2209 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2211 stencil_bits
[1] = 0;
2214 stencil_bits
[1] = 8;
2217 if (devinfo
->gen
>= 9) {
2218 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2219 multisample_samples
= multisample_samples_gen9
;
2220 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2221 } else if (devinfo
->gen
== 8) {
2222 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2223 multisample_samples
= multisample_samples_gen8
;
2224 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2225 } else if (devinfo
->gen
== 7) {
2226 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2227 multisample_samples
= multisample_samples_gen7
;
2228 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2229 } else if (devinfo
->gen
== 6) {
2230 static const uint8_t multisample_samples_gen6
[] = {4};
2231 multisample_samples
= multisample_samples_gen6
;
2232 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2235 new_configs
= driCreateConfigs(formats
[i
],
2238 num_depth_stencil_bits
,
2239 back_buffer_modes
, 1,
2240 multisample_samples
,
2243 configs
= driConcatConfigs(configs
, new_configs
);
2246 if (configs
== NULL
) {
2247 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2256 set_max_gl_versions(struct intel_screen
*screen
)
2258 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2259 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2261 switch (screen
->devinfo
.gen
) {
2266 dri_screen
->max_gl_core_version
= 45;
2267 dri_screen
->max_gl_compat_version
= 30;
2268 dri_screen
->max_gl_es1_version
= 11;
2269 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2272 dri_screen
->max_gl_core_version
= 33;
2273 if (can_do_pipelined_register_writes(screen
)) {
2274 dri_screen
->max_gl_core_version
= 42;
2275 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2276 dri_screen
->max_gl_core_version
= 43;
2277 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2278 dri_screen
->max_gl_core_version
= 45;
2280 dri_screen
->max_gl_compat_version
= 30;
2281 dri_screen
->max_gl_es1_version
= 11;
2282 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2285 dri_screen
->max_gl_core_version
= 33;
2286 dri_screen
->max_gl_compat_version
= 30;
2287 dri_screen
->max_gl_es1_version
= 11;
2288 dri_screen
->max_gl_es2_version
= 30;
2292 dri_screen
->max_gl_core_version
= 0;
2293 dri_screen
->max_gl_compat_version
= 21;
2294 dri_screen
->max_gl_es1_version
= 11;
2295 dri_screen
->max_gl_es2_version
= 20;
2298 unreachable("unrecognized intel_screen::gen");
2303 * Return the revision (generally the revid field of the PCI header) of the
2307 intel_device_get_revision(int fd
)
2309 struct drm_i915_getparam gp
;
2313 memset(&gp
, 0, sizeof(gp
));
2314 gp
.param
= I915_PARAM_REVISION
;
2315 gp
.value
= &revision
;
2317 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2325 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2327 struct brw_context
*brw
= (struct brw_context
*)data
;
2330 va_start(args
, fmt
);
2332 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2333 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2334 MESA_DEBUG_TYPE_OTHER
,
2335 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2340 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2342 struct brw_context
*brw
= (struct brw_context
*)data
;
2345 va_start(args
, fmt
);
2347 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2349 va_copy(args_copy
, args
);
2350 vfprintf(stderr
, fmt
, args_copy
);
2354 if (brw
->perf_debug
) {
2356 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2357 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2358 MESA_DEBUG_TYPE_PERFORMANCE
,
2359 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2365 * This is the driver specific part of the createNewScreen entry point.
2366 * Called when using DRI2.
2368 * \return the struct gl_config supported by this driver
2371 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2373 struct intel_screen
*screen
;
2375 if (dri_screen
->image
.loader
) {
2376 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2377 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2379 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2380 "support required\n");
2384 /* Allocate the private area */
2385 screen
= rzalloc(NULL
, struct intel_screen
);
2387 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2390 /* parse information in __driConfigOptions */
2391 driOptionCache options
;
2392 memset(&options
, 0, sizeof(options
));
2394 driParseOptionInfo(&options
, brw_config_options
.xml
);
2395 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
, "i965");
2396 driDestroyOptionCache(&options
);
2398 screen
->driScrnPriv
= dri_screen
;
2399 dri_screen
->driverPrivate
= (void *) screen
;
2401 screen
->deviceID
= gen_get_pci_device_id_override();
2402 if (screen
->deviceID
< 0)
2403 screen
->deviceID
= intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2405 screen
->no_hw
= true;
2407 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2410 if (!intel_init_bufmgr(screen
))
2413 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2415 brw_process_intel_debug_variable();
2417 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2419 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2420 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2423 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2424 /* Theorectically unlimited! At least for individual objects...
2426 * Currently the entire (global) address space for all GTT maps is
2427 * limited to 64bits. That is all objects on the system that are
2428 * setup for GTT mmapping must fit within 64bits. An attempt to use
2429 * one that exceeds the limit with fail in brw_bo_map_gtt().
2431 * Long before we hit that limit, we will be practically limited by
2432 * that any single object must fit in physical memory (RAM). The upper
2433 * limit on the CPU's address space is currently 48bits (Skylake), of
2434 * which only 39bits can be physical memory. (The GPU itself also has
2435 * a 48bit addressable virtual space.) We can fit over 32 million
2436 * objects of the current maximum allocable size before running out
2439 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2441 /* Estimate the size of the mappable aperture into the GTT. There's an
2442 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2443 * It turns out it's basically always 256MB, though some ancient hardware
2446 uint32_t gtt_size
= 256 * 1024 * 1024;
2448 /* We don't want to map two objects such that a memcpy between them would
2449 * just fault one mapping in and then the other over and over forever. So
2450 * we would need to divide the GTT size by 2. Additionally, some GTT is
2451 * taken up by things like the framebuffer and the ringbuffer and such, so
2452 * be more conservative.
2454 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2457 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2459 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2460 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2462 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2463 screen
->hw_has_swizzling
);
2465 if (devinfo
->gen
>= 10)
2466 intel_cs_timestamp_frequency(screen
);
2468 /* GENs prior to 8 do not support EU/Subslice info */
2469 if (devinfo
->gen
>= 8) {
2470 intel_detect_sseu(screen
);
2471 } else if (devinfo
->gen
== 7) {
2472 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2475 /* Gen7-7.5 kernel requirements / command parser saga:
2478 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2480 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2481 * all batches secure, allowing them to use any feature with no checking.
2482 * This is effectively equivalent to a command parser version of
2483 * \infinity - everything is possible.
2485 * The command parser does not exist, and querying the version will
2489 * The kernel enables the command parser by default, for systems with
2490 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2491 * hardware checker is still enabled, so Haswell and Baytrail cannot
2494 * Ivybridge goes from "everything is possible" to "only what the
2495 * command parser allows" (if the user boots with i915.cmd_parser=0,
2496 * then everything is possible again). We can only safely use features
2497 * allowed by the supported command parser version.
2499 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2500 * implemented by the kernel, even if it's turned off. So, checking
2501 * for version > 0 does not mean that you can write registers. We have
2502 * to try it and see. The version does, however, indicate the age of
2505 * Instead of matching the hardware checker's behavior of converting
2506 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2507 * -EINVAL, making it dangerous to try and use privileged features.
2509 * Effective command parser versions:
2510 * - Haswell: 0 (reporting 1, writes don't work)
2511 * - Baytrail: 0 (reporting 1, writes don't work)
2512 * - Ivybridge: 1 (enabled) or infinite (disabled)
2515 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2516 * effectively version 1 (enabled) or infinite (disabled).
2518 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2519 * Command parser v2 supports predicate writes.
2521 * - Haswell: 0 (reporting 1, writes don't work)
2522 * - Baytrail: 2 (enabled) or infinite (disabled)
2523 * - Ivybridge: 2 (enabled) or infinite (disabled)
2525 * So version >= 2 is enough to know that Ivybridge and Baytrail
2526 * will work. Haswell still can't do anything.
2528 * - v4.0: Version 3 happened. Largely not relevant.
2530 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2531 * L3 config registers are properly saved and restored as part
2532 * of the hardware context. We can approximately detect this point
2533 * in time by checking if I915_PARAM_REVISION is recognized - it
2534 * landed in a later commit, but in the same release cycle.
2536 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2537 * Command parser finally gains secure batch promotion. On Haswell,
2538 * the hardware checker gets disabled, which finally allows it to do
2539 * privileged commands.
2541 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2542 * - Haswell: 3 (enabled) or 0 (disabled)
2543 * - Baytrail: 3 (enabled) or infinite (disabled)
2544 * - Ivybridge: 3 (enabled) or infinite (disabled)
2546 * Unfortunately, detecting this point in time is tricky, because
2547 * no version bump happened when this important change occurred.
2548 * On Haswell, if we can write any register, then the kernel is at
2549 * least this new, and we can start trusting the version number.
2551 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2552 * Command parser reaches version 4, allowing access to Haswell
2553 * atomic scratch and chicken3 registers. If version >= 4, we know
2554 * the kernel is new enough to support privileged features on all
2555 * hardware. However, the user might have disabled it...and the
2556 * kernel will still report version 4. So we still have to guess
2559 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2560 * Command parser v5 whitelists indirect compute shader dispatch
2561 * registers, needed for OpenGL 4.3 and later.
2564 * Command parser v7 lets us use MI_MATH on Haswell.
2566 * Additionally, the kernel begins reporting version 0 when
2567 * the command parser is disabled, allowing us to skip the
2568 * guess-and-check step on Haswell. Unfortunately, this also
2569 * means that we can no longer use it as an indicator of the
2570 * age of the kernel.
2572 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2573 &screen
->cmd_parser_version
) < 0) {
2574 /* Command parser does not exist - getparam is unrecognized */
2575 screen
->cmd_parser_version
= 0;
2578 /* Kernel 4.13 retuired for exec object capture */
2579 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2580 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2583 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2584 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2587 if (!intel_detect_pipelined_so(screen
)) {
2588 /* We can't do anything, so the effective version is 0. */
2589 screen
->cmd_parser_version
= 0;
2591 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2594 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2595 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2597 /* Haswell requires command parser version 4 in order to have L3
2598 * atomic scratch1 and chicken3 bits
2600 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2601 screen
->kernel_features
|=
2602 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2605 /* Haswell requires command parser version 6 in order to write to the
2606 * MI_MATH GPR registers, and version 7 in order to use
2607 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2609 if (devinfo
->gen
>= 8 ||
2610 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2611 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2614 /* Gen7 needs at least command parser version 5 to support compute */
2615 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2616 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2618 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2619 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2621 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2623 screen
->winsys_msaa_samples_override
=
2624 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2625 printf("Forcing winsys sample count to %d\n",
2626 screen
->winsys_msaa_samples_override
);
2628 screen
->winsys_msaa_samples_override
= -1;
2631 set_max_gl_versions(screen
);
2633 /* Notification of GPU resets requires hardware contexts and a kernel new
2634 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2635 * supported, calling it with a context of 0 will either generate EPERM or
2636 * no error. If the ioctl is not supported, it always generate EINVAL.
2637 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2638 * extension to the loader.
2640 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2642 if (devinfo
->gen
>= 6) {
2643 struct drm_i915_reset_stats stats
;
2644 memset(&stats
, 0, sizeof(stats
));
2646 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2648 screen
->has_context_reset_notification
=
2649 (ret
!= -1 || errno
!= EINVAL
);
2652 dri_screen
->extensions
= !screen
->has_context_reset_notification
2653 ? screenExtensions
: intelRobustScreenExtensions
;
2655 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2656 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2657 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2659 /* Changing the meaning of constant buffer pointers from a dynamic state
2660 * offset to an absolute address is only safe if the kernel isolates other
2661 * contexts from our changes.
2663 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2664 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2666 screen
->compiler
->supports_pull_constants
= true;
2668 screen
->has_exec_fence
=
2669 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2671 intel_screen_init_surface_formats(screen
);
2673 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2674 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2676 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2677 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2678 fprintf(stderr
, " - User priority sorting enabled\n");
2679 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2680 fprintf(stderr
, " - Preemption enabled\n");
2684 brw_disk_cache_init(screen
);
2686 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2689 struct intel_buffer
{
2694 static __DRIbuffer
*
2695 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2696 unsigned attachment
, unsigned format
,
2697 int width
, int height
)
2699 struct intel_buffer
*intelBuffer
;
2700 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2702 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2703 attachment
== __DRI_BUFFER_BACK_LEFT
);
2705 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2706 if (intelBuffer
== NULL
)
2709 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2710 * supports Y tiled and compressed buffers, but there is no way to plumb that
2711 * through to here. */
2713 int cpp
= format
/ 8;
2714 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2715 "intelAllocateBuffer",
2719 I915_TILING_X
, &pitch
,
2722 if (intelBuffer
->bo
== NULL
) {
2727 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2729 intelBuffer
->base
.attachment
= attachment
;
2730 intelBuffer
->base
.cpp
= cpp
;
2731 intelBuffer
->base
.pitch
= pitch
;
2733 return &intelBuffer
->base
;
2737 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2739 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2741 brw_bo_unreference(intelBuffer
->bo
);
2745 static const struct __DriverAPIRec brw_driver_api
= {
2746 .InitScreen
= intelInitScreen2
,
2747 .DestroyScreen
= intelDestroyScreen
,
2748 .CreateContext
= brwCreateContext
,
2749 .DestroyContext
= intelDestroyContext
,
2750 .CreateBuffer
= intelCreateBuffer
,
2751 .DestroyBuffer
= intelDestroyBuffer
,
2752 .MakeCurrent
= intelMakeCurrent
,
2753 .UnbindContext
= intelUnbindContext
,
2754 .AllocateBuffer
= intelAllocateBuffer
,
2755 .ReleaseBuffer
= intelReleaseBuffer
2758 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2759 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2760 .vtable
= &brw_driver_api
,
2763 static const __DRIextension
*brw_driver_extensions
[] = {
2764 &driCoreExtension
.base
,
2765 &driImageDriverExtension
.base
,
2766 &driDRI2Extension
.base
,
2768 &brw_config_options
.base
,
2772 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2774 globalDriverAPI
= &brw_driver_api
;
2776 return brw_driver_extensions
;