2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_defines.h"
40 #include "compiler/nir/nir.h"
45 #ifndef DRM_FORMAT_MOD_INVALID
46 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
49 #ifndef DRM_FORMAT_MOD_LINEAR
50 #define DRM_FORMAT_MOD_LINEAR 0
53 static const __DRIconfigOptionsExtension brw_config_options
= {
54 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
57 DRI_CONF_SECTION_PERFORMANCE
58 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
59 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
60 * DRI_CONF_BO_REUSE_ALL
62 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
63 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
64 DRI_CONF_ENUM(0, "Disable buffer object reuse")
65 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
70 DRI_CONF_SECTION_QUALITY
71 DRI_CONF_FORCE_S3TC_ENABLE("false")
73 DRI_CONF_PRECISE_TRIG("false")
75 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
76 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
77 "given integer. If negative, then do not clamp.")
81 DRI_CONF_SECTION_DEBUG
82 DRI_CONF_NO_RAST("false")
83 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
84 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
85 DRI_CONF_DISABLE_THROTTLING("false")
86 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
87 DRI_CONF_FORCE_GLSL_VERSION(0)
88 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
89 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
90 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
91 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
92 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
94 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
95 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
99 DRI_CONF_SECTION_MISCELLANEOUS
100 DRI_CONF_GLSL_ZERO_INIT("false")
105 #include "intel_batchbuffer.h"
106 #include "intel_buffers.h"
107 #include "intel_bufmgr.h"
108 #include "intel_fbo.h"
109 #include "intel_mipmap_tree.h"
110 #include "intel_screen.h"
111 #include "intel_tex.h"
112 #include "intel_image.h"
114 #include "brw_context.h"
116 #include "i915_drm.h"
119 * For debugging purposes, this returns a time in seconds.
126 clock_gettime(CLOCK_MONOTONIC
, &tp
);
128 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
131 static const __DRItexBufferExtension intelTexBufferExtension
= {
132 .base
= { __DRI_TEX_BUFFER
, 3 },
134 .setTexBuffer
= intelSetTexBuffer
,
135 .setTexBuffer2
= intelSetTexBuffer2
,
136 .releaseTexBuffer
= NULL
,
140 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
141 __DRIdrawable
*dPriv
,
143 enum __DRI2throttleReason reason
)
145 struct brw_context
*brw
= cPriv
->driverPrivate
;
150 struct gl_context
*ctx
= &brw
->ctx
;
152 FLUSH_VERTICES(ctx
, 0);
154 if (flags
& __DRI2_FLUSH_DRAWABLE
)
155 intel_resolve_for_dri2_flush(brw
, dPriv
);
157 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
158 brw
->need_swap_throttle
= true;
159 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
160 brw
->need_flush_throttle
= true;
162 intel_batchbuffer_flush(brw
);
166 * Provides compatibility with loaders that only support the older (version
167 * 1-3) flush interface.
169 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
172 intel_dri2_flush(__DRIdrawable
*drawable
)
174 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
175 __DRI2_FLUSH_DRAWABLE
,
176 __DRI2_THROTTLE_SWAPBUFFER
);
179 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
180 .base
= { __DRI2_FLUSH
, 4 },
182 .flush
= intel_dri2_flush
,
183 .invalidate
= dri2InvalidateDrawable
,
184 .flush_with_flags
= intel_dri2_flush_with_flags
,
187 static struct intel_image_format intel_image_formats
[] = {
188 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
189 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
191 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
192 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
194 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
195 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
197 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
198 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
200 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
201 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
203 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
204 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
206 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
207 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
209 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
210 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
212 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
215 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
218 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
221 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
223 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
224 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
226 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
228 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
229 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
231 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
232 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
233 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
236 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
266 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
267 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
268 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
271 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
272 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
273 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
275 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
276 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
277 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
279 /* For YUYV buffers, we set up two overlapping DRI images and treat
280 * them as planar buffers in the compositors. Plane 0 is GR88 and
281 * samples YU or YV pairs and places Y into the R component, while
282 * plane 1 is ARGB and samples YUYV clusters and places pairs and
283 * places U into the G component and V into A. This lets the
284 * texture sampler interpolate the Y components correctly when
285 * sampling from plane 0, and interpolate U and V correctly when
286 * sampling from plane 1. */
287 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
288 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
289 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
293 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
295 uint32_t tiling
, swizzle
;
296 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
298 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
299 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
300 func
, image
->offset
);
304 static struct intel_image_format
*
305 intel_image_format_lookup(int fourcc
)
307 struct intel_image_format
*f
= NULL
;
309 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
310 if (intel_image_formats
[i
].fourcc
== fourcc
) {
311 f
= &intel_image_formats
[i
];
319 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
321 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
322 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
323 *fourcc
= intel_image_formats
[i
].fourcc
;
331 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
336 image
= calloc(1, sizeof *image
);
340 image
->screen
= screen
;
341 image
->dri_format
= dri_format
;
344 image
->format
= driImageFormatToGLFormat(dri_format
);
345 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
346 image
->format
== MESA_FORMAT_NONE
) {
351 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
352 image
->data
= loaderPrivate
;
358 * Sets up a DRIImage structure to point to a slice out of a miptree.
361 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
362 struct intel_mipmap_tree
*mt
, GLuint level
,
365 intel_miptree_make_shareable(brw
, mt
);
367 intel_miptree_check_level_layer(mt
, level
, zoffset
);
369 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
370 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
371 image
->pitch
= mt
->pitch
;
373 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
377 drm_intel_bo_unreference(image
->bo
);
379 drm_intel_bo_reference(mt
->bo
);
383 intel_create_image_from_name(__DRIscreen
*dri_screen
,
384 int width
, int height
, int format
,
385 int name
, int pitch
, void *loaderPrivate
)
387 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
391 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
395 if (image
->format
== MESA_FORMAT_NONE
)
398 cpp
= _mesa_get_format_bytes(image
->format
);
400 image
->width
= width
;
401 image
->height
= height
;
402 image
->pitch
= pitch
* cpp
;
403 image
->bo
= drm_intel_bo_gem_create_from_name(screen
->bufmgr
, "image",
414 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
415 int renderbuffer
, void *loaderPrivate
)
418 struct brw_context
*brw
= context
->driverPrivate
;
419 struct gl_context
*ctx
= &brw
->ctx
;
420 struct gl_renderbuffer
*rb
;
421 struct intel_renderbuffer
*irb
;
423 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
425 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
429 irb
= intel_renderbuffer(rb
);
430 intel_miptree_make_shareable(brw
, irb
->mt
);
431 image
= calloc(1, sizeof *image
);
435 image
->internal_format
= rb
->InternalFormat
;
436 image
->format
= rb
->Format
;
438 image
->data
= loaderPrivate
;
439 drm_intel_bo_unreference(image
->bo
);
440 image
->bo
= irb
->mt
->bo
;
441 drm_intel_bo_reference(irb
->mt
->bo
);
442 image
->width
= rb
->Width
;
443 image
->height
= rb
->Height
;
444 image
->pitch
= irb
->mt
->pitch
;
445 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
446 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
448 rb
->NeedsFinishRenderTexture
= true;
453 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
454 unsigned texture
, int zoffset
,
460 struct brw_context
*brw
= context
->driverPrivate
;
461 struct gl_texture_object
*obj
;
462 struct intel_texture_object
*iobj
;
465 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
466 if (!obj
|| obj
->Target
!= target
) {
467 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
471 if (target
== GL_TEXTURE_CUBE_MAP
)
474 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
475 iobj
= intel_texture_object(obj
);
476 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
477 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
481 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
482 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
486 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
487 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
490 image
= calloc(1, sizeof *image
);
492 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
496 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
497 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
498 image
->data
= loaderPrivate
;
499 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
500 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
501 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
502 if (image
->dri_format
== MESA_FORMAT_NONE
) {
503 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
508 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
513 intel_destroy_image(__DRIimage
*image
)
515 drm_intel_bo_unreference(image
->bo
);
519 enum modifier_priority
{
520 MODIFIER_PRIORITY_INVALID
= 0,
521 MODIFIER_PRIORITY_LINEAR
,
526 const uint64_t priority_to_modifier
[] = {
527 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
528 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
529 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
530 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
534 select_best_modifier(struct gen_device_info
*devinfo
,
535 const uint64_t *modifiers
,
536 const unsigned count
)
538 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
540 for (int i
= 0; i
< count
; i
++) {
541 switch (modifiers
[i
]) {
542 case I915_FORMAT_MOD_Y_TILED
:
543 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
545 case I915_FORMAT_MOD_X_TILED
:
546 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
548 case DRM_FORMAT_MOD_LINEAR
:
549 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
551 case DRM_FORMAT_MOD_INVALID
:
557 return priority_to_modifier
[prio
];
561 intel_create_image_common(__DRIscreen
*dri_screen
,
562 int width
, int height
, int format
,
564 const uint64_t *modifiers
,
569 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
570 /* Historically, X-tiled was the default, and so lack of modifier means
573 uint32_t tiling
= I915_TILING_X
;
577 /* Callers of this may specify a modifier, or a dri usage, but not both. The
578 * newer modifier interface deprecates the older usage flags newer modifier
579 * interface deprecates the older usage flags.
581 assert(!(use
&& count
));
583 uint64_t modifier
= select_best_modifier(&screen
->devinfo
, modifiers
, count
);
585 case I915_FORMAT_MOD_X_TILED
:
586 assert(tiling
== I915_TILING_X
);
588 case DRM_FORMAT_MOD_LINEAR
:
589 tiling
= I915_TILING_NONE
;
591 case I915_FORMAT_MOD_Y_TILED
:
592 tiling
= I915_TILING_Y
;
594 case DRM_FORMAT_MOD_INVALID
:
601 if (use
& __DRI_IMAGE_USE_CURSOR
) {
602 if (width
!= 64 || height
!= 64)
604 tiling
= I915_TILING_NONE
;
607 if (use
& __DRI_IMAGE_USE_LINEAR
)
608 tiling
= I915_TILING_NONE
;
610 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
614 cpp
= _mesa_get_format_bytes(image
->format
);
615 image
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "image",
616 width
, height
, cpp
, &tiling
,
618 if (image
->bo
== NULL
) {
622 image
->width
= width
;
623 image
->height
= height
;
624 image
->pitch
= pitch
;
625 image
->modifier
= modifier
;
631 intel_create_image(__DRIscreen
*dri_screen
,
632 int width
, int height
, int format
,
636 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
641 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
642 int width
, int height
, int format
,
643 const uint64_t *modifiers
,
644 const unsigned count
,
647 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
648 modifiers
, count
, loaderPrivate
);
652 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
655 case __DRI_IMAGE_ATTRIB_STRIDE
:
656 *value
= image
->pitch
;
658 case __DRI_IMAGE_ATTRIB_HANDLE
:
659 *value
= image
->bo
->handle
;
661 case __DRI_IMAGE_ATTRIB_NAME
:
662 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
663 case __DRI_IMAGE_ATTRIB_FORMAT
:
664 *value
= image
->dri_format
;
666 case __DRI_IMAGE_ATTRIB_WIDTH
:
667 *value
= image
->width
;
669 case __DRI_IMAGE_ATTRIB_HEIGHT
:
670 *value
= image
->height
;
672 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
673 if (image
->planar_format
== NULL
)
675 *value
= image
->planar_format
->components
;
677 case __DRI_IMAGE_ATTRIB_FD
:
678 return !drm_intel_bo_gem_export_to_prime(image
->bo
, value
);
679 case __DRI_IMAGE_ATTRIB_FOURCC
:
680 return intel_lookup_fourcc(image
->dri_format
, value
);
681 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
684 case __DRI_IMAGE_ATTRIB_OFFSET
:
685 *value
= image
->offset
;
687 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
688 *value
= (image
->modifier
& 0xffffffff);
690 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
691 *value
= ((image
->modifier
>> 32) & 0xffffffff);
700 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
704 image
= calloc(1, sizeof *image
);
708 drm_intel_bo_reference(orig_image
->bo
);
709 image
->bo
= orig_image
->bo
;
710 image
->internal_format
= orig_image
->internal_format
;
711 image
->planar_format
= orig_image
->planar_format
;
712 image
->dri_format
= orig_image
->dri_format
;
713 image
->format
= orig_image
->format
;
714 image
->offset
= orig_image
->offset
;
715 image
->width
= orig_image
->width
;
716 image
->height
= orig_image
->height
;
717 image
->pitch
= orig_image
->pitch
;
718 image
->tile_x
= orig_image
->tile_x
;
719 image
->tile_y
= orig_image
->tile_y
;
720 image
->has_depthstencil
= orig_image
->has_depthstencil
;
721 image
->data
= loaderPrivate
;
723 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
724 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
730 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
732 if (use
& __DRI_IMAGE_USE_CURSOR
) {
733 if (image
->width
!= 64 || image
->height
!= 64)
741 intel_create_image_from_names(__DRIscreen
*dri_screen
,
742 int width
, int height
, int fourcc
,
743 int *names
, int num_names
,
744 int *strides
, int *offsets
,
747 struct intel_image_format
*f
= NULL
;
751 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
754 f
= intel_image_format_lookup(fourcc
);
758 image
= intel_create_image_from_name(dri_screen
, width
, height
,
759 __DRI_IMAGE_FORMAT_NONE
,
760 names
[0], strides
[0],
766 image
->planar_format
= f
;
767 for (i
= 0; i
< f
->nplanes
; i
++) {
768 index
= f
->planes
[i
].buffer_index
;
769 image
->offsets
[index
] = offsets
[index
];
770 image
->strides
[index
] = strides
[index
];
777 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
778 int width
, int height
, int fourcc
,
779 int *fds
, int num_fds
, int *strides
, int *offsets
,
782 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
783 struct intel_image_format
*f
;
787 if (fds
== NULL
|| num_fds
< 1)
790 /* We only support all planes from the same bo */
791 for (i
= 0; i
< num_fds
; i
++)
792 if (fds
[0] != fds
[i
])
795 f
= intel_image_format_lookup(fourcc
);
800 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
803 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
809 image
->width
= width
;
810 image
->height
= height
;
811 image
->pitch
= strides
[0];
813 image
->planar_format
= f
;
815 for (i
= 0; i
< f
->nplanes
; i
++) {
816 index
= f
->planes
[i
].buffer_index
;
817 image
->offsets
[index
] = offsets
[index
];
818 image
->strides
[index
] = strides
[index
];
820 const int plane_height
= height
>> f
->planes
[i
].height_shift
;
821 const int end
= offsets
[index
] + plane_height
* strides
[index
];
826 image
->bo
= drm_intel_bo_gem_create_from_prime(screen
->bufmgr
,
828 if (image
->bo
== NULL
) {
833 if (f
->nplanes
== 1) {
834 image
->offset
= image
->offsets
[0];
835 intel_image_warn_if_unaligned(image
, __func__
);
842 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
843 int width
, int height
, int fourcc
,
844 int *fds
, int num_fds
,
845 int *strides
, int *offsets
,
846 enum __DRIYUVColorSpace yuv_color_space
,
847 enum __DRISampleRange sample_range
,
848 enum __DRIChromaSiting horizontal_siting
,
849 enum __DRIChromaSiting vertical_siting
,
854 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
857 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
861 image
= intel_create_image_from_fds(dri_screen
, width
, height
, fourcc
, fds
,
862 num_fds
, strides
, offsets
,
866 * Invalid parameters and any inconsistencies between are assumed to be
867 * checked by the caller. Therefore besides unsupported formats one can fail
868 * only in allocation.
871 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
875 image
->dma_buf_imported
= true;
876 image
->yuv_color_space
= yuv_color_space
;
877 image
->sample_range
= sample_range
;
878 image
->horizontal_siting
= horizontal_siting
;
879 image
->vertical_siting
= vertical_siting
;
881 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
886 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
888 int width
, height
, offset
, stride
, dri_format
, index
;
889 struct intel_image_format
*f
;
892 if (parent
== NULL
|| parent
->planar_format
== NULL
)
895 f
= parent
->planar_format
;
897 if (plane
>= f
->nplanes
)
900 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
901 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
902 dri_format
= f
->planes
[plane
].dri_format
;
903 index
= f
->planes
[plane
].buffer_index
;
904 offset
= parent
->offsets
[index
];
905 stride
= parent
->strides
[index
];
907 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
911 if (offset
+ height
* stride
> parent
->bo
->size
) {
912 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
917 image
->bo
= parent
->bo
;
918 drm_intel_bo_reference(parent
->bo
);
920 image
->width
= width
;
921 image
->height
= height
;
922 image
->pitch
= stride
;
923 image
->offset
= offset
;
925 intel_image_warn_if_unaligned(image
, __func__
);
930 static const __DRIimageExtension intelImageExtension
= {
931 .base
= { __DRI_IMAGE
, 14 },
933 .createImageFromName
= intel_create_image_from_name
,
934 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
935 .destroyImage
= intel_destroy_image
,
936 .createImage
= intel_create_image
,
937 .queryImage
= intel_query_image
,
938 .dupImage
= intel_dup_image
,
939 .validateUsage
= intel_validate_usage
,
940 .createImageFromNames
= intel_create_image_from_names
,
941 .fromPlanar
= intel_from_planar
,
942 .createImageFromTexture
= intel_create_image_from_texture
,
943 .createImageFromFds
= intel_create_image_from_fds
,
944 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
946 .getCapabilities
= NULL
,
949 .createImageWithModifiers
= intel_create_image_with_modifiers
,
953 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
954 int param
, unsigned int *value
)
956 const struct intel_screen
*const screen
=
957 (struct intel_screen
*) dri_screen
->driverPrivate
;
960 case __DRI2_RENDERER_VENDOR_ID
:
963 case __DRI2_RENDERER_DEVICE_ID
:
964 value
[0] = screen
->deviceID
;
966 case __DRI2_RENDERER_ACCELERATED
:
969 case __DRI2_RENDERER_VIDEO_MEMORY
: {
970 /* Once a batch uses more than 75% of the maximum mappable size, we
971 * assume that there's some fragmentation, and we start doing extra
972 * flushing, etc. That's the big cliff apps will care about.
975 size_t mappable_size
;
977 drm_intel_get_aperture_sizes(dri_screen
->fd
, &mappable_size
, &aper_size
);
979 const unsigned gpu_mappable_megabytes
=
980 (aper_size
/ (1024 * 1024)) * 3 / 4;
982 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
983 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
985 if (system_memory_pages
<= 0 || system_page_size
<= 0)
988 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
989 * (uint64_t) system_page_size
;
991 const unsigned system_memory_megabytes
=
992 (unsigned) (system_memory_bytes
/ (1024 * 1024));
994 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
997 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1000 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1004 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1011 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1012 int param
, const char **value
)
1014 const struct intel_screen
*screen
=
1015 (struct intel_screen
*) dri_screen
->driverPrivate
;
1018 case __DRI2_RENDERER_VENDOR_ID
:
1019 value
[0] = brw_vendor_string
;
1021 case __DRI2_RENDERER_DEVICE_ID
:
1022 value
[0] = brw_get_renderer_string(screen
);
1031 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1032 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1034 .queryInteger
= brw_query_renderer_integer
,
1035 .queryString
= brw_query_renderer_string
1038 static const __DRIrobustnessExtension dri2Robustness
= {
1039 .base
= { __DRI2_ROBUSTNESS
, 1 }
1042 static const __DRIextension
*screenExtensions
[] = {
1043 &intelTexBufferExtension
.base
,
1044 &intelFenceExtension
.base
,
1045 &intelFlushExtension
.base
,
1046 &intelImageExtension
.base
,
1047 &intelRendererQueryExtension
.base
,
1048 &dri2ConfigQueryExtension
.base
,
1052 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1053 &intelTexBufferExtension
.base
,
1054 &intelFenceExtension
.base
,
1055 &intelFlushExtension
.base
,
1056 &intelImageExtension
.base
,
1057 &intelRendererQueryExtension
.base
,
1058 &dri2ConfigQueryExtension
.base
,
1059 &dri2Robustness
.base
,
1064 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1067 struct drm_i915_getparam gp
;
1069 memset(&gp
, 0, sizeof(gp
));
1073 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1076 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1083 intel_get_boolean(struct intel_screen
*screen
, int param
)
1086 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1090 intel_get_integer(struct intel_screen
*screen
, int param
)
1094 if (intel_get_param(screen
, param
, &value
) == 0)
1101 intelDestroyScreen(__DRIscreen
* sPriv
)
1103 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1105 dri_bufmgr_destroy(screen
->bufmgr
);
1106 driDestroyOptionInfo(&screen
->optionCache
);
1108 ralloc_free(screen
);
1109 sPriv
->driverPrivate
= NULL
;
1114 * This is called when we need to set up GL rendering to a new X window.
1117 intelCreateBuffer(__DRIscreen
*dri_screen
,
1118 __DRIdrawable
* driDrawPriv
,
1119 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1121 struct intel_renderbuffer
*rb
;
1122 struct intel_screen
*screen
= (struct intel_screen
*)
1123 dri_screen
->driverPrivate
;
1124 mesa_format rgbFormat
;
1125 unsigned num_samples
=
1126 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1127 struct gl_framebuffer
*fb
;
1132 fb
= CALLOC_STRUCT(gl_framebuffer
);
1136 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1138 if (screen
->winsys_msaa_samples_override
!= -1) {
1139 num_samples
= screen
->winsys_msaa_samples_override
;
1140 fb
->Visual
.samples
= num_samples
;
1143 if (mesaVis
->redBits
== 5) {
1144 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1145 : MESA_FORMAT_B5G6R5_UNORM
;
1146 } else if (mesaVis
->sRGBCapable
) {
1147 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1148 : MESA_FORMAT_B8G8R8A8_SRGB
;
1149 } else if (mesaVis
->alphaBits
== 0) {
1150 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1151 : MESA_FORMAT_B8G8R8X8_UNORM
;
1153 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1154 : MESA_FORMAT_B8G8R8A8_SRGB
;
1155 fb
->Visual
.sRGBCapable
= true;
1158 /* setup the hardware-based renderbuffers */
1159 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1160 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1162 if (mesaVis
->doubleBufferMode
) {
1163 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1164 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1168 * Assert here that the gl_config has an expected depth/stencil bit
1169 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1170 * which constructs the advertised configs.)
1172 if (mesaVis
->depthBits
== 24) {
1173 assert(mesaVis
->stencilBits
== 8);
1175 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1176 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1178 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1179 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1181 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1184 * Use combined depth/stencil. Note that the renderbuffer is
1185 * attached to two attachment points.
1187 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1189 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1190 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1193 else if (mesaVis
->depthBits
== 16) {
1194 assert(mesaVis
->stencilBits
== 0);
1195 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1197 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1200 assert(mesaVis
->depthBits
== 0);
1201 assert(mesaVis
->stencilBits
== 0);
1204 /* now add any/all software-based renderbuffers we may need */
1205 _swrast_add_soft_renderbuffers(fb
,
1206 false, /* never sw color */
1207 false, /* never sw depth */
1208 false, /* never sw stencil */
1209 mesaVis
->accumRedBits
> 0,
1210 false, /* never sw alpha */
1211 false /* never sw aux */ );
1212 driDrawPriv
->driverPrivate
= fb
;
1218 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1220 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1222 _mesa_reference_framebuffer(&fb
, NULL
);
1226 intel_detect_sseu(struct intel_screen
*screen
)
1228 assert(screen
->devinfo
.gen
>= 8);
1231 screen
->subslice_total
= -1;
1232 screen
->eu_total
= -1;
1234 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1235 &screen
->subslice_total
);
1236 if (ret
< 0 && ret
!= -EINVAL
)
1239 ret
= intel_get_param(screen
,
1240 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1241 if (ret
< 0 && ret
!= -EINVAL
)
1244 /* Without this information, we cannot get the right Braswell brandstrings,
1245 * and we have to use conservative numbers for GPGPU on many platforms, but
1246 * otherwise, things will just work.
1248 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1250 "Kernel 4.1 required to properly query GPU properties.\n");
1255 screen
->subslice_total
= -1;
1256 screen
->eu_total
= -1;
1257 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1261 intel_init_bufmgr(struct intel_screen
*screen
)
1263 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1265 screen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1267 screen
->bufmgr
= intel_bufmgr_gem_init(dri_screen
->fd
, BATCH_SZ
);
1268 if (screen
->bufmgr
== NULL
) {
1269 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1270 __func__
, __LINE__
);
1274 drm_intel_bufmgr_gem_enable_fenced_relocs(screen
->bufmgr
);
1276 if (!intel_get_boolean(screen
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1277 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1285 intel_detect_swizzling(struct intel_screen
*screen
)
1287 drm_intel_bo
*buffer
;
1288 unsigned long flags
= 0;
1289 unsigned long aligned_pitch
;
1290 uint32_t tiling
= I915_TILING_X
;
1291 uint32_t swizzle_mode
= 0;
1293 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1295 &tiling
, &aligned_pitch
, flags
);
1299 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1300 drm_intel_bo_unreference(buffer
);
1302 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1309 intel_detect_timestamp(struct intel_screen
*screen
)
1311 uint64_t dummy
= 0, last
= 0;
1312 int upper
, lower
, loops
;
1314 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1315 * TIMESTAMP register being shifted and the low 32bits always zero.
1317 * More recent kernels offer an interface to read the full 36bits
1320 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1323 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1324 * upper 32bits for a rapidly changing timestamp.
1326 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1330 for (loops
= 0; loops
< 10; loops
++) {
1331 /* The TIMESTAMP should change every 80ns, so several round trips
1332 * through the kernel should be enough to advance it.
1334 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1337 upper
+= (dummy
>> 32) != (last
>> 32);
1338 if (upper
> 1) /* beware 32bit counter overflow */
1339 return 2; /* upper dword holds the low 32bits of the timestamp */
1341 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1343 return 1; /* timestamp is unshifted */
1348 /* No advancement? No timestamp! */
1353 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1355 * Some combinations of hardware and kernel versions allow this feature,
1356 * while others don't. Instead of trying to enumerate every case, just
1357 * try and write a register and see if works.
1360 intel_detect_pipelined_register(struct intel_screen
*screen
,
1361 int reg
, uint32_t expected_value
, bool reset
)
1363 drm_intel_bo
*results
, *bo
;
1365 uint32_t offset
= 0;
1366 bool success
= false;
1368 /* Create a zero'ed temporary buffer for reading our results */
1369 results
= drm_intel_bo_alloc(screen
->bufmgr
, "registers", 4096, 0);
1370 if (results
== NULL
)
1373 bo
= drm_intel_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, 0);
1377 if (drm_intel_bo_map(bo
, 1))
1380 batch
= bo
->virtual;
1382 /* Write the register. */
1383 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1385 *batch
++ = expected_value
;
1387 /* Save the register's value back to the buffer. */
1388 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1390 drm_intel_bo_emit_reloc(bo
, (char *)batch
-(char *)bo
->virtual,
1391 results
, offset
*sizeof(uint32_t),
1392 I915_GEM_DOMAIN_INSTRUCTION
,
1393 I915_GEM_DOMAIN_INSTRUCTION
);
1394 *batch
++ = results
->offset
+ offset
*sizeof(uint32_t);
1396 /* And afterwards clear the register */
1398 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1403 *batch
++ = MI_BATCH_BUFFER_END
;
1405 drm_intel_bo_mrb_exec(bo
, ALIGN((char *)batch
- (char *)bo
->virtual, 8),
1409 /* Check whether the value got written. */
1410 if (drm_intel_bo_map(results
, false) == 0) {
1411 success
= *((uint32_t *)results
->virtual + offset
) == expected_value
;
1412 drm_intel_bo_unmap(results
);
1416 drm_intel_bo_unreference(bo
);
1418 drm_intel_bo_unreference(results
);
1424 intel_detect_pipelined_so(struct intel_screen
*screen
)
1426 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1428 /* Supposedly, Broadwell just works. */
1429 if (devinfo
->gen
>= 8)
1432 if (devinfo
->gen
<= 6)
1435 /* See the big explanation about command parser versions below */
1436 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
1439 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
1440 * statistics registers), and we already reset it to zero before using it.
1442 return intel_detect_pipelined_register(screen
,
1443 GEN7_SO_WRITE_OFFSET(0),
1449 * Return array of MSAA modes supported by the hardware. The array is
1450 * zero-terminated and sorted in decreasing order.
1453 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1455 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
1456 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1457 static const int gen7_modes
[] = {8, 4, 0, -1};
1458 static const int gen6_modes
[] = {4, 0, -1};
1459 static const int gen4_modes
[] = {0, -1};
1461 if (screen
->devinfo
.gen
>= 9) {
1463 } else if (screen
->devinfo
.gen
>= 8) {
1465 } else if (screen
->devinfo
.gen
>= 7) {
1467 } else if (screen
->devinfo
.gen
== 6) {
1474 static __DRIconfig
**
1475 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1477 static const mesa_format formats
[] = {
1478 MESA_FORMAT_B5G6R5_UNORM
,
1479 MESA_FORMAT_B8G8R8A8_UNORM
,
1480 MESA_FORMAT_B8G8R8X8_UNORM
1483 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1484 static const GLenum back_buffer_modes
[] = {
1485 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1488 static const uint8_t singlesample_samples
[1] = {0};
1489 static const uint8_t multisample_samples
[2] = {4, 8};
1491 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1492 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1493 uint8_t depth_bits
[4], stencil_bits
[4];
1494 __DRIconfig
**configs
= NULL
;
1496 /* Generate singlesample configs without accumulation buffer. */
1497 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1498 __DRIconfig
**new_configs
;
1499 int num_depth_stencil_bits
= 2;
1501 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1502 * buffer that has a different number of bits per pixel than the color
1503 * buffer, gen >= 6 supports this.
1506 stencil_bits
[0] = 0;
1508 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1510 stencil_bits
[1] = 0;
1511 if (devinfo
->gen
>= 6) {
1513 stencil_bits
[2] = 8;
1514 num_depth_stencil_bits
= 3;
1518 stencil_bits
[1] = 8;
1521 new_configs
= driCreateConfigs(formats
[i
],
1524 num_depth_stencil_bits
,
1525 back_buffer_modes
, 2,
1526 singlesample_samples
, 1,
1528 configs
= driConcatConfigs(configs
, new_configs
);
1531 /* Generate the minimum possible set of configs that include an
1532 * accumulation buffer.
1534 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1535 __DRIconfig
**new_configs
;
1537 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1539 stencil_bits
[0] = 0;
1542 stencil_bits
[0] = 8;
1545 new_configs
= driCreateConfigs(formats
[i
],
1546 depth_bits
, stencil_bits
, 1,
1547 back_buffer_modes
, 1,
1548 singlesample_samples
, 1,
1550 configs
= driConcatConfigs(configs
, new_configs
);
1553 /* Generate multisample configs.
1555 * This loop breaks early, and hence is a no-op, on gen < 6.
1557 * Multisample configs must follow the singlesample configs in order to
1558 * work around an X server bug present in 1.12. The X server chooses to
1559 * associate the first listed RGBA888-Z24S8 config, regardless of its
1560 * sample count, with the 32-bit depth visual used for compositing.
1562 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1563 * supported. Singlebuffer configs are not supported because no one wants
1566 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1567 if (devinfo
->gen
< 6)
1570 __DRIconfig
**new_configs
;
1571 const int num_depth_stencil_bits
= 2;
1572 int num_msaa_modes
= 0;
1575 stencil_bits
[0] = 0;
1577 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1579 stencil_bits
[1] = 0;
1582 stencil_bits
[1] = 8;
1585 if (devinfo
->gen
>= 7)
1587 else if (devinfo
->gen
== 6)
1590 new_configs
= driCreateConfigs(formats
[i
],
1593 num_depth_stencil_bits
,
1594 back_buffer_modes
, 1,
1595 multisample_samples
,
1598 configs
= driConcatConfigs(configs
, new_configs
);
1601 if (configs
== NULL
) {
1602 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1611 set_max_gl_versions(struct intel_screen
*screen
)
1613 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1614 const bool has_astc
= screen
->devinfo
.gen
>= 9;
1616 switch (screen
->devinfo
.gen
) {
1619 dri_screen
->max_gl_core_version
= 45;
1620 dri_screen
->max_gl_compat_version
= 30;
1621 dri_screen
->max_gl_es1_version
= 11;
1622 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
1625 dri_screen
->max_gl_core_version
= 33;
1626 if (screen
->devinfo
.is_haswell
&&
1627 can_do_pipelined_register_writes(screen
)) {
1628 dri_screen
->max_gl_core_version
= 42;
1629 if (can_do_compute_dispatch(screen
))
1630 dri_screen
->max_gl_core_version
= 43;
1631 if (can_do_mi_math_and_lrr(screen
))
1632 dri_screen
->max_gl_core_version
= 45;
1634 dri_screen
->max_gl_compat_version
= 30;
1635 dri_screen
->max_gl_es1_version
= 11;
1636 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
1639 dri_screen
->max_gl_core_version
= 33;
1640 dri_screen
->max_gl_compat_version
= 30;
1641 dri_screen
->max_gl_es1_version
= 11;
1642 dri_screen
->max_gl_es2_version
= 30;
1646 dri_screen
->max_gl_core_version
= 0;
1647 dri_screen
->max_gl_compat_version
= 21;
1648 dri_screen
->max_gl_es1_version
= 11;
1649 dri_screen
->max_gl_es2_version
= 20;
1652 unreachable("unrecognized intel_screen::gen");
1657 * Return the revision (generally the revid field of the PCI header) of the
1660 * XXX: This function is useful to keep around even if it is not currently in
1661 * use. It is necessary for new platforms and revision specific workarounds or
1662 * features. Please don't remove it so that we know it at least continues to
1665 static __attribute__((__unused__
)) int
1666 brw_get_revision(int fd
)
1668 struct drm_i915_getparam gp
;
1672 memset(&gp
, 0, sizeof(gp
));
1673 gp
.param
= I915_PARAM_REVISION
;
1674 gp
.value
= &revision
;
1676 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1684 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
1686 struct brw_context
*brw
= (struct brw_context
*)data
;
1689 va_start(args
, fmt
);
1691 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1692 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1693 MESA_DEBUG_TYPE_OTHER
,
1694 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
1699 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
1701 struct brw_context
*brw
= (struct brw_context
*)data
;
1704 va_start(args
, fmt
);
1706 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1708 va_copy(args_copy
, args
);
1709 vfprintf(stderr
, fmt
, args_copy
);
1713 if (brw
->perf_debug
) {
1715 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
1716 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
1717 MESA_DEBUG_TYPE_PERFORMANCE
,
1718 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
1724 * This is the driver specific part of the createNewScreen entry point.
1725 * Called when using DRI2.
1727 * \return the struct gl_config supported by this driver
1730 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
1732 struct intel_screen
*screen
;
1734 if (dri_screen
->image
.loader
) {
1735 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
1736 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1738 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1739 "support required\n");
1743 /* Allocate the private area */
1744 screen
= rzalloc(NULL
, struct intel_screen
);
1746 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1749 /* parse information in __driConfigOptions */
1750 driParseOptionInfo(&screen
->optionCache
, brw_config_options
.xml
);
1752 screen
->driScrnPriv
= dri_screen
;
1753 dri_screen
->driverPrivate
= (void *) screen
;
1755 if (!intel_init_bufmgr(screen
))
1758 screen
->deviceID
= drm_intel_bufmgr_gem_get_devid(screen
->bufmgr
);
1759 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
1762 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
1764 brw_process_intel_debug_variable();
1766 if (INTEL_DEBUG
& DEBUG_BUFMGR
)
1767 dri_bufmgr_set_debug(screen
->bufmgr
, true);
1769 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
1771 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
1772 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
1775 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
1776 /* Theorectically unlimited! At least for individual objects...
1778 * Currently the entire (global) address space for all GTT maps is
1779 * limited to 64bits. That is all objects on the system that are
1780 * setup for GTT mmapping must fit within 64bits. An attempt to use
1781 * one that exceeds the limit with fail in drm_intel_bo_map_gtt().
1783 * Long before we hit that limit, we will be practically limited by
1784 * that any single object must fit in physical memory (RAM). The upper
1785 * limit on the CPU's address space is currently 48bits (Skylake), of
1786 * which only 39bits can be physical memory. (The GPU itself also has
1787 * a 48bit addressable virtual space.) We can fit over 32 million
1788 * objects of the current maximum allocable size before running out
1791 screen
->max_gtt_map_object_size
= UINT64_MAX
;
1793 /* Estimate the size of the mappable aperture into the GTT. There's an
1794 * ioctl to get the whole GTT size, but not one to get the mappable subset.
1795 * It turns out it's basically always 256MB, though some ancient hardware
1798 uint32_t gtt_size
= 256 * 1024 * 1024;
1800 /* We don't want to map two objects such that a memcpy between them would
1801 * just fault one mapping in and then the other over and over forever. So
1802 * we would need to divide the GTT size by 2. Additionally, some GTT is
1803 * taken up by things like the framebuffer and the ringbuffer and such, so
1804 * be more conservative.
1806 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
1809 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
1810 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
1812 /* GENs prior to 8 do not support EU/Subslice info */
1813 if (devinfo
->gen
>= 8) {
1814 intel_detect_sseu(screen
);
1815 } else if (devinfo
->gen
== 7) {
1816 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
1819 /* Gen7-7.5 kernel requirements / command parser saga:
1822 * Haswell and Baytrail cannot use any privileged batchbuffer features.
1824 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
1825 * all batches secure, allowing them to use any feature with no checking.
1826 * This is effectively equivalent to a command parser version of
1827 * \infinity - everything is possible.
1829 * The command parser does not exist, and querying the version will
1833 * The kernel enables the command parser by default, for systems with
1834 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
1835 * hardware checker is still enabled, so Haswell and Baytrail cannot
1838 * Ivybridge goes from "everything is possible" to "only what the
1839 * command parser allows" (if the user boots with i915.cmd_parser=0,
1840 * then everything is possible again). We can only safely use features
1841 * allowed by the supported command parser version.
1843 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
1844 * implemented by the kernel, even if it's turned off. So, checking
1845 * for version > 0 does not mean that you can write registers. We have
1846 * to try it and see. The version does, however, indicate the age of
1849 * Instead of matching the hardware checker's behavior of converting
1850 * privileged commands to MI_NOOP, it makes execbuf2 start returning
1851 * -EINVAL, making it dangerous to try and use privileged features.
1853 * Effective command parser versions:
1854 * - Haswell: 0 (reporting 1, writes don't work)
1855 * - Baytrail: 0 (reporting 1, writes don't work)
1856 * - Ivybridge: 1 (enabled) or infinite (disabled)
1859 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
1860 * effectively version 1 (enabled) or infinite (disabled).
1862 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
1863 * Command parser v2 supports predicate writes.
1865 * - Haswell: 0 (reporting 1, writes don't work)
1866 * - Baytrail: 2 (enabled) or infinite (disabled)
1867 * - Ivybridge: 2 (enabled) or infinite (disabled)
1869 * So version >= 2 is enough to know that Ivybridge and Baytrail
1870 * will work. Haswell still can't do anything.
1872 * - v4.0: Version 3 happened. Largely not relevant.
1874 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
1875 * L3 config registers are properly saved and restored as part
1876 * of the hardware context. We can approximately detect this point
1877 * in time by checking if I915_PARAM_REVISION is recognized - it
1878 * landed in a later commit, but in the same release cycle.
1880 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
1881 * Command parser finally gains secure batch promotion. On Haswell,
1882 * the hardware checker gets disabled, which finally allows it to do
1883 * privileged commands.
1885 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
1886 * - Haswell: 3 (enabled) or 0 (disabled)
1887 * - Baytrail: 3 (enabled) or infinite (disabled)
1888 * - Ivybridge: 3 (enabled) or infinite (disabled)
1890 * Unfortunately, detecting this point in time is tricky, because
1891 * no version bump happened when this important change occurred.
1892 * On Haswell, if we can write any register, then the kernel is at
1893 * least this new, and we can start trusting the version number.
1895 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
1896 * Command parser reaches version 4, allowing access to Haswell
1897 * atomic scratch and chicken3 registers. If version >= 4, we know
1898 * the kernel is new enough to support privileged features on all
1899 * hardware. However, the user might have disabled it...and the
1900 * kernel will still report version 4. So we still have to guess
1903 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
1904 * Command parser v5 whitelists indirect compute shader dispatch
1905 * registers, needed for OpenGL 4.3 and later.
1908 * Command parser v7 lets us use MI_MATH on Haswell.
1910 * Additionally, the kernel begins reporting version 0 when
1911 * the command parser is disabled, allowing us to skip the
1912 * guess-and-check step on Haswell. Unfortunately, this also
1913 * means that we can no longer use it as an indicator of the
1914 * age of the kernel.
1916 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
1917 &screen
->cmd_parser_version
) < 0) {
1918 /* Command parser does not exist - getparam is unrecognized */
1919 screen
->cmd_parser_version
= 0;
1922 if (!intel_detect_pipelined_so(screen
)) {
1923 /* We can't do anything, so the effective version is 0. */
1924 screen
->cmd_parser_version
= 0;
1926 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
1929 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1931 screen
->winsys_msaa_samples_override
=
1932 intel_quantize_num_samples(screen
, atoi(force_msaa
));
1933 printf("Forcing winsys sample count to %d\n",
1934 screen
->winsys_msaa_samples_override
);
1936 screen
->winsys_msaa_samples_override
= -1;
1939 set_max_gl_versions(screen
);
1941 /* Notification of GPU resets requires hardware contexts and a kernel new
1942 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1943 * supported, calling it with a context of 0 will either generate EPERM or
1944 * no error. If the ioctl is not supported, it always generate EINVAL.
1945 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1946 * extension to the loader.
1948 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1950 if (devinfo
->gen
>= 6) {
1951 struct drm_i915_reset_stats stats
;
1952 memset(&stats
, 0, sizeof(stats
));
1954 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1956 screen
->has_context_reset_notification
=
1957 (ret
!= -1 || errno
!= EINVAL
);
1960 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
1961 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
1963 /* Haswell requires command parser version 4 in order to have L3
1964 * atomic scratch1 and chicken3 bits
1966 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
1967 screen
->kernel_features
|=
1968 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
1971 /* Haswell requires command parser version 6 in order to write to the
1972 * MI_MATH GPR registers, and version 7 in order to use
1973 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
1975 if (devinfo
->gen
>= 8 ||
1976 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
1977 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
1980 /* Gen7 needs at least command parser version 5 to support compute */
1981 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
1982 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
1984 dri_screen
->extensions
= !screen
->has_context_reset_notification
1985 ? screenExtensions
: intelRobustScreenExtensions
;
1987 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
1988 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
1989 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
1990 screen
->program_id
= 1;
1992 screen
->has_exec_fence
=
1993 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
1995 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
1998 struct intel_buffer
{
2003 static __DRIbuffer
*
2004 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2005 unsigned attachment
, unsigned format
,
2006 int width
, int height
)
2008 struct intel_buffer
*intelBuffer
;
2009 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2011 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2012 attachment
== __DRI_BUFFER_BACK_LEFT
);
2014 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2015 if (intelBuffer
== NULL
)
2018 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2019 * supports Y tiled and compressed buffers, but there is no way to plumb that
2020 * through to here. */
2021 uint32_t tiling
= I915_TILING_X
;
2022 unsigned long pitch
;
2023 int cpp
= format
/ 8;
2024 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(screen
->bufmgr
,
2025 "intelAllocateBuffer",
2030 BO_ALLOC_FOR_RENDER
);
2032 if (intelBuffer
->bo
== NULL
) {
2037 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2039 intelBuffer
->base
.attachment
= attachment
;
2040 intelBuffer
->base
.cpp
= cpp
;
2041 intelBuffer
->base
.pitch
= pitch
;
2043 return &intelBuffer
->base
;
2047 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2049 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2051 drm_intel_bo_unreference(intelBuffer
->bo
);
2055 static const struct __DriverAPIRec brw_driver_api
= {
2056 .InitScreen
= intelInitScreen2
,
2057 .DestroyScreen
= intelDestroyScreen
,
2058 .CreateContext
= brwCreateContext
,
2059 .DestroyContext
= intelDestroyContext
,
2060 .CreateBuffer
= intelCreateBuffer
,
2061 .DestroyBuffer
= intelDestroyBuffer
,
2062 .MakeCurrent
= intelMakeCurrent
,
2063 .UnbindContext
= intelUnbindContext
,
2064 .AllocateBuffer
= intelAllocateBuffer
,
2065 .ReleaseBuffer
= intelReleaseBuffer
2068 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2069 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2070 .vtable
= &brw_driver_api
,
2073 static const __DRIextension
*brw_driver_extensions
[] = {
2074 &driCoreExtension
.base
,
2075 &driImageDriverExtension
.base
,
2076 &driDRI2Extension
.base
,
2078 &brw_config_options
.base
,
2082 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2084 globalDriverAPI
= &brw_driver_api
;
2086 return brw_driver_extensions
;