2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm_fourcc.h>
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "util/disk_cache.h"
40 #include "brw_defines.h"
41 #include "brw_state.h"
42 #include "compiler/nir/nir.h"
45 #include "util/disk_cache.h"
46 #include "util/xmlpool.h"
48 #include "common/gen_defines.h"
50 static const __DRIconfigOptionsExtension brw_config_options
= {
51 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
54 DRI_CONF_SECTION_PERFORMANCE
55 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
56 * DRI_CONF_BO_REUSE_ALL
58 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
59 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
60 DRI_CONF_ENUM(0, "Disable buffer object reuse")
61 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
64 DRI_CONF_MESA_NO_ERROR("false")
67 DRI_CONF_SECTION_QUALITY
68 DRI_CONF_PRECISE_TRIG("false")
70 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
71 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
72 "given integer. If negative, then do not clamp.")
76 DRI_CONF_SECTION_DEBUG
77 DRI_CONF_NO_RAST("false")
78 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
79 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
80 DRI_CONF_DISABLE_THROTTLING("false")
81 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
82 DRI_CONF_FORCE_GLSL_VERSION(0)
83 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
84 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
85 DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
86 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
87 DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION("false")
88 DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH("false")
89 DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
90 DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
92 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
93 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
97 DRI_CONF_SECTION_MISCELLANEOUS
98 DRI_CONF_GLSL_ZERO_INIT("false")
99 DRI_CONF_ALLOW_RGB10_CONFIGS("false")
104 #include "intel_batchbuffer.h"
105 #include "intel_buffers.h"
106 #include "brw_bufmgr.h"
107 #include "intel_fbo.h"
108 #include "intel_mipmap_tree.h"
109 #include "intel_screen.h"
110 #include "intel_tex.h"
111 #include "intel_image.h"
113 #include "brw_context.h"
115 #include "i915_drm.h"
118 * For debugging purposes, this returns a time in seconds.
125 clock_gettime(CLOCK_MONOTONIC
, &tp
);
127 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
130 static const __DRItexBufferExtension intelTexBufferExtension
= {
131 .base
= { __DRI_TEX_BUFFER
, 3 },
133 .setTexBuffer
= intelSetTexBuffer
,
134 .setTexBuffer2
= intelSetTexBuffer2
,
135 .releaseTexBuffer
= intelReleaseTexBuffer
,
139 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
140 __DRIdrawable
*dPriv
,
142 enum __DRI2throttleReason reason
)
144 struct brw_context
*brw
= cPriv
->driverPrivate
;
149 struct gl_context
*ctx
= &brw
->ctx
;
151 FLUSH_VERTICES(ctx
, 0);
153 if (flags
& __DRI2_FLUSH_DRAWABLE
)
154 intel_resolve_for_dri2_flush(brw
, dPriv
);
156 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
157 brw
->need_swap_throttle
= true;
158 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
159 brw
->need_flush_throttle
= true;
161 intel_batchbuffer_flush(brw
);
165 * Provides compatibility with loaders that only support the older (version
166 * 1-3) flush interface.
168 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
171 intel_dri2_flush(__DRIdrawable
*drawable
)
173 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
174 __DRI2_FLUSH_DRAWABLE
,
175 __DRI2_THROTTLE_SWAPBUFFER
);
178 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
179 .base
= { __DRI2_FLUSH
, 4 },
181 .flush
= intel_dri2_flush
,
182 .invalidate
= dri2InvalidateDrawable
,
183 .flush_with_flags
= intel_dri2_flush_with_flags
,
186 static const struct intel_image_format intel_image_formats
[] = {
187 { __DRI_IMAGE_FOURCC_ARGB2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
188 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010
, 4 } } },
190 { __DRI_IMAGE_FOURCC_XRGB2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
191 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010
, 4 } } },
193 { __DRI_IMAGE_FOURCC_ABGR2101010
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
194 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR2101010
, 4 } } },
196 { __DRI_IMAGE_FOURCC_XBGR2101010
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
197 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR2101010
, 4 } } },
199 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
200 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
202 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
203 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
205 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
206 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
208 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
209 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
211 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
212 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
214 { __DRI_IMAGE_FOURCC_ARGB1555
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
215 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB1555
, 2 } } },
217 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
218 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
220 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
221 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
223 { __DRI_IMAGE_FOURCC_R16
, __DRI_IMAGE_COMPONENTS_R
, 1,
224 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16
, 1 }, } },
226 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
227 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
229 { __DRI_IMAGE_FOURCC_GR1616
, __DRI_IMAGE_COMPONENTS_RG
, 1,
230 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616
, 2 }, } },
232 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
233 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
234 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
235 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
237 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
238 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
240 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
242 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
243 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
245 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
247 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
248 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
250 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
252 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
253 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
255 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
257 { __DRI_IMAGE_FOURCC_YVU410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
258 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
260 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
262 { __DRI_IMAGE_FOURCC_YVU411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
263 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
264 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
265 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
267 { __DRI_IMAGE_FOURCC_YVU420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
268 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
269 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
270 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
272 { __DRI_IMAGE_FOURCC_YVU422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
273 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
274 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
275 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
277 { __DRI_IMAGE_FOURCC_YVU444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
279 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
280 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
282 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
283 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
284 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
286 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
287 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
288 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
290 /* For YUYV and UYVY buffers, we set up two overlapping DRI images
291 * and treat them as planar buffers in the compositors.
292 * Plane 0 is GR88 and samples YU or YV pairs and places Y into
293 * the R component, while plane 1 is ARGB/ABGR and samples YUYV/UYVY
294 * clusters and places pairs and places U into the G component and
295 * V into A. This lets the texture sampler interpolate the Y
296 * components correctly when sampling from plane 0, and interpolate
297 * U and V correctly when sampling from plane 1. */
298 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
299 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
300 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
301 { __DRI_IMAGE_FOURCC_UYVY
, __DRI_IMAGE_COMPONENTS_Y_UXVX
, 2,
302 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
303 { 0, 1, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } }
306 static const struct {
309 } supported_modifiers
[] = {
310 { .modifier
= DRM_FORMAT_MOD_LINEAR
, .since_gen
= 1 },
311 { .modifier
= I915_FORMAT_MOD_X_TILED
, .since_gen
= 1 },
312 { .modifier
= I915_FORMAT_MOD_Y_TILED
, .since_gen
= 6 },
313 { .modifier
= I915_FORMAT_MOD_Y_TILED_CCS
, .since_gen
= 9 },
317 modifier_is_supported(const struct gen_device_info
*devinfo
,
318 const struct intel_image_format
*fmt
, int dri_format
,
321 const struct isl_drm_modifier_info
*modinfo
=
322 isl_drm_modifier_get_info(modifier
);
325 /* ISL had better know about the modifier */
329 if (modinfo
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
330 /* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
331 if (unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
))
334 /* CCS_E is not supported for planar images */
335 if (fmt
&& fmt
->nplanes
> 1)
339 assert(dri_format
== 0);
340 dri_format
= fmt
->planes
[0].dri_format
;
343 mesa_format format
= driImageFormatToGLFormat(dri_format
);
344 /* Whether or not we support compression is based on the RGBA non-sRGB
345 * version of the format.
347 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
348 format
= _mesa_get_srgb_format_linear(format
);
349 if (!isl_format_supports_ccs_e(devinfo
,
350 brw_isl_format_for_mesa_format(format
)))
354 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
355 if (supported_modifiers
[i
].modifier
!= modifier
)
358 return supported_modifiers
[i
].since_gen
<= devinfo
->gen
;
365 tiling_to_modifier(uint32_t tiling
)
367 static const uint64_t map
[] = {
368 [I915_TILING_NONE
] = DRM_FORMAT_MOD_LINEAR
,
369 [I915_TILING_X
] = I915_FORMAT_MOD_X_TILED
,
370 [I915_TILING_Y
] = I915_FORMAT_MOD_Y_TILED
,
373 assert(tiling
< ARRAY_SIZE(map
));
379 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
381 uint32_t tiling
, swizzle
;
382 brw_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
384 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
385 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
386 func
, image
->offset
);
390 static const struct intel_image_format
*
391 intel_image_format_lookup(int fourcc
)
393 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
394 if (intel_image_formats
[i
].fourcc
== fourcc
)
395 return &intel_image_formats
[i
];
402 intel_image_get_fourcc(__DRIimage
*image
, int *fourcc
)
404 if (image
->planar_format
) {
405 *fourcc
= image
->planar_format
->fourcc
;
409 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
410 if (intel_image_formats
[i
].planes
[0].dri_format
== image
->dri_format
) {
411 *fourcc
= intel_image_formats
[i
].fourcc
;
419 intel_allocate_image(struct intel_screen
*screen
, int dri_format
,
424 image
= calloc(1, sizeof *image
);
428 image
->screen
= screen
;
429 image
->dri_format
= dri_format
;
432 image
->format
= driImageFormatToGLFormat(dri_format
);
433 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
434 image
->format
== MESA_FORMAT_NONE
) {
439 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
440 image
->data
= loaderPrivate
;
446 * Sets up a DRIImage structure to point to a slice out of a miptree.
449 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
450 struct intel_mipmap_tree
*mt
, GLuint level
,
453 intel_miptree_make_shareable(brw
, mt
);
455 intel_miptree_check_level_layer(mt
, level
, zoffset
);
457 image
->width
= minify(mt
->surf
.phys_level0_sa
.width
,
458 level
- mt
->first_level
);
459 image
->height
= minify(mt
->surf
.phys_level0_sa
.height
,
460 level
- mt
->first_level
);
461 image
->pitch
= mt
->surf
.row_pitch
;
463 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
467 brw_bo_unreference(image
->bo
);
469 brw_bo_reference(mt
->bo
);
473 intel_create_image_from_name(__DRIscreen
*dri_screen
,
474 int width
, int height
, int format
,
475 int name
, int pitch
, void *loaderPrivate
)
477 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
481 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
485 if (image
->format
== MESA_FORMAT_NONE
)
488 cpp
= _mesa_get_format_bytes(image
->format
);
490 image
->width
= width
;
491 image
->height
= height
;
492 image
->pitch
= pitch
* cpp
;
493 image
->bo
= brw_bo_gem_create_from_name(screen
->bufmgr
, "image",
499 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
505 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
506 int renderbuffer
, void *loaderPrivate
)
509 struct brw_context
*brw
= context
->driverPrivate
;
510 struct gl_context
*ctx
= &brw
->ctx
;
511 struct gl_renderbuffer
*rb
;
512 struct intel_renderbuffer
*irb
;
514 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
516 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
520 irb
= intel_renderbuffer(rb
);
521 intel_miptree_make_shareable(brw
, irb
->mt
);
522 image
= calloc(1, sizeof *image
);
526 image
->internal_format
= rb
->InternalFormat
;
527 image
->format
= rb
->Format
;
528 image
->modifier
= tiling_to_modifier(
529 isl_tiling_to_i915_tiling(irb
->mt
->surf
.tiling
));
531 image
->data
= loaderPrivate
;
532 brw_bo_unreference(image
->bo
);
533 image
->bo
= irb
->mt
->bo
;
534 brw_bo_reference(irb
->mt
->bo
);
535 image
->width
= rb
->Width
;
536 image
->height
= rb
->Height
;
537 image
->pitch
= irb
->mt
->surf
.row_pitch
;
538 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
539 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
541 rb
->NeedsFinishRenderTexture
= true;
546 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
547 unsigned texture
, int zoffset
,
553 struct brw_context
*brw
= context
->driverPrivate
;
554 struct gl_texture_object
*obj
;
555 struct intel_texture_object
*iobj
;
558 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
559 if (!obj
|| obj
->Target
!= target
) {
560 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
564 if (target
== GL_TEXTURE_CUBE_MAP
)
567 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
568 iobj
= intel_texture_object(obj
);
569 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
570 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
574 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
575 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
579 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
580 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
583 image
= calloc(1, sizeof *image
);
585 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
589 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
590 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
591 image
->modifier
= tiling_to_modifier(
592 isl_tiling_to_i915_tiling(iobj
->mt
->surf
.tiling
));
593 image
->data
= loaderPrivate
;
594 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
595 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
596 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
597 image
->planar_format
= iobj
->planar_format
;
598 if (image
->dri_format
== __DRI_IMAGE_FORMAT_NONE
) {
599 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
604 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
609 intel_destroy_image(__DRIimage
*image
)
611 brw_bo_unreference(image
->bo
);
615 enum modifier_priority
{
616 MODIFIER_PRIORITY_INVALID
= 0,
617 MODIFIER_PRIORITY_LINEAR
,
620 MODIFIER_PRIORITY_Y_CCS
,
623 const uint64_t priority_to_modifier
[] = {
624 [MODIFIER_PRIORITY_INVALID
] = DRM_FORMAT_MOD_INVALID
,
625 [MODIFIER_PRIORITY_LINEAR
] = DRM_FORMAT_MOD_LINEAR
,
626 [MODIFIER_PRIORITY_X
] = I915_FORMAT_MOD_X_TILED
,
627 [MODIFIER_PRIORITY_Y
] = I915_FORMAT_MOD_Y_TILED
,
628 [MODIFIER_PRIORITY_Y_CCS
] = I915_FORMAT_MOD_Y_TILED_CCS
,
632 select_best_modifier(struct gen_device_info
*devinfo
,
634 const uint64_t *modifiers
,
635 const unsigned count
)
637 enum modifier_priority prio
= MODIFIER_PRIORITY_INVALID
;
639 for (int i
= 0; i
< count
; i
++) {
640 if (!modifier_is_supported(devinfo
, NULL
, dri_format
, modifiers
[i
]))
643 switch (modifiers
[i
]) {
644 case I915_FORMAT_MOD_Y_TILED_CCS
:
645 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y_CCS
);
647 case I915_FORMAT_MOD_Y_TILED
:
648 prio
= MAX2(prio
, MODIFIER_PRIORITY_Y
);
650 case I915_FORMAT_MOD_X_TILED
:
651 prio
= MAX2(prio
, MODIFIER_PRIORITY_X
);
653 case DRM_FORMAT_MOD_LINEAR
:
654 prio
= MAX2(prio
, MODIFIER_PRIORITY_LINEAR
);
656 case DRM_FORMAT_MOD_INVALID
:
662 return priority_to_modifier
[prio
];
666 intel_create_image_common(__DRIscreen
*dri_screen
,
667 int width
, int height
, int format
,
669 const uint64_t *modifiers
,
674 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
675 uint64_t modifier
= DRM_FORMAT_MOD_INVALID
;
678 /* Callers of this may specify a modifier, or a dri usage, but not both. The
679 * newer modifier interface deprecates the older usage flags newer modifier
680 * interface deprecates the older usage flags.
682 assert(!(use
&& count
));
684 if (use
& __DRI_IMAGE_USE_CURSOR
) {
685 if (width
!= 64 || height
!= 64)
687 modifier
= DRM_FORMAT_MOD_LINEAR
;
690 if (use
& __DRI_IMAGE_USE_LINEAR
)
691 modifier
= DRM_FORMAT_MOD_LINEAR
;
693 if (modifier
== DRM_FORMAT_MOD_INVALID
) {
695 /* User requested specific modifiers */
696 modifier
= select_best_modifier(&screen
->devinfo
, format
,
698 if (modifier
== DRM_FORMAT_MOD_INVALID
)
701 /* Historically, X-tiled was the default, and so lack of modifier means
704 modifier
= I915_FORMAT_MOD_X_TILED
;
708 image
= intel_allocate_image(screen
, format
, loaderPrivate
);
712 const struct isl_drm_modifier_info
*mod_info
=
713 isl_drm_modifier_get_info(modifier
);
715 struct isl_surf surf
;
716 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
717 .dim
= ISL_SURF_DIM_2D
,
718 .format
= brw_isl_format_for_mesa_format(image
->format
),
725 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
726 ISL_SURF_USAGE_TEXTURE_BIT
|
727 ISL_SURF_USAGE_STORAGE_BIT
,
728 .tiling_flags
= (1 << mod_info
->tiling
));
735 struct isl_surf aux_surf
;
736 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
737 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
, 0);
743 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
747 /* We request that the bufmgr zero the buffer for us for two reasons:
749 * 1) If a buffer gets re-used from the pool, we don't want to leak random
750 * garbage from our process to some other.
752 * 2) For images with CCS_E, we want to ensure that the CCS starts off in
753 * a valid state. A CCS value of 0 indicates that the given block is
754 * in the pass-through state which is what we want.
756 image
->bo
= brw_bo_alloc_tiled(screen
->bufmgr
, "image",
757 surf
.size
+ aux_surf
.size
,
759 isl_tiling_to_i915_tiling(mod_info
->tiling
),
760 surf
.row_pitch
, BO_ALLOC_ZEROED
);
761 if (image
->bo
== NULL
) {
765 image
->width
= width
;
766 image
->height
= height
;
767 image
->pitch
= surf
.row_pitch
;
768 image
->modifier
= modifier
;
771 image
->aux_offset
= surf
.size
;
772 image
->aux_pitch
= aux_surf
.row_pitch
;
773 image
->aux_size
= aux_surf
.size
;
780 intel_create_image(__DRIscreen
*dri_screen
,
781 int width
, int height
, int format
,
785 return intel_create_image_common(dri_screen
, width
, height
, format
, use
, NULL
, 0,
790 intel_map_image(__DRIcontext
*context
, __DRIimage
*image
,
791 int x0
, int y0
, int width
, int height
,
792 unsigned int flags
, int *stride
, void **map_info
)
794 struct brw_context
*brw
= NULL
;
795 struct brw_bo
*bo
= NULL
;
796 void *raw_data
= NULL
;
801 if (!context
|| !image
|| !stride
|| !map_info
|| *map_info
)
804 if (x0
< 0 || x0
>= image
->width
|| width
> image
->width
- x0
)
807 if (y0
< 0 || y0
>= image
->height
|| height
> image
->height
- y0
)
810 if (flags
& MAP_INTERNAL_MASK
)
813 brw
= context
->driverPrivate
;
819 /* DRI flags and GL_MAP.*_BIT flags are the same, so just pass them on. */
820 raw_data
= brw_bo_map(brw
, bo
, flags
);
824 _mesa_get_format_block_size(image
->format
, &pix_w
, &pix_h
);
825 pix_bytes
= _mesa_get_format_bytes(image
->format
);
829 assert(pix_bytes
> 0);
831 raw_data
+= (x0
/ pix_w
) * pix_bytes
+ (y0
/ pix_h
) * image
->pitch
;
833 brw_bo_reference(bo
);
835 *stride
= image
->pitch
;
842 intel_unmap_image(__DRIcontext
*context
, __DRIimage
*image
, void *map_info
)
844 struct brw_bo
*bo
= map_info
;
847 brw_bo_unreference(bo
);
851 intel_create_image_with_modifiers(__DRIscreen
*dri_screen
,
852 int width
, int height
, int format
,
853 const uint64_t *modifiers
,
854 const unsigned count
,
857 return intel_create_image_common(dri_screen
, width
, height
, format
, 0,
858 modifiers
, count
, loaderPrivate
);
862 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
865 case __DRI_IMAGE_ATTRIB_STRIDE
:
866 *value
= image
->pitch
;
868 case __DRI_IMAGE_ATTRIB_HANDLE
:
869 *value
= brw_bo_export_gem_handle(image
->bo
);
871 case __DRI_IMAGE_ATTRIB_NAME
:
872 return !brw_bo_flink(image
->bo
, (uint32_t *) value
);
873 case __DRI_IMAGE_ATTRIB_FORMAT
:
874 *value
= image
->dri_format
;
876 case __DRI_IMAGE_ATTRIB_WIDTH
:
877 *value
= image
->width
;
879 case __DRI_IMAGE_ATTRIB_HEIGHT
:
880 *value
= image
->height
;
882 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
883 if (image
->planar_format
== NULL
)
885 *value
= image
->planar_format
->components
;
887 case __DRI_IMAGE_ATTRIB_FD
:
888 return !brw_bo_gem_export_to_prime(image
->bo
, value
);
889 case __DRI_IMAGE_ATTRIB_FOURCC
:
890 return intel_image_get_fourcc(image
, value
);
891 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
892 if (isl_drm_modifier_has_aux(image
->modifier
)) {
893 assert(!image
->planar_format
|| image
->planar_format
->nplanes
== 1);
895 } else if (image
->planar_format
) {
896 *value
= image
->planar_format
->nplanes
;
901 case __DRI_IMAGE_ATTRIB_OFFSET
:
902 *value
= image
->offset
;
904 case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER
:
905 *value
= (image
->modifier
& 0xffffffff);
907 case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
:
908 *value
= ((image
->modifier
>> 32) & 0xffffffff);
917 intel_query_format_modifier_attribs(__DRIscreen
*dri_screen
,
918 uint32_t fourcc
, uint64_t modifier
,
919 int attrib
, uint64_t *value
)
921 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
922 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
924 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
928 case __DRI_IMAGE_FORMAT_MODIFIER_ATTRIB_PLANE_COUNT
:
929 *value
= isl_drm_modifier_has_aux(modifier
) ? 2 : f
->nplanes
;
938 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
942 image
= calloc(1, sizeof *image
);
946 brw_bo_reference(orig_image
->bo
);
947 image
->bo
= orig_image
->bo
;
948 image
->internal_format
= orig_image
->internal_format
;
949 image
->planar_format
= orig_image
->planar_format
;
950 image
->dri_format
= orig_image
->dri_format
;
951 image
->format
= orig_image
->format
;
952 image
->modifier
= orig_image
->modifier
;
953 image
->offset
= orig_image
->offset
;
954 image
->width
= orig_image
->width
;
955 image
->height
= orig_image
->height
;
956 image
->pitch
= orig_image
->pitch
;
957 image
->tile_x
= orig_image
->tile_x
;
958 image
->tile_y
= orig_image
->tile_y
;
959 image
->has_depthstencil
= orig_image
->has_depthstencil
;
960 image
->data
= loaderPrivate
;
961 image
->dma_buf_imported
= orig_image
->dma_buf_imported
;
962 image
->aux_offset
= orig_image
->aux_offset
;
963 image
->aux_pitch
= orig_image
->aux_pitch
;
965 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
966 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
972 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
974 if (use
& __DRI_IMAGE_USE_CURSOR
) {
975 if (image
->width
!= 64 || image
->height
!= 64)
983 intel_create_image_from_names(__DRIscreen
*dri_screen
,
984 int width
, int height
, int fourcc
,
985 int *names
, int num_names
,
986 int *strides
, int *offsets
,
989 const struct intel_image_format
*f
= NULL
;
993 if (dri_screen
== NULL
|| names
== NULL
|| num_names
!= 1)
996 f
= intel_image_format_lookup(fourcc
);
1000 image
= intel_create_image_from_name(dri_screen
, width
, height
,
1001 __DRI_IMAGE_FORMAT_NONE
,
1002 names
[0], strides
[0],
1008 image
->planar_format
= f
;
1009 for (i
= 0; i
< f
->nplanes
; i
++) {
1010 index
= f
->planes
[i
].buffer_index
;
1011 image
->offsets
[index
] = offsets
[index
];
1012 image
->strides
[index
] = strides
[index
];
1019 intel_create_image_from_fds_common(__DRIscreen
*dri_screen
,
1020 int width
, int height
, int fourcc
,
1021 uint64_t modifier
, int *fds
, int num_fds
,
1022 int *strides
, int *offsets
,
1023 void *loaderPrivate
)
1025 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1026 const struct intel_image_format
*f
;
1031 if (fds
== NULL
|| num_fds
< 1)
1034 f
= intel_image_format_lookup(fourcc
);
1038 if (modifier
!= DRM_FORMAT_MOD_INVALID
&&
1039 !modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1042 if (f
->nplanes
== 1)
1043 image
= intel_allocate_image(screen
, f
->planes
[0].dri_format
,
1046 image
= intel_allocate_image(screen
, __DRI_IMAGE_FORMAT_NONE
,
1052 image
->width
= width
;
1053 image
->height
= height
;
1054 image
->pitch
= strides
[0];
1056 image
->planar_format
= f
;
1058 if (modifier
!= DRM_FORMAT_MOD_INVALID
) {
1059 const struct isl_drm_modifier_info
*mod_info
=
1060 isl_drm_modifier_get_info(modifier
);
1061 uint32_t tiling
= isl_tiling_to_i915_tiling(mod_info
->tiling
);
1062 image
->bo
= brw_bo_gem_create_from_prime_tiled(screen
->bufmgr
, fds
[0],
1063 tiling
, strides
[0]);
1065 image
->bo
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[0]);
1068 if (image
->bo
== NULL
) {
1073 /* We only support all planes from the same bo.
1074 * brw_bo_gem_create_from_prime() should return the same pointer for all
1075 * fds received here */
1076 for (i
= 1; i
< num_fds
; i
++) {
1077 struct brw_bo
*aux
= brw_bo_gem_create_from_prime(screen
->bufmgr
, fds
[i
]);
1078 brw_bo_unreference(aux
);
1079 if (aux
!= image
->bo
) {
1080 brw_bo_unreference(image
->bo
);
1086 if (modifier
!= DRM_FORMAT_MOD_INVALID
)
1087 image
->modifier
= modifier
;
1089 image
->modifier
= tiling_to_modifier(image
->bo
->tiling_mode
);
1091 const struct isl_drm_modifier_info
*mod_info
=
1092 isl_drm_modifier_get_info(image
->modifier
);
1095 struct isl_surf surf
;
1096 for (i
= 0; i
< f
->nplanes
; i
++) {
1097 index
= f
->planes
[i
].buffer_index
;
1098 image
->offsets
[index
] = offsets
[index
];
1099 image
->strides
[index
] = strides
[index
];
1101 mesa_format format
= driImageFormatToGLFormat(f
->planes
[i
].dri_format
);
1102 /* The images we will create are actually based on the RGBA non-sRGB
1103 * version of the format.
1105 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1106 format
= _mesa_get_srgb_format_linear(format
);
1108 ok
= isl_surf_init(&screen
->isl_dev
, &surf
,
1109 .dim
= ISL_SURF_DIM_2D
,
1110 .format
= brw_isl_format_for_mesa_format(format
),
1111 .width
= image
->width
>> f
->planes
[i
].width_shift
,
1112 .height
= image
->height
>> f
->planes
[i
].height_shift
,
1117 .row_pitch
= strides
[index
],
1118 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1119 ISL_SURF_USAGE_TEXTURE_BIT
|
1120 ISL_SURF_USAGE_STORAGE_BIT
,
1121 .tiling_flags
= (1 << mod_info
->tiling
));
1123 brw_bo_unreference(image
->bo
);
1128 const int end
= offsets
[index
] + surf
.size
;
1133 if (mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1134 /* Even though we initialize surf in the loop above, we know that
1135 * anything with CCS_E will have exactly one plane so surf is properly
1136 * initialized when we get here.
1138 assert(f
->nplanes
== 1);
1140 image
->aux_offset
= offsets
[1];
1141 image
->aux_pitch
= strides
[1];
1143 /* Scanout hardware requires that the CCS be placed after the main
1144 * surface in memory. We consider any CCS that is placed any earlier in
1145 * memory to be invalid and reject it.
1147 * At some point in the future, this restriction may be relaxed if the
1148 * hardware becomes less strict but we may need a new modifier for that.
1151 if (image
->aux_offset
< size
) {
1152 brw_bo_unreference(image
->bo
);
1157 struct isl_surf aux_surf
;
1158 ok
= isl_surf_get_ccs_surf(&screen
->isl_dev
, &surf
, &aux_surf
,
1161 brw_bo_unreference(image
->bo
);
1166 image
->aux_size
= aux_surf
.size
;
1168 const int end
= image
->aux_offset
+ aux_surf
.size
;
1172 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
);
1175 /* Check that the requested image actually fits within the BO. 'size'
1176 * is already relative to the offsets, so we don't need to add that. */
1177 if (image
->bo
->size
== 0) {
1178 image
->bo
->size
= size
;
1179 } else if (size
> image
->bo
->size
) {
1180 brw_bo_unreference(image
->bo
);
1185 if (f
->nplanes
== 1) {
1186 image
->offset
= image
->offsets
[0];
1187 intel_image_warn_if_unaligned(image
, __func__
);
1194 intel_create_image_from_fds(__DRIscreen
*dri_screen
,
1195 int width
, int height
, int fourcc
,
1196 int *fds
, int num_fds
, int *strides
, int *offsets
,
1197 void *loaderPrivate
)
1199 return intel_create_image_from_fds_common(dri_screen
, width
, height
, fourcc
,
1200 DRM_FORMAT_MOD_INVALID
,
1201 fds
, num_fds
, strides
, offsets
,
1206 intel_create_image_from_dma_bufs2(__DRIscreen
*dri_screen
,
1207 int width
, int height
,
1208 int fourcc
, uint64_t modifier
,
1209 int *fds
, int num_fds
,
1210 int *strides
, int *offsets
,
1211 enum __DRIYUVColorSpace yuv_color_space
,
1212 enum __DRISampleRange sample_range
,
1213 enum __DRIChromaSiting horizontal_siting
,
1214 enum __DRIChromaSiting vertical_siting
,
1216 void *loaderPrivate
)
1219 const struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
1222 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
1226 image
= intel_create_image_from_fds_common(dri_screen
, width
, height
,
1228 fds
, num_fds
, strides
, offsets
,
1232 * Invalid parameters and any inconsistencies between are assumed to be
1233 * checked by the caller. Therefore besides unsupported formats one can fail
1234 * only in allocation.
1237 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
1241 image
->dma_buf_imported
= true;
1242 image
->yuv_color_space
= yuv_color_space
;
1243 image
->sample_range
= sample_range
;
1244 image
->horizontal_siting
= horizontal_siting
;
1245 image
->vertical_siting
= vertical_siting
;
1247 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
1252 intel_create_image_from_dma_bufs(__DRIscreen
*dri_screen
,
1253 int width
, int height
, int fourcc
,
1254 int *fds
, int num_fds
,
1255 int *strides
, int *offsets
,
1256 enum __DRIYUVColorSpace yuv_color_space
,
1257 enum __DRISampleRange sample_range
,
1258 enum __DRIChromaSiting horizontal_siting
,
1259 enum __DRIChromaSiting vertical_siting
,
1261 void *loaderPrivate
)
1263 return intel_create_image_from_dma_bufs2(dri_screen
, width
, height
,
1264 fourcc
, DRM_FORMAT_MOD_INVALID
,
1265 fds
, num_fds
, strides
, offsets
,
1275 intel_image_format_is_supported(const struct intel_image_format
*fmt
)
1277 if (fmt
->fourcc
== __DRI_IMAGE_FOURCC_SARGB8888
||
1278 fmt
->fourcc
== __DRI_IMAGE_FOURCC_SABGR8888
)
1285 intel_query_dma_buf_formats(__DRIscreen
*screen
, int max
,
1286 int *formats
, int *count
)
1288 int num_formats
= 0, i
;
1290 for (i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
1291 if (!intel_image_format_is_supported(&intel_image_formats
[i
]))
1298 formats
[num_formats
- 1] = intel_image_formats
[i
].fourcc
;
1299 if (num_formats
>= max
)
1303 *count
= num_formats
;
1308 intel_query_dma_buf_modifiers(__DRIscreen
*_screen
, int fourcc
, int max
,
1309 uint64_t *modifiers
,
1310 unsigned int *external_only
,
1313 struct intel_screen
*screen
= _screen
->driverPrivate
;
1314 const struct intel_image_format
*f
;
1315 int num_mods
= 0, i
;
1317 f
= intel_image_format_lookup(fourcc
);
1321 if (!intel_image_format_is_supported(f
))
1324 for (i
= 0; i
< ARRAY_SIZE(supported_modifiers
); i
++) {
1325 uint64_t modifier
= supported_modifiers
[i
].modifier
;
1326 if (!modifier_is_supported(&screen
->devinfo
, f
, 0, modifier
))
1333 modifiers
[num_mods
- 1] = modifier
;
1334 if (num_mods
>= max
)
1338 if (external_only
!= NULL
) {
1339 for (i
= 0; i
< num_mods
&& i
< max
; i
++) {
1340 if (f
->components
== __DRI_IMAGE_COMPONENTS_Y_U_V
||
1341 f
->components
== __DRI_IMAGE_COMPONENTS_Y_UV
||
1342 f
->components
== __DRI_IMAGE_COMPONENTS_Y_XUXV
) {
1343 external_only
[i
] = GL_TRUE
;
1346 external_only
[i
] = GL_FALSE
;
1356 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
1358 int width
, height
, offset
, stride
, size
, dri_format
;
1364 width
= parent
->width
;
1365 height
= parent
->height
;
1367 const struct intel_image_format
*f
= parent
->planar_format
;
1369 if (f
&& plane
< f
->nplanes
) {
1370 /* Use the planar format definition. */
1371 width
>>= f
->planes
[plane
].width_shift
;
1372 height
>>= f
->planes
[plane
].height_shift
;
1373 dri_format
= f
->planes
[plane
].dri_format
;
1374 int index
= f
->planes
[plane
].buffer_index
;
1375 offset
= parent
->offsets
[index
];
1376 stride
= parent
->strides
[index
];
1377 size
= height
* stride
;
1378 } else if (plane
== 0) {
1379 /* The only plane of a non-planar image: copy the parent definition
1381 dri_format
= parent
->dri_format
;
1382 offset
= parent
->offset
;
1383 stride
= parent
->pitch
;
1384 size
= height
* stride
;
1385 } else if (plane
== 1 && parent
->modifier
!= DRM_FORMAT_MOD_INVALID
&&
1386 isl_drm_modifier_has_aux(parent
->modifier
)) {
1387 /* Auxiliary plane */
1388 dri_format
= parent
->dri_format
;
1389 offset
= parent
->aux_offset
;
1390 stride
= parent
->aux_pitch
;
1391 size
= parent
->aux_size
;
1396 if (offset
+ size
> parent
->bo
->size
) {
1397 _mesa_warning(NULL
, "intel_from_planar: subimage out of bounds");
1401 image
= intel_allocate_image(parent
->screen
, dri_format
, loaderPrivate
);
1405 image
->bo
= parent
->bo
;
1406 brw_bo_reference(parent
->bo
);
1407 image
->modifier
= parent
->modifier
;
1409 image
->width
= width
;
1410 image
->height
= height
;
1411 image
->pitch
= stride
;
1412 image
->offset
= offset
;
1414 intel_image_warn_if_unaligned(image
, __func__
);
1419 static const __DRIimageExtension intelImageExtension
= {
1420 .base
= { __DRI_IMAGE
, 16 },
1422 .createImageFromName
= intel_create_image_from_name
,
1423 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
1424 .destroyImage
= intel_destroy_image
,
1425 .createImage
= intel_create_image
,
1426 .queryImage
= intel_query_image
,
1427 .dupImage
= intel_dup_image
,
1428 .validateUsage
= intel_validate_usage
,
1429 .createImageFromNames
= intel_create_image_from_names
,
1430 .fromPlanar
= intel_from_planar
,
1431 .createImageFromTexture
= intel_create_image_from_texture
,
1432 .createImageFromFds
= intel_create_image_from_fds
,
1433 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
1435 .getCapabilities
= NULL
,
1436 .mapImage
= intel_map_image
,
1437 .unmapImage
= intel_unmap_image
,
1438 .createImageWithModifiers
= intel_create_image_with_modifiers
,
1439 .createImageFromDmaBufs2
= intel_create_image_from_dma_bufs2
,
1440 .queryDmaBufFormats
= intel_query_dma_buf_formats
,
1441 .queryDmaBufModifiers
= intel_query_dma_buf_modifiers
,
1442 .queryDmaBufFormatModifierAttribs
= intel_query_format_modifier_attribs
,
1446 get_aperture_size(int fd
)
1448 struct drm_i915_gem_get_aperture aperture
;
1450 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_GET_APERTURE
, &aperture
) != 0)
1453 return aperture
.aper_size
;
1457 brw_query_renderer_integer(__DRIscreen
*dri_screen
,
1458 int param
, unsigned int *value
)
1460 const struct intel_screen
*const screen
=
1461 (struct intel_screen
*) dri_screen
->driverPrivate
;
1464 case __DRI2_RENDERER_VENDOR_ID
:
1467 case __DRI2_RENDERER_DEVICE_ID
:
1468 value
[0] = screen
->deviceID
;
1470 case __DRI2_RENDERER_ACCELERATED
:
1473 case __DRI2_RENDERER_VIDEO_MEMORY
: {
1474 /* Once a batch uses more than 75% of the maximum mappable size, we
1475 * assume that there's some fragmentation, and we start doing extra
1476 * flushing, etc. That's the big cliff apps will care about.
1478 const unsigned gpu_mappable_megabytes
=
1479 screen
->aperture_threshold
/ (1024 * 1024);
1481 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
1482 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
1484 if (system_memory_pages
<= 0 || system_page_size
<= 0)
1487 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
1488 * (uint64_t) system_page_size
;
1490 const unsigned system_memory_megabytes
=
1491 (unsigned) (system_memory_bytes
/ (1024 * 1024));
1493 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
1496 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
1499 case __DRI2_RENDERER_HAS_TEXTURE_3D
:
1502 case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY
:
1504 if (brw_hw_context_set_priority(screen
->bufmgr
,
1505 0, GEN_CONTEXT_HIGH_PRIORITY
) == 0)
1506 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH
;
1507 if (brw_hw_context_set_priority(screen
->bufmgr
,
1508 0, GEN_CONTEXT_LOW_PRIORITY
) == 0)
1509 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW
;
1510 /* reset to default last, just in case */
1511 if (brw_hw_context_set_priority(screen
->bufmgr
,
1512 0, GEN_CONTEXT_MEDIUM_PRIORITY
) == 0)
1513 value
[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM
;
1515 case __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB
:
1519 return driQueryRendererIntegerCommon(dri_screen
, param
, value
);
1526 brw_query_renderer_string(__DRIscreen
*dri_screen
,
1527 int param
, const char **value
)
1529 const struct intel_screen
*screen
=
1530 (struct intel_screen
*) dri_screen
->driverPrivate
;
1533 case __DRI2_RENDERER_VENDOR_ID
:
1534 value
[0] = brw_vendor_string
;
1536 case __DRI2_RENDERER_DEVICE_ID
:
1537 value
[0] = brw_get_renderer_string(screen
);
1547 brw_set_cache_funcs(__DRIscreen
*dri_screen
,
1548 __DRIblobCacheSet set
, __DRIblobCacheGet get
)
1550 const struct intel_screen
*const screen
=
1551 (struct intel_screen
*) dri_screen
->driverPrivate
;
1553 if (!screen
->disk_cache
)
1556 disk_cache_set_callbacks(screen
->disk_cache
, set
, get
);
1559 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
1560 .base
= { __DRI2_RENDERER_QUERY
, 1 },
1562 .queryInteger
= brw_query_renderer_integer
,
1563 .queryString
= brw_query_renderer_string
1566 static const __DRIrobustnessExtension dri2Robustness
= {
1567 .base
= { __DRI2_ROBUSTNESS
, 1 }
1570 static const __DRI2blobExtension intelBlobExtension
= {
1571 .base
= { __DRI2_BLOB
, 1 },
1572 .set_cache_funcs
= brw_set_cache_funcs
1575 static const __DRIextension
*screenExtensions
[] = {
1576 &intelTexBufferExtension
.base
,
1577 &intelFenceExtension
.base
,
1578 &intelFlushExtension
.base
,
1579 &intelImageExtension
.base
,
1580 &intelRendererQueryExtension
.base
,
1581 &dri2ConfigQueryExtension
.base
,
1582 &dri2NoErrorExtension
.base
,
1583 &intelBlobExtension
.base
,
1587 static const __DRIextension
*intelRobustScreenExtensions
[] = {
1588 &intelTexBufferExtension
.base
,
1589 &intelFenceExtension
.base
,
1590 &intelFlushExtension
.base
,
1591 &intelImageExtension
.base
,
1592 &intelRendererQueryExtension
.base
,
1593 &dri2ConfigQueryExtension
.base
,
1594 &dri2Robustness
.base
,
1595 &dri2NoErrorExtension
.base
,
1596 &intelBlobExtension
.base
,
1601 intel_get_param(struct intel_screen
*screen
, int param
, int *value
)
1604 struct drm_i915_getparam gp
;
1606 memset(&gp
, 0, sizeof(gp
));
1610 if (drmIoctl(screen
->driScrnPriv
->fd
, DRM_IOCTL_I915_GETPARAM
, &gp
) == -1) {
1613 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
1620 intel_get_boolean(struct intel_screen
*screen
, int param
)
1623 return (intel_get_param(screen
, param
, &value
) == 0) && value
;
1627 intel_get_integer(struct intel_screen
*screen
, int param
)
1631 if (intel_get_param(screen
, param
, &value
) == 0)
1638 intelDestroyScreen(__DRIscreen
* sPriv
)
1640 struct intel_screen
*screen
= sPriv
->driverPrivate
;
1642 brw_bufmgr_destroy(screen
->bufmgr
);
1643 driDestroyOptionInfo(&screen
->optionCache
);
1645 disk_cache_destroy(screen
->disk_cache
);
1647 ralloc_free(screen
);
1648 sPriv
->driverPrivate
= NULL
;
1653 * Create a gl_framebuffer and attach it to __DRIdrawable::driverPrivate.
1655 *_This implements driDriverAPI::createNewDrawable, which the DRI layer calls
1656 * when creating a EGLSurface, GLXDrawable, or GLXPixmap. Despite the name,
1657 * this does not allocate GPU memory.
1660 intelCreateBuffer(__DRIscreen
*dri_screen
,
1661 __DRIdrawable
* driDrawPriv
,
1662 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
1664 struct intel_renderbuffer
*rb
;
1665 struct intel_screen
*screen
= (struct intel_screen
*)
1666 dri_screen
->driverPrivate
;
1667 mesa_format rgbFormat
;
1668 unsigned num_samples
=
1669 intel_quantize_num_samples(screen
, mesaVis
->samples
);
1674 struct gl_framebuffer
*fb
= CALLOC_STRUCT(gl_framebuffer
);
1678 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
1680 if (screen
->winsys_msaa_samples_override
!= -1) {
1681 num_samples
= screen
->winsys_msaa_samples_override
;
1682 fb
->Visual
.samples
= num_samples
;
1685 if (mesaVis
->redBits
== 10 && mesaVis
->alphaBits
> 0) {
1686 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10A2_UNORM
1687 : MESA_FORMAT_R10G10B10A2_UNORM
;
1688 } else if (mesaVis
->redBits
== 10) {
1689 rgbFormat
= mesaVis
->redMask
== 0x3ff00000 ? MESA_FORMAT_B10G10R10X2_UNORM
1690 : MESA_FORMAT_R10G10B10X2_UNORM
;
1691 } else if (mesaVis
->redBits
== 5) {
1692 rgbFormat
= mesaVis
->redMask
== 0x1f ? MESA_FORMAT_R5G6B5_UNORM
1693 : MESA_FORMAT_B5G6R5_UNORM
;
1694 } else if (mesaVis
->sRGBCapable
) {
1695 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1696 : MESA_FORMAT_B8G8R8A8_SRGB
;
1697 } else if (mesaVis
->alphaBits
== 0) {
1698 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8X8_UNORM
1699 : MESA_FORMAT_B8G8R8X8_UNORM
;
1701 rgbFormat
= mesaVis
->redMask
== 0xff ? MESA_FORMAT_R8G8B8A8_SRGB
1702 : MESA_FORMAT_B8G8R8A8_SRGB
;
1703 fb
->Visual
.sRGBCapable
= true;
1706 /* mesaVis->sRGBCapable was set, user is asking for sRGB */
1707 bool srgb_cap_set
= mesaVis
->redBits
>= 8 && mesaVis
->sRGBCapable
;
1709 /* setup the hardware-based renderbuffers */
1710 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1711 _mesa_attach_and_own_rb(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1712 rb
->need_srgb
= srgb_cap_set
;
1714 if (mesaVis
->doubleBufferMode
) {
1715 rb
= intel_create_winsys_renderbuffer(screen
, rgbFormat
, num_samples
);
1716 _mesa_attach_and_own_rb(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1717 rb
->need_srgb
= srgb_cap_set
;
1721 * Assert here that the gl_config has an expected depth/stencil bit
1722 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1723 * which constructs the advertised configs.)
1725 if (mesaVis
->depthBits
== 24) {
1726 assert(mesaVis
->stencilBits
== 8);
1728 if (screen
->devinfo
.has_hiz_and_separate_stencil
) {
1729 rb
= intel_create_private_renderbuffer(screen
,
1730 MESA_FORMAT_Z24_UNORM_X8_UINT
,
1732 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1733 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_S_UINT8
,
1735 _mesa_attach_and_own_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1738 * Use combined depth/stencil. Note that the renderbuffer is
1739 * attached to two attachment points.
1741 rb
= intel_create_private_renderbuffer(screen
,
1742 MESA_FORMAT_Z24_UNORM_S8_UINT
,
1744 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1745 _mesa_attach_and_reference_rb(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1748 else if (mesaVis
->depthBits
== 16) {
1749 assert(mesaVis
->stencilBits
== 0);
1750 rb
= intel_create_private_renderbuffer(screen
, MESA_FORMAT_Z_UNORM16
,
1752 _mesa_attach_and_own_rb(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1755 assert(mesaVis
->depthBits
== 0);
1756 assert(mesaVis
->stencilBits
== 0);
1759 /* now add any/all software-based renderbuffers we may need */
1760 _swrast_add_soft_renderbuffers(fb
,
1761 false, /* never sw color */
1762 false, /* never sw depth */
1763 false, /* never sw stencil */
1764 mesaVis
->accumRedBits
> 0,
1765 false, /* never sw alpha */
1766 false /* never sw aux */ );
1767 driDrawPriv
->driverPrivate
= fb
;
1773 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1775 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1777 _mesa_reference_framebuffer(&fb
, NULL
);
1781 intel_cs_timestamp_frequency(struct intel_screen
*screen
)
1783 /* We shouldn't need to update gen_device_info.timestamp_frequency prior to
1784 * gen10, PCI-id is enough to figure it out.
1786 assert(screen
->devinfo
.gen
>= 10);
1790 ret
= intel_get_param(screen
, I915_PARAM_CS_TIMESTAMP_FREQUENCY
,
1794 "Kernel 4.15 required to read the CS timestamp frequency.\n");
1798 screen
->devinfo
.timestamp_frequency
= freq
;
1802 intel_detect_sseu(struct intel_screen
*screen
)
1804 assert(screen
->devinfo
.gen
>= 8);
1807 screen
->subslice_total
= -1;
1808 screen
->eu_total
= -1;
1810 ret
= intel_get_param(screen
, I915_PARAM_SUBSLICE_TOTAL
,
1811 &screen
->subslice_total
);
1812 if (ret
< 0 && ret
!= -EINVAL
)
1815 ret
= intel_get_param(screen
,
1816 I915_PARAM_EU_TOTAL
, &screen
->eu_total
);
1817 if (ret
< 0 && ret
!= -EINVAL
)
1820 /* Without this information, we cannot get the right Braswell brandstrings,
1821 * and we have to use conservative numbers for GPGPU on many platforms, but
1822 * otherwise, things will just work.
1824 if (screen
->subslice_total
< 1 || screen
->eu_total
< 1)
1826 "Kernel 4.1 required to properly query GPU properties.\n");
1831 screen
->subslice_total
= -1;
1832 screen
->eu_total
= -1;
1833 _mesa_warning(NULL
, "Failed to query GPU properties (%s).\n", strerror(-ret
));
1837 intel_init_bufmgr(struct intel_screen
*screen
)
1839 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
1841 if (getenv("INTEL_NO_HW") != NULL
)
1842 screen
->no_hw
= true;
1844 screen
->bufmgr
= brw_bufmgr_init(&screen
->devinfo
, dri_screen
->fd
);
1845 if (screen
->bufmgr
== NULL
) {
1846 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1847 __func__
, __LINE__
);
1851 if (!intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_NO_RELOC
)) {
1852 fprintf(stderr
, "[%s: %u] Kernel 3.9 required.\n", __func__
, __LINE__
);
1860 intel_detect_swizzling(struct intel_screen
*screen
)
1862 uint32_t tiling
= I915_TILING_X
;
1863 uint32_t swizzle_mode
= 0;
1864 struct brw_bo
*buffer
=
1865 brw_bo_alloc_tiled(screen
->bufmgr
, "swizzle test", 32768,
1866 BRW_MEMZONE_OTHER
, tiling
, 512, 0);
1870 brw_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1871 brw_bo_unreference(buffer
);
1873 return swizzle_mode
!= I915_BIT_6_SWIZZLE_NONE
;
1877 intel_detect_timestamp(struct intel_screen
*screen
)
1879 uint64_t dummy
= 0, last
= 0;
1880 int upper
, lower
, loops
;
1882 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1883 * TIMESTAMP register being shifted and the low 32bits always zero.
1885 * More recent kernels offer an interface to read the full 36bits
1888 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1891 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1892 * upper 32bits for a rapidly changing timestamp.
1894 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1898 for (loops
= 0; loops
< 10; loops
++) {
1899 /* The TIMESTAMP should change every 80ns, so several round trips
1900 * through the kernel should be enough to advance it.
1902 if (brw_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1905 upper
+= (dummy
>> 32) != (last
>> 32);
1906 if (upper
> 1) /* beware 32bit counter overflow */
1907 return 2; /* upper dword holds the low 32bits of the timestamp */
1909 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1911 return 1; /* timestamp is unshifted */
1916 /* No advancement? No timestamp! */
1921 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
1923 * Some combinations of hardware and kernel versions allow this feature,
1924 * while others don't. Instead of trying to enumerate every case, just
1925 * try and write a register and see if works.
1928 intel_detect_pipelined_register(struct intel_screen
*screen
,
1929 int reg
, uint32_t expected_value
, bool reset
)
1934 struct brw_bo
*results
, *bo
;
1936 uint32_t offset
= 0;
1938 bool success
= false;
1940 /* Create a zero'ed temporary buffer for reading our results */
1941 results
= brw_bo_alloc(screen
->bufmgr
, "registers", 4096, BRW_MEMZONE_OTHER
);
1942 if (results
== NULL
)
1945 bo
= brw_bo_alloc(screen
->bufmgr
, "batchbuffer", 4096, BRW_MEMZONE_OTHER
);
1949 map
= brw_bo_map(NULL
, bo
, MAP_WRITE
);
1955 /* Write the register. */
1956 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1958 *batch
++ = expected_value
;
1960 /* Save the register's value back to the buffer. */
1961 *batch
++ = MI_STORE_REGISTER_MEM
| (3 - 2);
1963 struct drm_i915_gem_relocation_entry reloc
= {
1964 .offset
= (char *) batch
- (char *) map
,
1965 .delta
= offset
* sizeof(uint32_t),
1966 .target_handle
= results
->gem_handle
,
1967 .read_domains
= I915_GEM_DOMAIN_INSTRUCTION
,
1968 .write_domain
= I915_GEM_DOMAIN_INSTRUCTION
,
1970 *batch
++ = reloc
.presumed_offset
+ reloc
.delta
;
1972 /* And afterwards clear the register */
1974 *batch
++ = MI_LOAD_REGISTER_IMM
| (3 - 2);
1979 *batch
++ = MI_BATCH_BUFFER_END
;
1981 struct drm_i915_gem_exec_object2 exec_objects
[2] = {
1983 .handle
= results
->gem_handle
,
1986 .handle
= bo
->gem_handle
,
1987 .relocation_count
= 1,
1988 .relocs_ptr
= (uintptr_t) &reloc
,
1992 struct drm_i915_gem_execbuffer2 execbuf
= {
1993 .buffers_ptr
= (uintptr_t) exec_objects
,
1995 .batch_len
= ALIGN((char *) batch
- (char *) map
, 8),
1996 .flags
= I915_EXEC_RENDER
,
1999 /* Don't bother with error checking - if the execbuf fails, the
2000 * value won't be written and we'll just report that there's no access.
2002 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2003 drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GEM_EXECBUFFER2
, &execbuf
);
2005 /* Check whether the value got written. */
2006 void *results_map
= brw_bo_map(NULL
, results
, MAP_READ
);
2008 success
= *((uint32_t *)results_map
+ offset
) == expected_value
;
2009 brw_bo_unmap(results
);
2013 brw_bo_unreference(bo
);
2015 brw_bo_unreference(results
);
2021 intel_detect_pipelined_so(struct intel_screen
*screen
)
2023 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2025 /* Supposedly, Broadwell just works. */
2026 if (devinfo
->gen
>= 8)
2029 if (devinfo
->gen
<= 6)
2032 /* See the big explanation about command parser versions below */
2033 if (screen
->cmd_parser_version
>= (devinfo
->is_haswell
? 7 : 2))
2036 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
2037 * statistics registers), and we already reset it to zero before using it.
2039 return intel_detect_pipelined_register(screen
,
2040 GEN7_SO_WRITE_OFFSET(0),
2046 * Return array of MSAA modes supported by the hardware. The array is
2047 * zero-terminated and sorted in decreasing order.
2050 intel_supported_msaa_modes(const struct intel_screen
*screen
)
2052 static const int gen9_modes
[] = {16, 8, 4, 2, 0, -1};
2053 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
2054 static const int gen7_modes
[] = {8, 4, 0, -1};
2055 static const int gen6_modes
[] = {4, 0, -1};
2056 static const int gen4_modes
[] = {0, -1};
2058 if (screen
->devinfo
.gen
>= 9) {
2060 } else if (screen
->devinfo
.gen
>= 8) {
2062 } else if (screen
->devinfo
.gen
>= 7) {
2064 } else if (screen
->devinfo
.gen
== 6) {
2072 intel_loader_get_cap(const __DRIscreen
*dri_screen
, enum dri_loader_cap cap
)
2074 if (dri_screen
->dri2
.loader
&& dri_screen
->dri2
.loader
->base
.version
>= 4 &&
2075 dri_screen
->dri2
.loader
->getCapability
)
2076 return dri_screen
->dri2
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2078 if (dri_screen
->image
.loader
&& dri_screen
->image
.loader
->base
.version
>= 2 &&
2079 dri_screen
->image
.loader
->getCapability
)
2080 return dri_screen
->image
.loader
->getCapability(dri_screen
->loaderPrivate
, cap
);
2085 static __DRIconfig
**
2086 intel_screen_make_configs(__DRIscreen
*dri_screen
)
2088 static const mesa_format formats
[] = {
2089 MESA_FORMAT_B5G6R5_UNORM
,
2090 MESA_FORMAT_B8G8R8A8_UNORM
,
2091 MESA_FORMAT_B8G8R8X8_UNORM
,
2093 MESA_FORMAT_B8G8R8A8_SRGB
,
2095 /* For 10 bpc, 30 bit depth framebuffers. */
2096 MESA_FORMAT_B10G10R10A2_UNORM
,
2097 MESA_FORMAT_B10G10R10X2_UNORM
,
2099 /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
2100 * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX
2101 * server may disagree on which format the GLXFBConfig represents,
2102 * resulting in swapped color channels.
2104 * The problem, as of 2017-05-30:
2105 * When matching a GLXFBConfig to a __DRIconfig, GLX ignores the channel
2106 * order and chooses the first __DRIconfig with the expected channel
2107 * sizes. Specifically, GLX compares the GLXFBConfig's and __DRIconfig's
2108 * __DRI_ATTRIB_{CHANNEL}_SIZE but ignores __DRI_ATTRIB_{CHANNEL}_MASK.
2110 * EGL does not suffer from this problem. It correctly compares the
2111 * channel masks when matching EGLConfig to __DRIconfig.
2114 /* Required by Android, for HAL_PIXEL_FORMAT_RGBA_8888. */
2115 MESA_FORMAT_R8G8B8A8_UNORM
,
2117 /* Required by Android, for HAL_PIXEL_FORMAT_RGBX_8888. */
2118 MESA_FORMAT_R8G8B8X8_UNORM
,
2120 MESA_FORMAT_R8G8B8A8_SRGB
,
2123 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
2124 static const GLenum back_buffer_modes
[] = {
2125 __DRI_ATTRIB_SWAP_UNDEFINED
, __DRI_ATTRIB_SWAP_NONE
2128 static const uint8_t singlesample_samples
[1] = {0};
2130 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2131 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2132 uint8_t depth_bits
[4], stencil_bits
[4];
2133 __DRIconfig
**configs
= NULL
;
2135 /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */
2136 unsigned num_formats
;
2137 if (intel_loader_get_cap(dri_screen
, DRI_LOADER_CAP_RGBA_ORDERING
))
2138 num_formats
= ARRAY_SIZE(formats
);
2140 num_formats
= ARRAY_SIZE(formats
) - 3; /* all - RGBA_ORDERING formats */
2142 /* Shall we expose 10 bpc formats? */
2143 bool allow_rgb10_configs
= driQueryOptionb(&screen
->optionCache
,
2144 "allow_rgb10_configs");
2146 /* Generate singlesample configs without accumulation buffer. */
2147 for (unsigned i
= 0; i
< num_formats
; i
++) {
2148 __DRIconfig
**new_configs
;
2149 int num_depth_stencil_bits
= 2;
2151 if (!allow_rgb10_configs
&&
2152 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2153 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2156 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
2157 * buffer that has a different number of bits per pixel than the color
2158 * buffer, gen >= 6 supports this.
2161 stencil_bits
[0] = 0;
2163 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2165 stencil_bits
[1] = 0;
2166 if (devinfo
->gen
>= 6) {
2168 stencil_bits
[2] = 8;
2169 num_depth_stencil_bits
= 3;
2173 stencil_bits
[1] = 8;
2176 new_configs
= driCreateConfigs(formats
[i
],
2179 num_depth_stencil_bits
,
2180 back_buffer_modes
, 2,
2181 singlesample_samples
, 1,
2183 configs
= driConcatConfigs(configs
, new_configs
);
2186 /* Generate the minimum possible set of configs that include an
2187 * accumulation buffer.
2189 for (unsigned i
= 0; i
< num_formats
; i
++) {
2190 __DRIconfig
**new_configs
;
2192 if (!allow_rgb10_configs
&&
2193 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2194 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2197 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2199 stencil_bits
[0] = 0;
2202 stencil_bits
[0] = 8;
2205 new_configs
= driCreateConfigs(formats
[i
],
2206 depth_bits
, stencil_bits
, 1,
2207 back_buffer_modes
, 1,
2208 singlesample_samples
, 1,
2210 configs
= driConcatConfigs(configs
, new_configs
);
2213 /* Generate multisample configs.
2215 * This loop breaks early, and hence is a no-op, on gen < 6.
2217 * Multisample configs must follow the singlesample configs in order to
2218 * work around an X server bug present in 1.12. The X server chooses to
2219 * associate the first listed RGBA888-Z24S8 config, regardless of its
2220 * sample count, with the 32-bit depth visual used for compositing.
2222 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
2223 * supported. Singlebuffer configs are not supported because no one wants
2226 for (unsigned i
= 0; i
< num_formats
; i
++) {
2227 if (devinfo
->gen
< 6)
2230 if (!allow_rgb10_configs
&&
2231 (formats
[i
] == MESA_FORMAT_B10G10R10A2_UNORM
||
2232 formats
[i
] == MESA_FORMAT_B10G10R10X2_UNORM
))
2235 __DRIconfig
**new_configs
;
2236 const int num_depth_stencil_bits
= 2;
2237 int num_msaa_modes
= 0;
2238 const uint8_t *multisample_samples
= NULL
;
2241 stencil_bits
[0] = 0;
2243 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
2245 stencil_bits
[1] = 0;
2248 stencil_bits
[1] = 8;
2251 if (devinfo
->gen
>= 9) {
2252 static const uint8_t multisample_samples_gen9
[] = {2, 4, 8, 16};
2253 multisample_samples
= multisample_samples_gen9
;
2254 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen9
);
2255 } else if (devinfo
->gen
== 8) {
2256 static const uint8_t multisample_samples_gen8
[] = {2, 4, 8};
2257 multisample_samples
= multisample_samples_gen8
;
2258 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen8
);
2259 } else if (devinfo
->gen
== 7) {
2260 static const uint8_t multisample_samples_gen7
[] = {4, 8};
2261 multisample_samples
= multisample_samples_gen7
;
2262 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen7
);
2263 } else if (devinfo
->gen
== 6) {
2264 static const uint8_t multisample_samples_gen6
[] = {4};
2265 multisample_samples
= multisample_samples_gen6
;
2266 num_msaa_modes
= ARRAY_SIZE(multisample_samples_gen6
);
2269 new_configs
= driCreateConfigs(formats
[i
],
2272 num_depth_stencil_bits
,
2273 back_buffer_modes
, 1,
2274 multisample_samples
,
2277 configs
= driConcatConfigs(configs
, new_configs
);
2280 if (configs
== NULL
) {
2281 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
2290 set_max_gl_versions(struct intel_screen
*screen
)
2292 __DRIscreen
*dri_screen
= screen
->driScrnPriv
;
2293 const bool has_astc
= screen
->devinfo
.gen
>= 9;
2295 switch (screen
->devinfo
.gen
) {
2300 dri_screen
->max_gl_core_version
= 45;
2301 dri_screen
->max_gl_compat_version
= 30;
2302 dri_screen
->max_gl_es1_version
= 11;
2303 dri_screen
->max_gl_es2_version
= has_astc
? 32 : 31;
2306 dri_screen
->max_gl_core_version
= 33;
2307 if (can_do_pipelined_register_writes(screen
)) {
2308 dri_screen
->max_gl_core_version
= 42;
2309 if (screen
->devinfo
.is_haswell
&& can_do_compute_dispatch(screen
))
2310 dri_screen
->max_gl_core_version
= 43;
2311 if (screen
->devinfo
.is_haswell
&& can_do_mi_math_and_lrr(screen
))
2312 dri_screen
->max_gl_core_version
= 45;
2314 dri_screen
->max_gl_compat_version
= 30;
2315 dri_screen
->max_gl_es1_version
= 11;
2316 dri_screen
->max_gl_es2_version
= screen
->devinfo
.is_haswell
? 31 : 30;
2319 dri_screen
->max_gl_core_version
= 33;
2320 dri_screen
->max_gl_compat_version
= 30;
2321 dri_screen
->max_gl_es1_version
= 11;
2322 dri_screen
->max_gl_es2_version
= 30;
2326 dri_screen
->max_gl_core_version
= 0;
2327 dri_screen
->max_gl_compat_version
= 21;
2328 dri_screen
->max_gl_es1_version
= 11;
2329 dri_screen
->max_gl_es2_version
= 20;
2332 unreachable("unrecognized intel_screen::gen");
2337 * Return the revision (generally the revid field of the PCI header) of the
2341 intel_device_get_revision(int fd
)
2343 struct drm_i915_getparam gp
;
2347 memset(&gp
, 0, sizeof(gp
));
2348 gp
.param
= I915_PARAM_REVISION
;
2349 gp
.value
= &revision
;
2351 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
2359 shader_debug_log_mesa(void *data
, const char *fmt
, ...)
2361 struct brw_context
*brw
= (struct brw_context
*)data
;
2364 va_start(args
, fmt
);
2366 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2367 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2368 MESA_DEBUG_TYPE_OTHER
,
2369 MESA_DEBUG_SEVERITY_NOTIFICATION
, fmt
, args
);
2374 shader_perf_log_mesa(void *data
, const char *fmt
, ...)
2376 struct brw_context
*brw
= (struct brw_context
*)data
;
2379 va_start(args
, fmt
);
2381 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
2383 va_copy(args_copy
, args
);
2384 vfprintf(stderr
, fmt
, args_copy
);
2388 if (brw
->perf_debug
) {
2390 _mesa_gl_vdebug(&brw
->ctx
, &msg_id
,
2391 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2392 MESA_DEBUG_TYPE_PERFORMANCE
,
2393 MESA_DEBUG_SEVERITY_MEDIUM
, fmt
, args
);
2399 * This is the driver specific part of the createNewScreen entry point.
2400 * Called when using DRI2.
2402 * \return the struct gl_config supported by this driver
2405 __DRIconfig
**intelInitScreen2(__DRIscreen
*dri_screen
)
2407 struct intel_screen
*screen
;
2409 if (dri_screen
->image
.loader
) {
2410 } else if (dri_screen
->dri2
.loader
->base
.version
<= 2 ||
2411 dri_screen
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
2413 "\nERROR! DRI2 loader with getBuffersWithFormat() "
2414 "support required\n");
2418 /* Allocate the private area */
2419 screen
= rzalloc(NULL
, struct intel_screen
);
2421 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
2424 /* parse information in __driConfigOptions */
2425 driOptionCache options
;
2426 memset(&options
, 0, sizeof(options
));
2428 driParseOptionInfo(&options
, brw_config_options
.xml
);
2429 driParseConfigFiles(&screen
->optionCache
, &options
, dri_screen
->myNum
, "i965");
2430 driDestroyOptionCache(&options
);
2432 screen
->driScrnPriv
= dri_screen
;
2433 dri_screen
->driverPrivate
= (void *) screen
;
2435 screen
->deviceID
= gen_get_pci_device_id_override();
2436 if (screen
->deviceID
< 0)
2437 screen
->deviceID
= intel_get_integer(screen
, I915_PARAM_CHIPSET_ID
);
2439 screen
->no_hw
= true;
2441 if (!gen_get_device_info(screen
->deviceID
, &screen
->devinfo
))
2444 if (!intel_init_bufmgr(screen
))
2447 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
2449 brw_process_intel_debug_variable();
2451 if ((INTEL_DEBUG
& DEBUG_SHADER_TIME
) && devinfo
->gen
< 7) {
2453 "shader_time debugging requires gen7 (Ivybridge) or better.\n");
2454 INTEL_DEBUG
&= ~DEBUG_SHADER_TIME
;
2457 if (intel_get_integer(screen
, I915_PARAM_MMAP_GTT_VERSION
) >= 1) {
2458 /* Theorectically unlimited! At least for individual objects...
2460 * Currently the entire (global) address space for all GTT maps is
2461 * limited to 64bits. That is all objects on the system that are
2462 * setup for GTT mmapping must fit within 64bits. An attempt to use
2463 * one that exceeds the limit with fail in brw_bo_map_gtt().
2465 * Long before we hit that limit, we will be practically limited by
2466 * that any single object must fit in physical memory (RAM). The upper
2467 * limit on the CPU's address space is currently 48bits (Skylake), of
2468 * which only 39bits can be physical memory. (The GPU itself also has
2469 * a 48bit addressable virtual space.) We can fit over 32 million
2470 * objects of the current maximum allocable size before running out
2473 screen
->max_gtt_map_object_size
= UINT64_MAX
;
2475 /* Estimate the size of the mappable aperture into the GTT. There's an
2476 * ioctl to get the whole GTT size, but not one to get the mappable subset.
2477 * It turns out it's basically always 256MB, though some ancient hardware
2480 uint32_t gtt_size
= 256 * 1024 * 1024;
2482 /* We don't want to map two objects such that a memcpy between them would
2483 * just fault one mapping in and then the other over and over forever. So
2484 * we would need to divide the GTT size by 2. Additionally, some GTT is
2485 * taken up by things like the framebuffer and the ringbuffer and such, so
2486 * be more conservative.
2488 screen
->max_gtt_map_object_size
= gtt_size
/ 4;
2491 screen
->aperture_threshold
= get_aperture_size(dri_screen
->fd
) * 3 / 4;
2493 screen
->hw_has_swizzling
= intel_detect_swizzling(screen
);
2494 screen
->hw_has_timestamp
= intel_detect_timestamp(screen
);
2496 isl_device_init(&screen
->isl_dev
, &screen
->devinfo
,
2497 screen
->hw_has_swizzling
);
2499 if (devinfo
->gen
>= 10)
2500 intel_cs_timestamp_frequency(screen
);
2502 /* GENs prior to 8 do not support EU/Subslice info */
2503 if (devinfo
->gen
>= 8) {
2504 intel_detect_sseu(screen
);
2505 } else if (devinfo
->gen
== 7) {
2506 screen
->subslice_total
= 1 << (devinfo
->gt
- 1);
2509 /* Gen7-7.5 kernel requirements / command parser saga:
2512 * Haswell and Baytrail cannot use any privileged batchbuffer features.
2514 * Ivybridge has aliasing PPGTT on by default, which accidentally marks
2515 * all batches secure, allowing them to use any feature with no checking.
2516 * This is effectively equivalent to a command parser version of
2517 * \infinity - everything is possible.
2519 * The command parser does not exist, and querying the version will
2523 * The kernel enables the command parser by default, for systems with
2524 * aliasing PPGTT enabled (Ivybridge and Haswell). However, the
2525 * hardware checker is still enabled, so Haswell and Baytrail cannot
2528 * Ivybridge goes from "everything is possible" to "only what the
2529 * command parser allows" (if the user boots with i915.cmd_parser=0,
2530 * then everything is possible again). We can only safely use features
2531 * allowed by the supported command parser version.
2533 * Annoyingly, I915_PARAM_CMD_PARSER_VERSION reports the static version
2534 * implemented by the kernel, even if it's turned off. So, checking
2535 * for version > 0 does not mean that you can write registers. We have
2536 * to try it and see. The version does, however, indicate the age of
2539 * Instead of matching the hardware checker's behavior of converting
2540 * privileged commands to MI_NOOP, it makes execbuf2 start returning
2541 * -EINVAL, making it dangerous to try and use privileged features.
2543 * Effective command parser versions:
2544 * - Haswell: 0 (reporting 1, writes don't work)
2545 * - Baytrail: 0 (reporting 1, writes don't work)
2546 * - Ivybridge: 1 (enabled) or infinite (disabled)
2549 * Baytrail aliasing PPGTT is enabled, making it like Ivybridge:
2550 * effectively version 1 (enabled) or infinite (disabled).
2552 * - v3.19: f1f55cc0556031c8ee3fe99dae7251e78b9b653b
2553 * Command parser v2 supports predicate writes.
2555 * - Haswell: 0 (reporting 1, writes don't work)
2556 * - Baytrail: 2 (enabled) or infinite (disabled)
2557 * - Ivybridge: 2 (enabled) or infinite (disabled)
2559 * So version >= 2 is enough to know that Ivybridge and Baytrail
2560 * will work. Haswell still can't do anything.
2562 * - v4.0: Version 3 happened. Largely not relevant.
2564 * - v4.1: 6702cf16e0ba8b0129f5aa1b6609d4e9c70bc13b
2565 * L3 config registers are properly saved and restored as part
2566 * of the hardware context. We can approximately detect this point
2567 * in time by checking if I915_PARAM_REVISION is recognized - it
2568 * landed in a later commit, but in the same release cycle.
2570 * - v4.2: 245054a1fe33c06ad233e0d58a27ec7b64db9284
2571 * Command parser finally gains secure batch promotion. On Haswell,
2572 * the hardware checker gets disabled, which finally allows it to do
2573 * privileged commands.
2575 * I915_PARAM_CMD_PARSER_VERSION reports 3. Effective versions:
2576 * - Haswell: 3 (enabled) or 0 (disabled)
2577 * - Baytrail: 3 (enabled) or infinite (disabled)
2578 * - Ivybridge: 3 (enabled) or infinite (disabled)
2580 * Unfortunately, detecting this point in time is tricky, because
2581 * no version bump happened when this important change occurred.
2582 * On Haswell, if we can write any register, then the kernel is at
2583 * least this new, and we can start trusting the version number.
2585 * - v4.4: 2bbe6bbb0dc94fd4ce287bdac9e1bd184e23057b and
2586 * Command parser reaches version 4, allowing access to Haswell
2587 * atomic scratch and chicken3 registers. If version >= 4, we know
2588 * the kernel is new enough to support privileged features on all
2589 * hardware. However, the user might have disabled it...and the
2590 * kernel will still report version 4. So we still have to guess
2593 * - v4.4: 7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8
2594 * Command parser v5 whitelists indirect compute shader dispatch
2595 * registers, needed for OpenGL 4.3 and later.
2598 * Command parser v7 lets us use MI_MATH on Haswell.
2600 * Additionally, the kernel begins reporting version 0 when
2601 * the command parser is disabled, allowing us to skip the
2602 * guess-and-check step on Haswell. Unfortunately, this also
2603 * means that we can no longer use it as an indicator of the
2604 * age of the kernel.
2606 if (intel_get_param(screen
, I915_PARAM_CMD_PARSER_VERSION
,
2607 &screen
->cmd_parser_version
) < 0) {
2608 /* Command parser does not exist - getparam is unrecognized */
2609 screen
->cmd_parser_version
= 0;
2612 /* Kernel 4.13 retuired for exec object capture */
2613 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_CAPTURE
)) {
2614 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_CAPTURE
;
2617 if (intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_BATCH_FIRST
)) {
2618 screen
->kernel_features
|= KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
2621 if (!intel_detect_pipelined_so(screen
)) {
2622 /* We can't do anything, so the effective version is 0. */
2623 screen
->cmd_parser_version
= 0;
2625 screen
->kernel_features
|= KERNEL_ALLOWS_SOL_OFFSET_WRITES
;
2628 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 2)
2629 screen
->kernel_features
|= KERNEL_ALLOWS_PREDICATE_WRITES
;
2631 /* Haswell requires command parser version 4 in order to have L3
2632 * atomic scratch1 and chicken3 bits
2634 if (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 4) {
2635 screen
->kernel_features
|=
2636 KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3
;
2639 /* Haswell requires command parser version 6 in order to write to the
2640 * MI_MATH GPR registers, and version 7 in order to use
2641 * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
2643 if (devinfo
->gen
>= 8 ||
2644 (devinfo
->is_haswell
&& screen
->cmd_parser_version
>= 7)) {
2645 screen
->kernel_features
|= KERNEL_ALLOWS_MI_MATH_AND_LRR
;
2648 /* Gen7 needs at least command parser version 5 to support compute */
2649 if (devinfo
->gen
>= 8 || screen
->cmd_parser_version
>= 5)
2650 screen
->kernel_features
|= KERNEL_ALLOWS_COMPUTE_DISPATCH
;
2652 if (intel_get_boolean(screen
, I915_PARAM_HAS_CONTEXT_ISOLATION
))
2653 screen
->kernel_features
|= KERNEL_ALLOWS_CONTEXT_ISOLATION
;
2655 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
2657 screen
->winsys_msaa_samples_override
=
2658 intel_quantize_num_samples(screen
, atoi(force_msaa
));
2659 printf("Forcing winsys sample count to %d\n",
2660 screen
->winsys_msaa_samples_override
);
2662 screen
->winsys_msaa_samples_override
= -1;
2665 set_max_gl_versions(screen
);
2667 /* Notification of GPU resets requires hardware contexts and a kernel new
2668 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
2669 * supported, calling it with a context of 0 will either generate EPERM or
2670 * no error. If the ioctl is not supported, it always generate EINVAL.
2671 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
2672 * extension to the loader.
2674 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
2676 if (devinfo
->gen
>= 6) {
2677 struct drm_i915_reset_stats stats
;
2678 memset(&stats
, 0, sizeof(stats
));
2680 const int ret
= drmIoctl(dri_screen
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
2682 screen
->has_context_reset_notification
=
2683 (ret
!= -1 || errno
!= EINVAL
);
2686 dri_screen
->extensions
= !screen
->has_context_reset_notification
2687 ? screenExtensions
: intelRobustScreenExtensions
;
2689 screen
->compiler
= brw_compiler_create(screen
, devinfo
);
2690 screen
->compiler
->shader_debug_log
= shader_debug_log_mesa
;
2691 screen
->compiler
->shader_perf_log
= shader_perf_log_mesa
;
2693 /* Changing the meaning of constant buffer pointers from a dynamic state
2694 * offset to an absolute address is only safe if the kernel isolates other
2695 * contexts from our changes.
2697 screen
->compiler
->constant_buffer_0_is_relative
= devinfo
->gen
< 8 ||
2698 !(screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
);
2700 screen
->compiler
->supports_pull_constants
= true;
2702 screen
->has_exec_fence
=
2703 intel_get_boolean(screen
, I915_PARAM_HAS_EXEC_FENCE
);
2705 intel_screen_init_surface_formats(screen
);
2707 if (INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
)) {
2708 unsigned int caps
= intel_get_integer(screen
, I915_PARAM_HAS_SCHEDULER
);
2710 fprintf(stderr
, "Kernel scheduler detected: %08x\n", caps
);
2711 if (caps
& I915_SCHEDULER_CAP_PRIORITY
)
2712 fprintf(stderr
, " - User priority sorting enabled\n");
2713 if (caps
& I915_SCHEDULER_CAP_PREEMPTION
)
2714 fprintf(stderr
, " - Preemption enabled\n");
2718 brw_disk_cache_init(screen
);
2720 return (const __DRIconfig
**) intel_screen_make_configs(dri_screen
);
2723 struct intel_buffer
{
2728 static __DRIbuffer
*
2729 intelAllocateBuffer(__DRIscreen
*dri_screen
,
2730 unsigned attachment
, unsigned format
,
2731 int width
, int height
)
2733 struct intel_buffer
*intelBuffer
;
2734 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
2736 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
2737 attachment
== __DRI_BUFFER_BACK_LEFT
);
2739 intelBuffer
= calloc(1, sizeof *intelBuffer
);
2740 if (intelBuffer
== NULL
)
2743 /* The front and back buffers are color buffers, which are X tiled. GEN9+
2744 * supports Y tiled and compressed buffers, but there is no way to plumb that
2745 * through to here. */
2747 int cpp
= format
/ 8;
2748 intelBuffer
->bo
= brw_bo_alloc_tiled_2d(screen
->bufmgr
,
2749 "intelAllocateBuffer",
2754 I915_TILING_X
, &pitch
,
2757 if (intelBuffer
->bo
== NULL
) {
2762 brw_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
2764 intelBuffer
->base
.attachment
= attachment
;
2765 intelBuffer
->base
.cpp
= cpp
;
2766 intelBuffer
->base
.pitch
= pitch
;
2768 return &intelBuffer
->base
;
2772 intelReleaseBuffer(__DRIscreen
*dri_screen
, __DRIbuffer
*buffer
)
2774 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
2776 brw_bo_unreference(intelBuffer
->bo
);
2780 static const struct __DriverAPIRec brw_driver_api
= {
2781 .InitScreen
= intelInitScreen2
,
2782 .DestroyScreen
= intelDestroyScreen
,
2783 .CreateContext
= brwCreateContext
,
2784 .DestroyContext
= intelDestroyContext
,
2785 .CreateBuffer
= intelCreateBuffer
,
2786 .DestroyBuffer
= intelDestroyBuffer
,
2787 .MakeCurrent
= intelMakeCurrent
,
2788 .UnbindContext
= intelUnbindContext
,
2789 .AllocateBuffer
= intelAllocateBuffer
,
2790 .ReleaseBuffer
= intelReleaseBuffer
2793 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
2794 .base
= { __DRI_DRIVER_VTABLE
, 1 },
2795 .vtable
= &brw_driver_api
,
2798 static const __DRIextension
*brw_driver_extensions
[] = {
2799 &driCoreExtension
.base
,
2800 &driImageDriverExtension
.base
,
2801 &driDRI2Extension
.base
,
2803 &brw_config_options
.base
,
2807 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
2809 globalDriverAPI
= &brw_driver_api
;
2811 return brw_driver_extensions
;