2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "main/glheader.h"
30 #include "main/context.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/texobj.h"
34 #include "main/hash.h"
35 #include "main/fbobject.h"
36 #include "main/version.h"
37 #include "swrast/s_renderbuffer.h"
38 #include "util/ralloc.h"
39 #include "brw_shader.h"
40 #include "glsl/nir/nir.h"
45 static const __DRIconfigOptionsExtension brw_config_options
= {
46 .base
= { __DRI_CONFIG_OPTIONS
, 1 },
49 DRI_CONF_SECTION_PERFORMANCE
50 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC
)
51 /* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
52 * DRI_CONF_BO_REUSE_ALL
54 DRI_CONF_OPT_BEGIN_V(bo_reuse
, enum, 1, "0:1")
55 DRI_CONF_DESC_BEGIN(en
, "Buffer object reuse")
56 DRI_CONF_ENUM(0, "Disable buffer object reuse")
57 DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
61 DRI_CONF_OPT_BEGIN_B(hiz
, "true")
62 DRI_CONF_DESC(en
, "Enable Hierarchical Z on gen6+")
66 DRI_CONF_SECTION_QUALITY
67 DRI_CONF_FORCE_S3TC_ENABLE("false")
69 DRI_CONF_OPT_BEGIN(clamp_max_samples
, int, -1)
70 DRI_CONF_DESC(en
, "Clamp the value of GL_MAX_SAMPLES to the "
71 "given integer. If negative, then do not clamp.")
75 DRI_CONF_SECTION_DEBUG
76 DRI_CONF_NO_RAST("false")
77 DRI_CONF_ALWAYS_FLUSH_BATCH("false")
78 DRI_CONF_ALWAYS_FLUSH_CACHE("false")
79 DRI_CONF_DISABLE_THROTTLING("false")
80 DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
81 DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
82 DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
83 DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
85 DRI_CONF_OPT_BEGIN_B(shader_precompile
, "true")
86 DRI_CONF_DESC(en
, "Perform code generation at shader link time.")
92 #include "intel_batchbuffer.h"
93 #include "intel_buffers.h"
94 #include "intel_bufmgr.h"
95 #include "intel_fbo.h"
96 #include "intel_mipmap_tree.h"
97 #include "intel_screen.h"
98 #include "intel_tex.h"
99 #include "intel_image.h"
101 #include "brw_context.h"
103 #include "i915_drm.h"
106 * For debugging purposes, this returns a time in seconds.
113 clock_gettime(CLOCK_MONOTONIC
, &tp
);
115 return tp
.tv_sec
+ tp
.tv_nsec
/ 1000000000.0;
119 aub_dump_bmp(struct gl_context
*ctx
)
121 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
123 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
124 struct intel_renderbuffer
*irb
=
125 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
127 if (irb
&& irb
->mt
) {
128 enum aub_dump_bmp_format format
;
130 switch (irb
->Base
.Base
.Format
) {
131 case MESA_FORMAT_B8G8R8A8_UNORM
:
132 case MESA_FORMAT_B8G8R8X8_UNORM
:
133 format
= AUB_DUMP_BMP_FORMAT_ARGB_8888
;
139 drm_intel_gem_bo_aub_dump_bmp(irb
->mt
->bo
,
142 irb
->Base
.Base
.Width
,
143 irb
->Base
.Base
.Height
,
151 static const __DRItexBufferExtension intelTexBufferExtension
= {
152 .base
= { __DRI_TEX_BUFFER
, 3 },
154 .setTexBuffer
= intelSetTexBuffer
,
155 .setTexBuffer2
= intelSetTexBuffer2
,
156 .releaseTexBuffer
= NULL
,
160 intel_dri2_flush_with_flags(__DRIcontext
*cPriv
,
161 __DRIdrawable
*dPriv
,
163 enum __DRI2throttleReason reason
)
165 struct brw_context
*brw
= cPriv
->driverPrivate
;
170 struct gl_context
*ctx
= &brw
->ctx
;
172 FLUSH_VERTICES(ctx
, 0);
174 if (flags
& __DRI2_FLUSH_DRAWABLE
)
175 intel_resolve_for_dri2_flush(brw
, dPriv
);
177 if (reason
== __DRI2_THROTTLE_SWAPBUFFER
)
178 brw
->need_swap_throttle
= true;
179 if (reason
== __DRI2_THROTTLE_FLUSHFRONT
)
180 brw
->need_flush_throttle
= true;
182 intel_batchbuffer_flush(brw
);
184 if (INTEL_DEBUG
& DEBUG_AUB
) {
190 * Provides compatibility with loaders that only support the older (version
191 * 1-3) flush interface.
193 * That includes libGL up to Mesa 9.0, and the X Server at least up to 1.13.
196 intel_dri2_flush(__DRIdrawable
*drawable
)
198 intel_dri2_flush_with_flags(drawable
->driContextPriv
, drawable
,
199 __DRI2_FLUSH_DRAWABLE
,
200 __DRI2_THROTTLE_SWAPBUFFER
);
203 static const struct __DRI2flushExtensionRec intelFlushExtension
= {
204 .base
= { __DRI2_FLUSH
, 4 },
206 .flush
= intel_dri2_flush
,
207 .invalidate
= dri2InvalidateDrawable
,
208 .flush_with_flags
= intel_dri2_flush_with_flags
,
211 static struct intel_image_format intel_image_formats
[] = {
212 { __DRI_IMAGE_FOURCC_ARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
213 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } },
215 { __DRI_IMAGE_FOURCC_ABGR8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
216 { { 0, 0, 0, __DRI_IMAGE_FORMAT_ABGR8888
, 4 } } },
218 { __DRI_IMAGE_FOURCC_SARGB8888
, __DRI_IMAGE_COMPONENTS_RGBA
, 1,
219 { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8
, 4 } } },
221 { __DRI_IMAGE_FOURCC_XRGB8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
222 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB8888
, 4 }, } },
224 { __DRI_IMAGE_FOURCC_XBGR8888
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
225 { { 0, 0, 0, __DRI_IMAGE_FORMAT_XBGR8888
, 4 }, } },
227 { __DRI_IMAGE_FOURCC_RGB565
, __DRI_IMAGE_COMPONENTS_RGB
, 1,
228 { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565
, 2 } } },
230 { __DRI_IMAGE_FOURCC_R8
, __DRI_IMAGE_COMPONENTS_R
, 1,
231 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 }, } },
233 { __DRI_IMAGE_FOURCC_GR88
, __DRI_IMAGE_COMPONENTS_RG
, 1,
234 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 }, } },
236 { __DRI_IMAGE_FOURCC_YUV410
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
237 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
238 { 1, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 },
239 { 2, 2, 2, __DRI_IMAGE_FORMAT_R8
, 1 } } },
241 { __DRI_IMAGE_FOURCC_YUV411
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
242 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
243 { 1, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
244 { 2, 2, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
246 { __DRI_IMAGE_FOURCC_YUV420
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
247 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
248 { 1, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 },
249 { 2, 1, 1, __DRI_IMAGE_FORMAT_R8
, 1 } } },
251 { __DRI_IMAGE_FOURCC_YUV422
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
252 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
253 { 1, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
254 { 2, 1, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
256 { __DRI_IMAGE_FOURCC_YUV444
, __DRI_IMAGE_COMPONENTS_Y_U_V
, 3,
257 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
258 { 1, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
259 { 2, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 } } },
261 { __DRI_IMAGE_FOURCC_NV12
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
262 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
263 { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
265 { __DRI_IMAGE_FOURCC_NV16
, __DRI_IMAGE_COMPONENTS_Y_UV
, 2,
266 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8
, 1 },
267 { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88
, 2 } } },
269 /* For YUYV buffers, we set up two overlapping DRI images and treat
270 * them as planar buffers in the compositors. Plane 0 is GR88 and
271 * samples YU or YV pairs and places Y into the R component, while
272 * plane 1 is ARGB and samples YUYV clusters and places pairs and
273 * places U into the G component and V into A. This lets the
274 * texture sampler interpolate the Y components correctly when
275 * sampling from plane 0, and interpolate U and V correctly when
276 * sampling from plane 1. */
277 { __DRI_IMAGE_FOURCC_YUYV
, __DRI_IMAGE_COMPONENTS_Y_XUXV
, 2,
278 { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88
, 2 },
279 { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB8888
, 4 } } }
283 intel_image_warn_if_unaligned(__DRIimage
*image
, const char *func
)
285 uint32_t tiling
, swizzle
;
286 drm_intel_bo_get_tiling(image
->bo
, &tiling
, &swizzle
);
288 if (tiling
!= I915_TILING_NONE
&& (image
->offset
& 0xfff)) {
289 _mesa_warning(NULL
, "%s: offset 0x%08x not on tile boundary",
290 func
, image
->offset
);
294 static struct intel_image_format
*
295 intel_image_format_lookup(int fourcc
)
297 struct intel_image_format
*f
= NULL
;
299 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
300 if (intel_image_formats
[i
].fourcc
== fourcc
) {
301 f
= &intel_image_formats
[i
];
309 static boolean
intel_lookup_fourcc(int dri_format
, int *fourcc
)
311 for (unsigned i
= 0; i
< ARRAY_SIZE(intel_image_formats
); i
++) {
312 if (intel_image_formats
[i
].planes
[0].dri_format
== dri_format
) {
313 *fourcc
= intel_image_formats
[i
].fourcc
;
321 intel_allocate_image(int dri_format
, void *loaderPrivate
)
325 image
= calloc(1, sizeof *image
);
329 image
->dri_format
= dri_format
;
332 image
->format
= driImageFormatToGLFormat(dri_format
);
333 if (dri_format
!= __DRI_IMAGE_FORMAT_NONE
&&
334 image
->format
== MESA_FORMAT_NONE
) {
339 image
->internal_format
= _mesa_get_format_base_format(image
->format
);
340 image
->data
= loaderPrivate
;
346 * Sets up a DRIImage structure to point to a slice out of a miptree.
349 intel_setup_image_from_mipmap_tree(struct brw_context
*brw
, __DRIimage
*image
,
350 struct intel_mipmap_tree
*mt
, GLuint level
,
353 intel_miptree_make_shareable(brw
, mt
);
355 intel_miptree_check_level_layer(mt
, level
, zoffset
);
357 image
->width
= minify(mt
->physical_width0
, level
- mt
->first_level
);
358 image
->height
= minify(mt
->physical_height0
, level
- mt
->first_level
);
359 image
->pitch
= mt
->pitch
;
361 image
->offset
= intel_miptree_get_tile_offsets(mt
, level
, zoffset
,
365 drm_intel_bo_unreference(image
->bo
);
367 drm_intel_bo_reference(mt
->bo
);
371 intel_create_image_from_name(__DRIscreen
*screen
,
372 int width
, int height
, int format
,
373 int name
, int pitch
, void *loaderPrivate
)
375 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
379 image
= intel_allocate_image(format
, loaderPrivate
);
383 if (image
->format
== MESA_FORMAT_NONE
)
386 cpp
= _mesa_get_format_bytes(image
->format
);
388 image
->width
= width
;
389 image
->height
= height
;
390 image
->pitch
= pitch
* cpp
;
391 image
->bo
= drm_intel_bo_gem_create_from_name(intelScreen
->bufmgr
, "image",
402 intel_create_image_from_renderbuffer(__DRIcontext
*context
,
403 int renderbuffer
, void *loaderPrivate
)
406 struct brw_context
*brw
= context
->driverPrivate
;
407 struct gl_context
*ctx
= &brw
->ctx
;
408 struct gl_renderbuffer
*rb
;
409 struct intel_renderbuffer
*irb
;
411 rb
= _mesa_lookup_renderbuffer(ctx
, renderbuffer
);
413 _mesa_error(ctx
, GL_INVALID_OPERATION
, "glRenderbufferExternalMESA");
417 irb
= intel_renderbuffer(rb
);
418 intel_miptree_make_shareable(brw
, irb
->mt
);
419 image
= calloc(1, sizeof *image
);
423 image
->internal_format
= rb
->InternalFormat
;
424 image
->format
= rb
->Format
;
426 image
->data
= loaderPrivate
;
427 drm_intel_bo_unreference(image
->bo
);
428 image
->bo
= irb
->mt
->bo
;
429 drm_intel_bo_reference(irb
->mt
->bo
);
430 image
->width
= rb
->Width
;
431 image
->height
= rb
->Height
;
432 image
->pitch
= irb
->mt
->pitch
;
433 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
434 image
->has_depthstencil
= irb
->mt
->stencil_mt
? true : false;
436 rb
->NeedsFinishRenderTexture
= true;
441 intel_create_image_from_texture(__DRIcontext
*context
, int target
,
442 unsigned texture
, int zoffset
,
448 struct brw_context
*brw
= context
->driverPrivate
;
449 struct gl_texture_object
*obj
;
450 struct intel_texture_object
*iobj
;
453 obj
= _mesa_lookup_texture(&brw
->ctx
, texture
);
454 if (!obj
|| obj
->Target
!= target
) {
455 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
459 if (target
== GL_TEXTURE_CUBE_MAP
)
462 _mesa_test_texobj_completeness(&brw
->ctx
, obj
);
463 iobj
= intel_texture_object(obj
);
464 if (!obj
->_BaseComplete
|| (level
> 0 && !obj
->_MipmapComplete
)) {
465 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
469 if (level
< obj
->BaseLevel
|| level
> obj
->_MaxLevel
) {
470 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
474 if (target
== GL_TEXTURE_3D
&& obj
->Image
[face
][level
]->Depth
< zoffset
) {
475 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
478 image
= calloc(1, sizeof *image
);
480 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
484 image
->internal_format
= obj
->Image
[face
][level
]->InternalFormat
;
485 image
->format
= obj
->Image
[face
][level
]->TexFormat
;
486 image
->data
= loaderPrivate
;
487 intel_setup_image_from_mipmap_tree(brw
, image
, iobj
->mt
, level
, zoffset
);
488 image
->dri_format
= driGLFormatToImageFormat(image
->format
);
489 image
->has_depthstencil
= iobj
->mt
->stencil_mt
? true : false;
490 if (image
->dri_format
== MESA_FORMAT_NONE
) {
491 *error
= __DRI_IMAGE_ERROR_BAD_PARAMETER
;
496 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
501 intel_destroy_image(__DRIimage
*image
)
503 drm_intel_bo_unreference(image
->bo
);
508 intel_create_image(__DRIscreen
*screen
,
509 int width
, int height
, int format
,
514 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
519 tiling
= I915_TILING_X
;
520 if (use
& __DRI_IMAGE_USE_CURSOR
) {
521 if (width
!= 64 || height
!= 64)
523 tiling
= I915_TILING_NONE
;
526 if (use
& __DRI_IMAGE_USE_LINEAR
)
527 tiling
= I915_TILING_NONE
;
529 image
= intel_allocate_image(format
, loaderPrivate
);
534 cpp
= _mesa_get_format_bytes(image
->format
);
535 image
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
, "image",
536 width
, height
, cpp
, &tiling
,
538 if (image
->bo
== NULL
) {
542 image
->width
= width
;
543 image
->height
= height
;
544 image
->pitch
= pitch
;
550 intel_query_image(__DRIimage
*image
, int attrib
, int *value
)
553 case __DRI_IMAGE_ATTRIB_STRIDE
:
554 *value
= image
->pitch
;
556 case __DRI_IMAGE_ATTRIB_HANDLE
:
557 *value
= image
->bo
->handle
;
559 case __DRI_IMAGE_ATTRIB_NAME
:
560 return !drm_intel_bo_flink(image
->bo
, (uint32_t *) value
);
561 case __DRI_IMAGE_ATTRIB_FORMAT
:
562 *value
= image
->dri_format
;
564 case __DRI_IMAGE_ATTRIB_WIDTH
:
565 *value
= image
->width
;
567 case __DRI_IMAGE_ATTRIB_HEIGHT
:
568 *value
= image
->height
;
570 case __DRI_IMAGE_ATTRIB_COMPONENTS
:
571 if (image
->planar_format
== NULL
)
573 *value
= image
->planar_format
->components
;
575 case __DRI_IMAGE_ATTRIB_FD
:
576 if (drm_intel_bo_gem_export_to_prime(image
->bo
, value
) == 0)
579 case __DRI_IMAGE_ATTRIB_FOURCC
:
580 if (intel_lookup_fourcc(image
->dri_format
, value
))
583 case __DRI_IMAGE_ATTRIB_NUM_PLANES
:
593 intel_dup_image(__DRIimage
*orig_image
, void *loaderPrivate
)
597 image
= calloc(1, sizeof *image
);
601 drm_intel_bo_reference(orig_image
->bo
);
602 image
->bo
= orig_image
->bo
;
603 image
->internal_format
= orig_image
->internal_format
;
604 image
->planar_format
= orig_image
->planar_format
;
605 image
->dri_format
= orig_image
->dri_format
;
606 image
->format
= orig_image
->format
;
607 image
->offset
= orig_image
->offset
;
608 image
->width
= orig_image
->width
;
609 image
->height
= orig_image
->height
;
610 image
->pitch
= orig_image
->pitch
;
611 image
->tile_x
= orig_image
->tile_x
;
612 image
->tile_y
= orig_image
->tile_y
;
613 image
->has_depthstencil
= orig_image
->has_depthstencil
;
614 image
->data
= loaderPrivate
;
616 memcpy(image
->strides
, orig_image
->strides
, sizeof(image
->strides
));
617 memcpy(image
->offsets
, orig_image
->offsets
, sizeof(image
->offsets
));
623 intel_validate_usage(__DRIimage
*image
, unsigned int use
)
625 if (use
& __DRI_IMAGE_USE_CURSOR
) {
626 if (image
->width
!= 64 || image
->height
!= 64)
634 intel_create_image_from_names(__DRIscreen
*screen
,
635 int width
, int height
, int fourcc
,
636 int *names
, int num_names
,
637 int *strides
, int *offsets
,
640 struct intel_image_format
*f
= NULL
;
644 if (screen
== NULL
|| names
== NULL
|| num_names
!= 1)
647 f
= intel_image_format_lookup(fourcc
);
651 image
= intel_create_image_from_name(screen
, width
, height
,
652 __DRI_IMAGE_FORMAT_NONE
,
653 names
[0], strides
[0],
659 image
->planar_format
= f
;
660 for (i
= 0; i
< f
->nplanes
; i
++) {
661 index
= f
->planes
[i
].buffer_index
;
662 image
->offsets
[index
] = offsets
[index
];
663 image
->strides
[index
] = strides
[index
];
670 intel_create_image_from_fds(__DRIscreen
*screen
,
671 int width
, int height
, int fourcc
,
672 int *fds
, int num_fds
, int *strides
, int *offsets
,
675 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
676 struct intel_image_format
*f
;
680 if (fds
== NULL
|| num_fds
!= 1)
683 f
= intel_image_format_lookup(fourcc
);
688 image
= intel_allocate_image(f
->planes
[0].dri_format
, loaderPrivate
);
690 image
= intel_allocate_image(__DRI_IMAGE_FORMAT_NONE
, loaderPrivate
);
695 image
->bo
= drm_intel_bo_gem_create_from_prime(intelScreen
->bufmgr
,
697 height
* strides
[0]);
698 if (image
->bo
== NULL
) {
702 image
->width
= width
;
703 image
->height
= height
;
704 image
->pitch
= strides
[0];
706 image
->planar_format
= f
;
707 for (i
= 0; i
< f
->nplanes
; i
++) {
708 index
= f
->planes
[i
].buffer_index
;
709 image
->offsets
[index
] = offsets
[index
];
710 image
->strides
[index
] = strides
[index
];
713 if (f
->nplanes
== 1) {
714 image
->offset
= image
->offsets
[0];
715 intel_image_warn_if_unaligned(image
, __func__
);
722 intel_create_image_from_dma_bufs(__DRIscreen
*screen
,
723 int width
, int height
, int fourcc
,
724 int *fds
, int num_fds
,
725 int *strides
, int *offsets
,
726 enum __DRIYUVColorSpace yuv_color_space
,
727 enum __DRISampleRange sample_range
,
728 enum __DRIChromaSiting horizontal_siting
,
729 enum __DRIChromaSiting vertical_siting
,
734 struct intel_image_format
*f
= intel_image_format_lookup(fourcc
);
736 /* For now only packed formats that have native sampling are supported. */
737 if (!f
|| f
->nplanes
!= 1) {
738 *error
= __DRI_IMAGE_ERROR_BAD_MATCH
;
742 image
= intel_create_image_from_fds(screen
, width
, height
, fourcc
, fds
,
743 num_fds
, strides
, offsets
,
747 * Invalid parameters and any inconsistencies between are assumed to be
748 * checked by the caller. Therefore besides unsupported formats one can fail
749 * only in allocation.
752 *error
= __DRI_IMAGE_ERROR_BAD_ALLOC
;
756 image
->dma_buf_imported
= true;
757 image
->yuv_color_space
= yuv_color_space
;
758 image
->sample_range
= sample_range
;
759 image
->horizontal_siting
= horizontal_siting
;
760 image
->vertical_siting
= vertical_siting
;
762 *error
= __DRI_IMAGE_ERROR_SUCCESS
;
767 intel_from_planar(__DRIimage
*parent
, int plane
, void *loaderPrivate
)
769 int width
, height
, offset
, stride
, dri_format
, index
;
770 struct intel_image_format
*f
;
773 if (parent
== NULL
|| parent
->planar_format
== NULL
)
776 f
= parent
->planar_format
;
778 if (plane
>= f
->nplanes
)
781 width
= parent
->width
>> f
->planes
[plane
].width_shift
;
782 height
= parent
->height
>> f
->planes
[plane
].height_shift
;
783 dri_format
= f
->planes
[plane
].dri_format
;
784 index
= f
->planes
[plane
].buffer_index
;
785 offset
= parent
->offsets
[index
];
786 stride
= parent
->strides
[index
];
788 image
= intel_allocate_image(dri_format
, loaderPrivate
);
792 if (offset
+ height
* stride
> parent
->bo
->size
) {
793 _mesa_warning(NULL
, "intel_create_sub_image: subimage out of bounds");
798 image
->bo
= parent
->bo
;
799 drm_intel_bo_reference(parent
->bo
);
801 image
->width
= width
;
802 image
->height
= height
;
803 image
->pitch
= stride
;
804 image
->offset
= offset
;
806 intel_image_warn_if_unaligned(image
, __func__
);
811 static const __DRIimageExtension intelImageExtension
= {
812 .base
= { __DRI_IMAGE
, 11 },
814 .createImageFromName
= intel_create_image_from_name
,
815 .createImageFromRenderbuffer
= intel_create_image_from_renderbuffer
,
816 .destroyImage
= intel_destroy_image
,
817 .createImage
= intel_create_image
,
818 .queryImage
= intel_query_image
,
819 .dupImage
= intel_dup_image
,
820 .validateUsage
= intel_validate_usage
,
821 .createImageFromNames
= intel_create_image_from_names
,
822 .fromPlanar
= intel_from_planar
,
823 .createImageFromTexture
= intel_create_image_from_texture
,
824 .createImageFromFds
= intel_create_image_from_fds
,
825 .createImageFromDmaBufs
= intel_create_image_from_dma_bufs
,
827 .getCapabilities
= NULL
831 brw_query_renderer_integer(__DRIscreen
*psp
, int param
, unsigned int *value
)
833 const struct intel_screen
*const intelScreen
=
834 (struct intel_screen
*) psp
->driverPrivate
;
837 case __DRI2_RENDERER_VENDOR_ID
:
840 case __DRI2_RENDERER_DEVICE_ID
:
841 value
[0] = intelScreen
->deviceID
;
843 case __DRI2_RENDERER_ACCELERATED
:
846 case __DRI2_RENDERER_VIDEO_MEMORY
: {
847 /* Once a batch uses more than 75% of the maximum mappable size, we
848 * assume that there's some fragmentation, and we start doing extra
849 * flushing, etc. That's the big cliff apps will care about.
852 size_t mappable_size
;
854 drm_intel_get_aperture_sizes(psp
->fd
, &mappable_size
, &aper_size
);
856 const unsigned gpu_mappable_megabytes
=
857 (aper_size
/ (1024 * 1024)) * 3 / 4;
859 const long system_memory_pages
= sysconf(_SC_PHYS_PAGES
);
860 const long system_page_size
= sysconf(_SC_PAGE_SIZE
);
862 if (system_memory_pages
<= 0 || system_page_size
<= 0)
865 const uint64_t system_memory_bytes
= (uint64_t) system_memory_pages
866 * (uint64_t) system_page_size
;
868 const unsigned system_memory_megabytes
=
869 (unsigned) (system_memory_bytes
/ (1024 * 1024));
871 value
[0] = MIN2(system_memory_megabytes
, gpu_mappable_megabytes
);
874 case __DRI2_RENDERER_UNIFIED_MEMORY_ARCHITECTURE
:
878 return driQueryRendererIntegerCommon(psp
, param
, value
);
885 brw_query_renderer_string(__DRIscreen
*psp
, int param
, const char **value
)
887 const struct intel_screen
*intelScreen
=
888 (struct intel_screen
*) psp
->driverPrivate
;
891 case __DRI2_RENDERER_VENDOR_ID
:
892 value
[0] = brw_vendor_string
;
894 case __DRI2_RENDERER_DEVICE_ID
:
895 value
[0] = brw_get_renderer_string(intelScreen
->deviceID
);
904 static const __DRI2rendererQueryExtension intelRendererQueryExtension
= {
905 .base
= { __DRI2_RENDERER_QUERY
, 1 },
907 .queryInteger
= brw_query_renderer_integer
,
908 .queryString
= brw_query_renderer_string
911 static const __DRIrobustnessExtension dri2Robustness
= {
912 .base
= { __DRI2_ROBUSTNESS
, 1 }
915 static const __DRIextension
*intelScreenExtensions
[] = {
916 &intelTexBufferExtension
.base
,
917 &intelFenceExtension
.base
,
918 &intelFlushExtension
.base
,
919 &intelImageExtension
.base
,
920 &intelRendererQueryExtension
.base
,
921 &dri2ConfigQueryExtension
.base
,
925 static const __DRIextension
*intelRobustScreenExtensions
[] = {
926 &intelTexBufferExtension
.base
,
927 &intelFenceExtension
.base
,
928 &intelFlushExtension
.base
,
929 &intelImageExtension
.base
,
930 &intelRendererQueryExtension
.base
,
931 &dri2ConfigQueryExtension
.base
,
932 &dri2Robustness
.base
,
937 intel_get_param(__DRIscreen
*psp
, int param
, int *value
)
940 struct drm_i915_getparam gp
;
942 memset(&gp
, 0, sizeof(gp
));
946 ret
= drmCommandWriteRead(psp
->fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
949 _mesa_warning(NULL
, "drm_i915_getparam: %d", ret
);
957 intel_get_boolean(__DRIscreen
*psp
, int param
)
960 return intel_get_param(psp
, param
, &value
) && value
;
964 intelDestroyScreen(__DRIscreen
* sPriv
)
966 struct intel_screen
*intelScreen
= sPriv
->driverPrivate
;
968 dri_bufmgr_destroy(intelScreen
->bufmgr
);
969 driDestroyOptionInfo(&intelScreen
->optionCache
);
971 ralloc_free(intelScreen
);
972 sPriv
->driverPrivate
= NULL
;
977 * This is called when we need to set up GL rendering to a new X window.
980 intelCreateBuffer(__DRIscreen
* driScrnPriv
,
981 __DRIdrawable
* driDrawPriv
,
982 const struct gl_config
* mesaVis
, GLboolean isPixmap
)
984 struct intel_renderbuffer
*rb
;
985 struct intel_screen
*screen
= (struct intel_screen
*) driScrnPriv
->driverPrivate
;
986 mesa_format rgbFormat
;
987 unsigned num_samples
= intel_quantize_num_samples(screen
, mesaVis
->samples
);
988 struct gl_framebuffer
*fb
;
993 fb
= CALLOC_STRUCT(gl_framebuffer
);
997 _mesa_initialize_window_framebuffer(fb
, mesaVis
);
999 if (screen
->winsys_msaa_samples_override
!= -1) {
1000 num_samples
= screen
->winsys_msaa_samples_override
;
1001 fb
->Visual
.samples
= num_samples
;
1004 if (mesaVis
->redBits
== 5)
1005 rgbFormat
= MESA_FORMAT_B5G6R5_UNORM
;
1006 else if (mesaVis
->sRGBCapable
)
1007 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
1008 else if (mesaVis
->alphaBits
== 0)
1009 rgbFormat
= MESA_FORMAT_B8G8R8X8_UNORM
;
1011 rgbFormat
= MESA_FORMAT_B8G8R8A8_SRGB
;
1012 fb
->Visual
.sRGBCapable
= true;
1015 /* setup the hardware-based renderbuffers */
1016 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1017 _mesa_add_renderbuffer(fb
, BUFFER_FRONT_LEFT
, &rb
->Base
.Base
);
1019 if (mesaVis
->doubleBufferMode
) {
1020 rb
= intel_create_renderbuffer(rgbFormat
, num_samples
);
1021 _mesa_add_renderbuffer(fb
, BUFFER_BACK_LEFT
, &rb
->Base
.Base
);
1025 * Assert here that the gl_config has an expected depth/stencil bit
1026 * combination: one of d24/s8, d16/s0, d0/s0. (See intelInitScreen2(),
1027 * which constructs the advertised configs.)
1029 if (mesaVis
->depthBits
== 24) {
1030 assert(mesaVis
->stencilBits
== 8);
1032 if (screen
->devinfo
->has_hiz_and_separate_stencil
) {
1033 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT
,
1035 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1036 rb
= intel_create_private_renderbuffer(MESA_FORMAT_S_UINT8
,
1038 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1041 * Use combined depth/stencil. Note that the renderbuffer is
1042 * attached to two attachment points.
1044 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_S8_UINT
,
1046 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1047 _mesa_add_renderbuffer(fb
, BUFFER_STENCIL
, &rb
->Base
.Base
);
1050 else if (mesaVis
->depthBits
== 16) {
1051 assert(mesaVis
->stencilBits
== 0);
1052 rb
= intel_create_private_renderbuffer(MESA_FORMAT_Z_UNORM16
,
1054 _mesa_add_renderbuffer(fb
, BUFFER_DEPTH
, &rb
->Base
.Base
);
1057 assert(mesaVis
->depthBits
== 0);
1058 assert(mesaVis
->stencilBits
== 0);
1061 /* now add any/all software-based renderbuffers we may need */
1062 _swrast_add_soft_renderbuffers(fb
,
1063 false, /* never sw color */
1064 false, /* never sw depth */
1065 false, /* never sw stencil */
1066 mesaVis
->accumRedBits
> 0,
1067 false, /* never sw alpha */
1068 false /* never sw aux */ );
1069 driDrawPriv
->driverPrivate
= fb
;
1075 intelDestroyBuffer(__DRIdrawable
* driDrawPriv
)
1077 struct gl_framebuffer
*fb
= driDrawPriv
->driverPrivate
;
1079 _mesa_reference_framebuffer(&fb
, NULL
);
1083 intel_init_bufmgr(struct intel_screen
*intelScreen
)
1085 __DRIscreen
*spriv
= intelScreen
->driScrnPriv
;
1087 intelScreen
->no_hw
= getenv("INTEL_NO_HW") != NULL
;
1089 intelScreen
->bufmgr
= intel_bufmgr_gem_init(spriv
->fd
, BATCH_SZ
);
1090 if (intelScreen
->bufmgr
== NULL
) {
1091 fprintf(stderr
, "[%s:%u] Error initializing buffer manager.\n",
1092 __func__
, __LINE__
);
1096 drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen
->bufmgr
);
1098 if (!intel_get_boolean(spriv
, I915_PARAM_HAS_RELAXED_DELTA
)) {
1099 fprintf(stderr
, "[%s: %u] Kernel 2.6.39 required.\n", __func__
, __LINE__
);
1107 intel_detect_swizzling(struct intel_screen
*screen
)
1109 drm_intel_bo
*buffer
;
1110 unsigned long flags
= 0;
1111 unsigned long aligned_pitch
;
1112 uint32_t tiling
= I915_TILING_X
;
1113 uint32_t swizzle_mode
= 0;
1115 buffer
= drm_intel_bo_alloc_tiled(screen
->bufmgr
, "swizzle test",
1117 &tiling
, &aligned_pitch
, flags
);
1121 drm_intel_bo_get_tiling(buffer
, &tiling
, &swizzle_mode
);
1122 drm_intel_bo_unreference(buffer
);
1124 if (swizzle_mode
== I915_BIT_6_SWIZZLE_NONE
)
1131 intel_detect_timestamp(struct intel_screen
*screen
)
1133 uint64_t dummy
= 0, last
= 0;
1134 int upper
, lower
, loops
;
1136 /* On 64bit systems, some old kernels trigger a hw bug resulting in the
1137 * TIMESTAMP register being shifted and the low 32bits always zero.
1139 * More recent kernels offer an interface to read the full 36bits
1142 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
| 1, &dummy
) == 0)
1145 /* Determine if we have a 32bit or 64bit kernel by inspecting the
1146 * upper 32bits for a rapidly changing timestamp.
1148 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &last
))
1152 for (loops
= 0; loops
< 10; loops
++) {
1153 /* The TIMESTAMP should change every 80ns, so several round trips
1154 * through the kernel should be enough to advance it.
1156 if (drm_intel_reg_read(screen
->bufmgr
, TIMESTAMP
, &dummy
))
1159 upper
+= (dummy
>> 32) != (last
>> 32);
1160 if (upper
> 1) /* beware 32bit counter overflow */
1161 return 2; /* upper dword holds the low 32bits of the timestamp */
1163 lower
+= (dummy
& 0xffffffff) != (last
& 0xffffffff);
1165 return 1; /* timestamp is unshifted */
1170 /* No advancement? No timestamp! */
1175 * Return array of MSAA modes supported by the hardware. The array is
1176 * zero-terminated and sorted in decreasing order.
1179 intel_supported_msaa_modes(const struct intel_screen
*screen
)
1181 static const int gen8_modes
[] = {8, 4, 2, 0, -1};
1182 static const int gen7_modes
[] = {8, 4, 0, -1};
1183 static const int gen6_modes
[] = {4, 0, -1};
1184 static const int gen4_modes
[] = {0, -1};
1186 if (screen
->devinfo
->gen
>= 8) {
1188 } else if (screen
->devinfo
->gen
>= 7) {
1190 } else if (screen
->devinfo
->gen
== 6) {
1197 static __DRIconfig
**
1198 intel_screen_make_configs(__DRIscreen
*dri_screen
)
1200 static const mesa_format formats
[] = {
1201 MESA_FORMAT_B5G6R5_UNORM
,
1202 MESA_FORMAT_B8G8R8A8_UNORM
,
1203 MESA_FORMAT_B8G8R8X8_UNORM
1206 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */
1207 static const GLenum back_buffer_modes
[] = {
1208 GLX_SWAP_UNDEFINED_OML
, GLX_NONE
,
1211 static const uint8_t singlesample_samples
[1] = {0};
1212 static const uint8_t multisample_samples
[2] = {4, 8};
1214 struct intel_screen
*screen
= dri_screen
->driverPrivate
;
1215 const struct brw_device_info
*devinfo
= screen
->devinfo
;
1216 uint8_t depth_bits
[4], stencil_bits
[4];
1217 __DRIconfig
**configs
= NULL
;
1219 /* Generate singlesample configs without accumulation buffer. */
1220 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1221 __DRIconfig
**new_configs
;
1222 int num_depth_stencil_bits
= 2;
1224 /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
1225 * buffer that has a different number of bits per pixel than the color
1226 * buffer, gen >= 6 supports this.
1229 stencil_bits
[0] = 0;
1231 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1233 stencil_bits
[1] = 0;
1234 if (devinfo
->gen
>= 6) {
1236 stencil_bits
[2] = 8;
1237 num_depth_stencil_bits
= 3;
1241 stencil_bits
[1] = 8;
1244 new_configs
= driCreateConfigs(formats
[i
],
1247 num_depth_stencil_bits
,
1248 back_buffer_modes
, 2,
1249 singlesample_samples
, 1,
1251 configs
= driConcatConfigs(configs
, new_configs
);
1254 /* Generate the minimum possible set of configs that include an
1255 * accumulation buffer.
1257 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1258 __DRIconfig
**new_configs
;
1260 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1262 stencil_bits
[0] = 0;
1265 stencil_bits
[0] = 8;
1268 new_configs
= driCreateConfigs(formats
[i
],
1269 depth_bits
, stencil_bits
, 1,
1270 back_buffer_modes
, 1,
1271 singlesample_samples
, 1,
1273 configs
= driConcatConfigs(configs
, new_configs
);
1276 /* Generate multisample configs.
1278 * This loop breaks early, and hence is a no-op, on gen < 6.
1280 * Multisample configs must follow the singlesample configs in order to
1281 * work around an X server bug present in 1.12. The X server chooses to
1282 * associate the first listed RGBA888-Z24S8 config, regardless of its
1283 * sample count, with the 32-bit depth visual used for compositing.
1285 * Only doublebuffer configs with GLX_SWAP_UNDEFINED_OML behavior are
1286 * supported. Singlebuffer configs are not supported because no one wants
1289 for (unsigned i
= 0; i
< ARRAY_SIZE(formats
); i
++) {
1290 if (devinfo
->gen
< 6)
1293 __DRIconfig
**new_configs
;
1294 const int num_depth_stencil_bits
= 2;
1295 int num_msaa_modes
= 0;
1298 stencil_bits
[0] = 0;
1300 if (formats
[i
] == MESA_FORMAT_B5G6R5_UNORM
) {
1302 stencil_bits
[1] = 0;
1305 stencil_bits
[1] = 8;
1308 if (devinfo
->gen
>= 7)
1310 else if (devinfo
->gen
== 6)
1313 new_configs
= driCreateConfigs(formats
[i
],
1316 num_depth_stencil_bits
,
1317 back_buffer_modes
, 1,
1318 multisample_samples
,
1321 configs
= driConcatConfigs(configs
, new_configs
);
1324 if (configs
== NULL
) {
1325 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1334 set_max_gl_versions(struct intel_screen
*screen
)
1336 __DRIscreen
*psp
= screen
->driScrnPriv
;
1338 switch (screen
->devinfo
->gen
) {
1343 psp
->max_gl_core_version
= 33;
1344 psp
->max_gl_compat_version
= 30;
1345 psp
->max_gl_es1_version
= 11;
1346 psp
->max_gl_es2_version
= 30;
1350 psp
->max_gl_core_version
= 0;
1351 psp
->max_gl_compat_version
= 21;
1352 psp
->max_gl_es1_version
= 11;
1353 psp
->max_gl_es2_version
= 20;
1356 unreachable("unrecognized intel_screen::gen");
1361 brw_get_revision(int fd
)
1363 struct drm_i915_getparam gp
;
1367 memset(&gp
, 0, sizeof(gp
));
1368 gp
.param
= I915_PARAM_REVISION
;
1369 gp
.value
= &revision
;
1371 ret
= drmCommandWriteRead(fd
, DRM_I915_GETPARAM
, &gp
, sizeof(gp
));
1378 /* Drop when RS headers get pulled to libdrm */
1379 #ifndef I915_PARAM_HAS_RESOURCE_STREAMER
1380 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
1384 * This is the driver specific part of the createNewScreen entry point.
1385 * Called when using DRI2.
1387 * \return the struct gl_config supported by this driver
1390 __DRIconfig
**intelInitScreen2(__DRIscreen
*psp
)
1392 struct intel_screen
*intelScreen
;
1394 if (psp
->image
.loader
) {
1395 } else if (psp
->dri2
.loader
->base
.version
<= 2 ||
1396 psp
->dri2
.loader
->getBuffersWithFormat
== NULL
) {
1398 "\nERROR! DRI2 loader with getBuffersWithFormat() "
1399 "support required\n");
1403 /* Allocate the private area */
1404 intelScreen
= rzalloc(NULL
, struct intel_screen
);
1406 fprintf(stderr
, "\nERROR! Allocating private area failed\n");
1409 /* parse information in __driConfigOptions */
1410 driParseOptionInfo(&intelScreen
->optionCache
, brw_config_options
.xml
);
1412 intelScreen
->driScrnPriv
= psp
;
1413 psp
->driverPrivate
= (void *) intelScreen
;
1415 if (!intel_init_bufmgr(intelScreen
))
1418 intelScreen
->deviceID
= drm_intel_bufmgr_gem_get_devid(intelScreen
->bufmgr
);
1419 intelScreen
->devinfo
= brw_get_device_info(intelScreen
->deviceID
,
1420 brw_get_revision(psp
->fd
));
1421 if (!intelScreen
->devinfo
)
1424 brw_process_intel_debug_variable(intelScreen
);
1426 intelScreen
->hw_must_use_separate_stencil
= intelScreen
->devinfo
->gen
>= 7;
1428 intelScreen
->hw_has_swizzling
= intel_detect_swizzling(intelScreen
);
1429 intelScreen
->hw_has_timestamp
= intel_detect_timestamp(intelScreen
);
1431 const char *force_msaa
= getenv("INTEL_FORCE_MSAA");
1433 intelScreen
->winsys_msaa_samples_override
=
1434 intel_quantize_num_samples(intelScreen
, atoi(force_msaa
));
1435 printf("Forcing winsys sample count to %d\n",
1436 intelScreen
->winsys_msaa_samples_override
);
1438 intelScreen
->winsys_msaa_samples_override
= -1;
1441 set_max_gl_versions(intelScreen
);
1443 /* Notification of GPU resets requires hardware contexts and a kernel new
1444 * enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
1445 * supported, calling it with a context of 0 will either generate EPERM or
1446 * no error. If the ioctl is not supported, it always generate EINVAL.
1447 * Use this to determine whether to advertise the __DRI2_ROBUSTNESS
1448 * extension to the loader.
1450 * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
1452 if (intelScreen
->devinfo
->gen
>= 6) {
1453 struct drm_i915_reset_stats stats
;
1454 memset(&stats
, 0, sizeof(stats
));
1456 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GET_RESET_STATS
, &stats
);
1458 intelScreen
->has_context_reset_notification
=
1459 (ret
!= -1 || errno
!= EINVAL
);
1462 struct drm_i915_getparam getparam
;
1463 getparam
.param
= I915_PARAM_CMD_PARSER_VERSION
;
1464 getparam
.value
= &intelScreen
->cmd_parser_version
;
1465 const int ret
= drmIoctl(psp
->fd
, DRM_IOCTL_I915_GETPARAM
, &getparam
);
1467 intelScreen
->cmd_parser_version
= 0;
1469 psp
->extensions
= !intelScreen
->has_context_reset_notification
1470 ? intelScreenExtensions
: intelRobustScreenExtensions
;
1472 intelScreen
->compiler
= brw_compiler_create(intelScreen
,
1473 intelScreen
->devinfo
);
1475 if (intelScreen
->devinfo
->has_resource_streamer
) {
1477 getparam
.param
= I915_PARAM_HAS_RESOURCE_STREAMER
;
1478 getparam
.value
= &val
;
1480 drmIoctl(psp
->fd
, DRM_IOCTL_I915_GETPARAM
, &getparam
);
1481 intelScreen
->has_resource_streamer
= val
> 0;
1484 return (const __DRIconfig
**) intel_screen_make_configs(psp
);
1487 struct intel_buffer
{
1492 static __DRIbuffer
*
1493 intelAllocateBuffer(__DRIscreen
*screen
,
1494 unsigned attachment
, unsigned format
,
1495 int width
, int height
)
1497 struct intel_buffer
*intelBuffer
;
1498 struct intel_screen
*intelScreen
= screen
->driverPrivate
;
1500 assert(attachment
== __DRI_BUFFER_FRONT_LEFT
||
1501 attachment
== __DRI_BUFFER_BACK_LEFT
);
1503 intelBuffer
= calloc(1, sizeof *intelBuffer
);
1504 if (intelBuffer
== NULL
)
1507 /* The front and back buffers are color buffers, which are X tiled. */
1508 uint32_t tiling
= I915_TILING_X
;
1509 unsigned long pitch
;
1510 int cpp
= format
/ 8;
1511 intelBuffer
->bo
= drm_intel_bo_alloc_tiled(intelScreen
->bufmgr
,
1512 "intelAllocateBuffer",
1517 BO_ALLOC_FOR_RENDER
);
1519 if (intelBuffer
->bo
== NULL
) {
1524 drm_intel_bo_flink(intelBuffer
->bo
, &intelBuffer
->base
.name
);
1526 intelBuffer
->base
.attachment
= attachment
;
1527 intelBuffer
->base
.cpp
= cpp
;
1528 intelBuffer
->base
.pitch
= pitch
;
1530 return &intelBuffer
->base
;
1534 intelReleaseBuffer(__DRIscreen
*screen
, __DRIbuffer
*buffer
)
1536 struct intel_buffer
*intelBuffer
= (struct intel_buffer
*) buffer
;
1538 drm_intel_bo_unreference(intelBuffer
->bo
);
1542 static const struct __DriverAPIRec brw_driver_api
= {
1543 .InitScreen
= intelInitScreen2
,
1544 .DestroyScreen
= intelDestroyScreen
,
1545 .CreateContext
= brwCreateContext
,
1546 .DestroyContext
= intelDestroyContext
,
1547 .CreateBuffer
= intelCreateBuffer
,
1548 .DestroyBuffer
= intelDestroyBuffer
,
1549 .MakeCurrent
= intelMakeCurrent
,
1550 .UnbindContext
= intelUnbindContext
,
1551 .AllocateBuffer
= intelAllocateBuffer
,
1552 .ReleaseBuffer
= intelReleaseBuffer
1555 static const struct __DRIDriverVtableExtensionRec brw_vtable
= {
1556 .base
= { __DRI_DRIVER_VTABLE
, 1 },
1557 .vtable
= &brw_driver_api
,
1560 static const __DRIextension
*brw_driver_extensions
[] = {
1561 &driCoreExtension
.base
,
1562 &driImageDriverExtension
.base
,
1563 &driDRI2Extension
.base
,
1565 &brw_config_options
.base
,
1569 PUBLIC
const __DRIextension
**__driDriverGetExtensions_i965(void)
1571 globalDriverAPI
= &brw_driver_api
;
1573 return brw_driver_extensions
;